utility.cc revision 10474:799c8ee4ecba 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 */
31
32#include "arch/sparc/faults.hh"
33#include "arch/sparc/utility.hh"
34#include "arch/sparc/vtophys.hh"
35#include "mem/fs_translating_port_proxy.hh"
36
37namespace SparcISA {
38
39
40// The caller uses %o0-%05 for the first 6 arguments even if their floating
41// point. Double precision floating point values take two registers/args.
42// Quads, structs, and unions are passed as pointers. All arguments beyond
43// the sixth are passed on the stack past the 16 word window save area,
44// space for the struct/union return pointer, and space reserved for the
45// first 6 arguments which the caller may use but doesn't have to.
46uint64_t
47getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
48{
49    if (!FullSystem) {
50        panic("getArgument() only implemented for full system\n");
51        M5_DUMMY_RETURN
52    }
53
54    const int NumArgumentRegs = 6;
55    if (number < NumArgumentRegs) {
56        return tc->readIntReg(8 + number);
57    } else {
58        Addr sp = tc->readIntReg(StackPointerReg);
59        FSTranslatingPortProxy &vp = tc->getVirtProxy();
60        uint64_t arg = vp.read<uint64_t>(sp + 92 +
61                            (number-NumArgumentRegs) * sizeof(uint64_t));
62        return arg;
63    }
64}
65
66void
67copyMiscRegs(ThreadContext *src, ThreadContext *dest)
68{
69
70    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
71
72    // Read all the trap level dependent registers and save them off
73    for (int i = 1; i <= MaxTL; i++) {
74        src->setMiscRegNoEffect(MISCREG_TL, i);
75        dest->setMiscRegNoEffect(MISCREG_TL, i);
76
77        dest->setMiscRegNoEffect(MISCREG_TT,
78                src->readMiscRegNoEffect(MISCREG_TT));
79        dest->setMiscRegNoEffect(MISCREG_TPC,
80                src->readMiscRegNoEffect(MISCREG_TPC));
81        dest->setMiscRegNoEffect(MISCREG_TNPC,
82                src->readMiscRegNoEffect(MISCREG_TNPC));
83        dest->setMiscRegNoEffect(MISCREG_TSTATE,
84                src->readMiscRegNoEffect(MISCREG_TSTATE));
85    }
86
87    // Save off the traplevel
88    dest->setMiscRegNoEffect(MISCREG_TL, tl);
89    src->setMiscRegNoEffect(MISCREG_TL, tl);
90
91
92    // ASRs
93//    dest->setMiscRegNoEffect(MISCREG_Y,
94//            src->readMiscRegNoEffect(MISCREG_Y));
95//    dest->setMiscRegNoEffect(MISCREG_CCR,
96//            src->readMiscRegNoEffect(MISCREG_CCR));
97    dest->setMiscReg(MISCREG_ASI,
98            src->readMiscRegNoEffect(MISCREG_ASI));
99    dest->setMiscRegNoEffect(MISCREG_TICK,
100            src->readMiscRegNoEffect(MISCREG_TICK));
101    dest->setMiscRegNoEffect(MISCREG_FPRS,
102            src->readMiscRegNoEffect(MISCREG_FPRS));
103    dest->setMiscRegNoEffect(MISCREG_SOFTINT,
104            src->readMiscRegNoEffect(MISCREG_SOFTINT));
105    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
106            src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
107    dest->setMiscRegNoEffect(MISCREG_STICK,
108            src->readMiscRegNoEffect(MISCREG_STICK));
109    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
110            src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
111
112    // Priv Registers
113    dest->setMiscRegNoEffect(MISCREG_TICK,
114            src->readMiscRegNoEffect(MISCREG_TICK));
115    dest->setMiscRegNoEffect(MISCREG_TBA,
116            src->readMiscRegNoEffect(MISCREG_TBA));
117    dest->setMiscRegNoEffect(MISCREG_PSTATE,
118            src->readMiscRegNoEffect(MISCREG_PSTATE));
119    dest->setMiscRegNoEffect(MISCREG_PIL,
120            src->readMiscRegNoEffect(MISCREG_PIL));
121    dest->setMiscReg(MISCREG_CWP,
122            src->readMiscRegNoEffect(MISCREG_CWP));
123//    dest->setMiscRegNoEffect(MISCREG_CANSAVE,
124//            src->readMiscRegNoEffect(MISCREG_CANSAVE));
125//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
126//            src->readMiscRegNoEffect(MISCREG_CANRESTORE));
127//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
128//            src->readMiscRegNoEffect(MISCREG_OTHERWIN));
129//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
130//            src->readMiscRegNoEffect(MISCREG_CLEANWIN));
131//    dest->setMiscRegNoEffect(MISCREG_WSTATE,
132//            src->readMiscRegNoEffect(MISCREG_WSTATE));
133    dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
134
135    // Hyperprivilged registers
136    dest->setMiscRegNoEffect(MISCREG_HPSTATE,
137            src->readMiscRegNoEffect(MISCREG_HPSTATE));
138    dest->setMiscRegNoEffect(MISCREG_HINTP,
139            src->readMiscRegNoEffect(MISCREG_HINTP));
140    dest->setMiscRegNoEffect(MISCREG_HTBA,
141            src->readMiscRegNoEffect(MISCREG_HTBA));
142    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
143            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
144    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
145            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
146
147    // FSR
148    dest->setMiscRegNoEffect(MISCREG_FSR,
149            src->readMiscRegNoEffect(MISCREG_FSR));
150
151    // Strand Status Register
152    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
153            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
154
155    // MMU Registers
156    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
157            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
158    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
159            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
160    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
161            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
162    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
163            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
164
165    // Scratchpad Registers
166    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
167            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
168    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
169            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
170    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
171            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
172    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
173            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
174    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
175            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
176    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
177            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
178    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
179            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
180    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
181            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
182
183    // Queue Registers
184    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
185            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
186    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
187            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
188    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
189            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
190    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
191            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
192    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
193            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
194    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
195            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
196    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
197            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
198    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
199            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
200}
201
202void
203copyRegs(ThreadContext *src, ThreadContext *dest)
204{
205    // First loop through the integer registers.
206    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
207    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
208    // Globals
209    for (int x = 0; x < MaxGL; ++x) {
210        src->setMiscReg(MISCREG_GL, x);
211        dest->setMiscReg(MISCREG_GL, x);
212        // Skip %g0 which is always zero.
213        for (int y = 1; y < 8; y++)
214            dest->setIntReg(y, src->readIntReg(y));
215    }
216    // Locals and ins. Outs are all also ins.
217    for (int x = 0; x < NWindows; ++x) {
218         src->setMiscReg(MISCREG_CWP, x);
219         dest->setMiscReg(MISCREG_CWP, x);
220         for (int y = 16; y < 32; y++)
221             dest->setIntReg(y, src->readIntReg(y));
222    }
223    // Microcode reg and pseudo int regs (misc regs in the integer regfile).
224    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
225        dest->setIntReg(y, src->readIntReg(y));
226
227    // Restore src's GL, CWP
228    src->setMiscReg(MISCREG_GL, old_gl);
229    src->setMiscReg(MISCREG_CWP, old_cwp);
230
231
232    // Then loop through the floating point registers.
233    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
234        dest->setFloatRegBits(i, src->readFloatRegBits(i));
235    }
236
237    // Would need to add condition-code regs if implemented
238    assert(NumCCRegs == 0);
239
240    // Copy misc. registers
241    copyMiscRegs(src, dest);
242
243    // Lastly copy PC/NPC
244    dest->pcState(src->pcState());
245}
246
247void
248skipFunction(ThreadContext *tc)
249{
250    TheISA::PCState newPC = tc->pcState();
251    newPC.set(tc->readIntReg(ReturnAddressReg));
252    tc->pcState(newPC);
253}
254
255
256void
257initCPU(ThreadContext *tc, int cpuId)
258{
259    static Fault por = std::make_shared<PowerOnReset>();
260    if (cpuId == 0)
261        por->invoke(tc);
262}
263
264} // namespace SPARC_ISA
265