ua2005.cc revision 8778:fbaf6af0be93 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/isa.hh"
30#include "arch/sparc/kernel_stats.hh"
31#include "arch/sparc/registers.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "debug/Quiesce.hh"
37#include "debug/Timer.hh"
38#include "sim/system.hh"
39#include "sim/full_system.hh"
40
41using namespace SparcISA;
42using namespace std;
43
44
45void
46ISA::checkSoftInt(ThreadContext *tc)
47{
48    BaseCPU *cpu = tc->getCpuPtr();
49
50    // If PIL < 14, copy over the tm and sm bits
51    if (pil < 14 && softint & 0x10000)
52        cpu->postInterrupt(IT_SOFT_INT, 16);
53    else
54        cpu->clearInterrupt(IT_SOFT_INT, 16);
55    if (pil < 14 && softint & 0x1)
56        cpu->postInterrupt(IT_SOFT_INT, 0);
57    else
58        cpu->clearInterrupt(IT_SOFT_INT, 0);
59
60    // Copy over any of the other bits that are set
61    for (int bit = 15; bit > 0; --bit) {
62        if (1 << bit & softint && bit > pil)
63            cpu->postInterrupt(IT_SOFT_INT, bit);
64        else
65            cpu->clearInterrupt(IT_SOFT_INT, bit);
66    }
67}
68
69// These functions map register indices to names
70static inline string
71getMiscRegName(RegIndex index)
72{
73    static string miscRegName[NumMiscRegs] =
74        {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
75         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
76         "stick", "stick_cmpr",
77         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
78         "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
79         "wstate",*/ "gl",
80         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
81         "hstick_cmpr",
82         "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
83         "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
84         "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
85         "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
86         "nresErrorHead", "nresErrorTail", "TlbData" };
87    return miscRegName[index];
88}
89
90void
91ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
92{
93    BaseCPU *cpu = tc->getCpuPtr();
94
95    int64_t time;
96    switch (miscReg) {
97        /* Full system only ASRs */
98      case MISCREG_SOFTINT:
99        setMiscRegNoEffect(miscReg, val);;
100        checkSoftInt(tc);
101        break;
102      case MISCREG_SOFTINT_CLR:
103        return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
104      case MISCREG_SOFTINT_SET:
105        return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
106
107      case MISCREG_TICK_CMPR:
108        if (tickCompare == NULL)
109            tickCompare = new TickCompareEvent(this, tc);
110        setMiscRegNoEffect(miscReg, val);
111        if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
112            cpu->deschedule(tickCompare);
113        time = (tick_cmpr & mask(63)) - (tick & mask(63));
114        if (!(tick_cmpr & ~mask(63)) && time > 0) {
115            if (tickCompare->scheduled())
116                cpu->deschedule(tickCompare);
117            cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
118        }
119        panic("writing to TICK compare register %#X\n", val);
120        break;
121
122      case MISCREG_STICK_CMPR:
123        if (sTickCompare == NULL)
124            sTickCompare = new STickCompareEvent(this, tc);
125        setMiscRegNoEffect(miscReg, val);
126        if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
127            cpu->deschedule(sTickCompare);
128        time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
129            cpu->instCount();
130        if (!(stick_cmpr & ~mask(63)) && time > 0) {
131            if (sTickCompare->scheduled())
132                cpu->deschedule(sTickCompare);
133            cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
134        }
135        DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
136        break;
137
138      case MISCREG_PSTATE:
139        setMiscRegNoEffect(miscReg, val);
140
141      case MISCREG_PIL:
142        setMiscRegNoEffect(miscReg, val);
143        checkSoftInt(tc);
144        break;
145
146      case MISCREG_HVER:
147        panic("Shouldn't be writing HVER\n");
148
149      case MISCREG_HINTP:
150        setMiscRegNoEffect(miscReg, val);
151        if (hintp)
152            cpu->postInterrupt(IT_HINTP, 0);
153        else
154            cpu->clearInterrupt(IT_HINTP, 0);
155        break;
156
157      case MISCREG_HTBA:
158        // clear lower 7 bits on writes.
159        setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
160        break;
161
162      case MISCREG_QUEUE_CPU_MONDO_HEAD:
163      case MISCREG_QUEUE_CPU_MONDO_TAIL:
164        setMiscRegNoEffect(miscReg, val);
165        if (cpu_mondo_head != cpu_mondo_tail)
166            cpu->postInterrupt(IT_CPU_MONDO, 0);
167        else
168            cpu->clearInterrupt(IT_CPU_MONDO, 0);
169        break;
170      case MISCREG_QUEUE_DEV_MONDO_HEAD:
171      case MISCREG_QUEUE_DEV_MONDO_TAIL:
172        setMiscRegNoEffect(miscReg, val);
173        if (dev_mondo_head != dev_mondo_tail)
174            cpu->postInterrupt(IT_DEV_MONDO, 0);
175        else
176            cpu->clearInterrupt(IT_DEV_MONDO, 0);
177        break;
178      case MISCREG_QUEUE_RES_ERROR_HEAD:
179      case MISCREG_QUEUE_RES_ERROR_TAIL:
180        setMiscRegNoEffect(miscReg, val);
181        if (res_error_head != res_error_tail)
182            cpu->postInterrupt(IT_RES_ERROR, 0);
183        else
184            cpu->clearInterrupt(IT_RES_ERROR, 0);
185        break;
186      case MISCREG_QUEUE_NRES_ERROR_HEAD:
187      case MISCREG_QUEUE_NRES_ERROR_TAIL:
188        setMiscRegNoEffect(miscReg, val);
189        // This one doesn't have an interrupt to report to the guest OS
190        break;
191
192      case MISCREG_HSTICK_CMPR:
193        if (hSTickCompare == NULL)
194            hSTickCompare = new HSTickCompareEvent(this, tc);
195        setMiscRegNoEffect(miscReg, val);
196        if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
197            cpu->deschedule(hSTickCompare);
198        time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
199            cpu->instCount();
200        if (!(hstick_cmpr & ~mask(63)) && time > 0) {
201            if (hSTickCompare->scheduled())
202                cpu->deschedule(hSTickCompare);
203            cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
204        }
205        DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
206        break;
207
208      case MISCREG_HPSTATE:
209        // T1000 spec says impl. dependent val must always be 1
210        setMiscRegNoEffect(miscReg, val | HPSTATE::id);
211        if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
212            cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
213        else
214            cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
215        break;
216      case MISCREG_HTSTATE:
217        setMiscRegNoEffect(miscReg, val);
218        break;
219
220      case MISCREG_STRAND_STS_REG:
221        if (bits(val,2,2))
222            panic("No support for setting spec_en bit\n");
223        setMiscRegNoEffect(miscReg, bits(val,0,0));
224        if (!bits(val,0,0)) {
225            DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
226            // Time to go to sleep
227            tc->suspend();
228            if (FullSystem && tc->getKernelStats())
229                tc->getKernelStats()->quiesce();
230        }
231        break;
232
233      default:
234        panic("Invalid write to FS misc register %s\n",
235              getMiscRegName(miscReg));
236    }
237}
238
239MiscReg
240ISA::readFSReg(int miscReg, ThreadContext * tc)
241{
242    uint64_t temp;
243
244    switch (miscReg) {
245        /* Privileged registers. */
246      case MISCREG_QUEUE_CPU_MONDO_HEAD:
247      case MISCREG_QUEUE_CPU_MONDO_TAIL:
248      case MISCREG_QUEUE_DEV_MONDO_HEAD:
249      case MISCREG_QUEUE_DEV_MONDO_TAIL:
250      case MISCREG_QUEUE_RES_ERROR_HEAD:
251      case MISCREG_QUEUE_RES_ERROR_TAIL:
252      case MISCREG_QUEUE_NRES_ERROR_HEAD:
253      case MISCREG_QUEUE_NRES_ERROR_TAIL:
254      case MISCREG_SOFTINT:
255      case MISCREG_TICK_CMPR:
256      case MISCREG_STICK_CMPR:
257      case MISCREG_PIL:
258      case MISCREG_HPSTATE:
259      case MISCREG_HINTP:
260      case MISCREG_HTSTATE:
261      case MISCREG_HSTICK_CMPR:
262        return readMiscRegNoEffect(miscReg) ;
263
264      case MISCREG_HTBA:
265        return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
266      case MISCREG_HVER:
267        // XXX set to match Legion
268        return ULL(0x3e) << 48 |
269               ULL(0x23) << 32 |
270               ULL(0x20) << 24 |
271                   // MaxGL << 16 | XXX For some reason legion doesn't set GL
272                   MaxTL << 8  |
273           (NWindows -1) << 0;
274
275      case MISCREG_STRAND_STS_REG:
276        System *sys;
277        int x;
278        sys = tc->getSystemPtr();
279
280        temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative);
281        // Check that the CPU array is fully populated
282        // (by calling getNumCPus())
283        assert(sys->numContexts() > tc->contextId());
284
285        temp |= tc->contextId()  << STS::shft_id;
286
287        for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
288            switch (sys->threadContexts[x]->status()) {
289              case ThreadContext::Active:
290                temp |= STS::st_run << (STS::shft_fsm0 -
291                        ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
292                break;
293              case ThreadContext::Suspended:
294                // should this be idle?
295                temp |= STS::st_idle << (STS::shft_fsm0 -
296                        ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
297                break;
298              case ThreadContext::Halted:
299                temp |= STS::st_halt << (STS::shft_fsm0 -
300                        ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
301                break;
302              default:
303                panic("What state are we in?!\n");
304            } // switch
305        } // for
306
307        return temp;
308      default:
309        panic("Invalid read to FS misc register\n");
310    }
311}
312
313void
314ISA::processTickCompare(ThreadContext *tc)
315{
316    panic("tick compare not implemented\n");
317}
318
319void
320ISA::processSTickCompare(ThreadContext *tc)
321{
322    BaseCPU *cpu = tc->getCpuPtr();
323
324    // since our microcode instructions take two cycles we need to check if
325    // we're actually at the correct cycle or we need to wait a little while
326    // more
327    int ticks;
328    ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
329        cpu->instCount();
330    assert(ticks >= 0 && "stick compare missed interrupt cycle");
331
332    if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
333        DPRINTF(Timer, "STick compare cycle reached at %#x\n",
334                (stick_cmpr & mask(63)));
335        if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
336            setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
337        }
338    } else {
339        cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
340    }
341}
342
343void
344ISA::processHSTickCompare(ThreadContext *tc)
345{
346    BaseCPU *cpu = tc->getCpuPtr();
347
348    // since our microcode instructions take two cycles we need to check if
349    // we're actually at the correct cycle or we need to wait a little while
350    // more
351    int ticks;
352    if ( tc->status() == ThreadContext::Halted)
353       return;
354
355    ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
356        cpu->instCount();
357    assert(ticks >= 0 && "hstick compare missed interrupt cycle");
358
359    if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
360        DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
361                (stick_cmpr & mask(63)));
362        if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
363            setMiscReg(MISCREG_HINTP, 1, tc);
364        }
365        // Need to do something to cause interrupt to happen here !!! @todo
366    } else {
367        cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
368    }
369}
370
371