ua2005.cc revision 6029:007c36616f47
14483Sgblack@eecs.umich.edu/* 24483Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34483Sgblack@eecs.umich.edu * All rights reserved. 44483Sgblack@eecs.umich.edu * 54483Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64483Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74483Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84483Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94483Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104483Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114483Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124483Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134483Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144483Sgblack@eecs.umich.edu * this software without specific prior written permission. 154483Sgblack@eecs.umich.edu * 164483Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174483Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184483Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194483Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204483Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214483Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224483Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234483Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244483Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254483Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264483Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274483Sgblack@eecs.umich.edu */ 284483Sgblack@eecs.umich.edu 294483Sgblack@eecs.umich.edu#include "arch/sparc/kernel_stats.hh" 304483Sgblack@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 314483Sgblack@eecs.umich.edu#include "base/bitfield.hh" 324483Sgblack@eecs.umich.edu#include "base/trace.hh" 334483Sgblack@eecs.umich.edu#include "cpu/base.hh" 344483Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 354483Sgblack@eecs.umich.edu#include "sim/system.hh" 364483Sgblack@eecs.umich.edu 374483Sgblack@eecs.umich.eduusing namespace SparcISA; 384483Sgblack@eecs.umich.eduusing namespace std; 394483Sgblack@eecs.umich.edu 404483Sgblack@eecs.umich.edu 414483Sgblack@eecs.umich.eduvoid 424483Sgblack@eecs.umich.eduMiscRegFile::checkSoftInt(ThreadContext *tc) 434483Sgblack@eecs.umich.edu{ 444483Sgblack@eecs.umich.edu BaseCPU *cpu = tc->getCpuPtr(); 454483Sgblack@eecs.umich.edu 464483Sgblack@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 474483Sgblack@eecs.umich.edu if (pil < 14 && softint & 0x10000) 484483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_SOFT_INT, 16); 494483Sgblack@eecs.umich.edu else 504483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_SOFT_INT, 16); 514483Sgblack@eecs.umich.edu if (pil < 14 && softint & 0x1) 524483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_SOFT_INT, 0); 534483Sgblack@eecs.umich.edu else 544483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_SOFT_INT, 0); 554483Sgblack@eecs.umich.edu 564483Sgblack@eecs.umich.edu // Copy over any of the other bits that are set 574483Sgblack@eecs.umich.edu for (int bit = 15; bit > 0; --bit) { 584483Sgblack@eecs.umich.edu if (1 << bit & softint && bit > pil) 594483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_SOFT_INT, bit); 604483Sgblack@eecs.umich.edu else 614483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_SOFT_INT, bit); 624483Sgblack@eecs.umich.edu } 634483Sgblack@eecs.umich.edu} 644483Sgblack@eecs.umich.edu 654483Sgblack@eecs.umich.edu//These functions map register indices to names 664483Sgblack@eecs.umich.edustatic inline string 674507Sgblack@eecs.umich.edugetMiscRegName(RegIndex index) 684483Sgblack@eecs.umich.edu{ 694483Sgblack@eecs.umich.edu static string miscRegName[NumMiscRegs] = 704507Sgblack@eecs.umich.edu {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 714507Sgblack@eecs.umich.edu "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 724507Sgblack@eecs.umich.edu "stick", "stick_cmpr", 734507Sgblack@eecs.umich.edu "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 744507Sgblack@eecs.umich.edu "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 754508Sgblack@eecs.umich.edu "wstate",*/ "gl", 764508Sgblack@eecs.umich.edu "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 774508Sgblack@eecs.umich.edu "hstick_cmpr", 784483Sgblack@eecs.umich.edu "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 794483Sgblack@eecs.umich.edu "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 804483Sgblack@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 814483Sgblack@eecs.umich.edu "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 824483Sgblack@eecs.umich.edu "nresErrorHead", "nresErrorTail", "TlbData" }; 834483Sgblack@eecs.umich.edu return miscRegName[index]; 844483Sgblack@eecs.umich.edu} 854483Sgblack@eecs.umich.edu 864483Sgblack@eecs.umich.eduvoid 874483Sgblack@eecs.umich.eduMiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 884483Sgblack@eecs.umich.edu{ 894483Sgblack@eecs.umich.edu BaseCPU *cpu = tc->getCpuPtr(); 904483Sgblack@eecs.umich.edu 914483Sgblack@eecs.umich.edu int64_t time; 924483Sgblack@eecs.umich.edu switch (miscReg) { 934483Sgblack@eecs.umich.edu /* Full system only ASRs */ 944483Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 954483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val);; 964483Sgblack@eecs.umich.edu checkSoftInt(tc); 974483Sgblack@eecs.umich.edu break; 984483Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 994483Sgblack@eecs.umich.edu return setReg(MISCREG_SOFTINT, ~val & softint, tc); 1004483Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 1014483Sgblack@eecs.umich.edu return setReg(MISCREG_SOFTINT, val | softint, tc); 1024503Sgblack@eecs.umich.edu 1034483Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 1044483Sgblack@eecs.umich.edu if (tickCompare == NULL) 1054483Sgblack@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 1064483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1074483Sgblack@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1084483Sgblack@eecs.umich.edu cpu->deschedule(tickCompare); 1094483Sgblack@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1104483Sgblack@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 1114483Sgblack@eecs.umich.edu if (tickCompare->scheduled()) 1124483Sgblack@eecs.umich.edu cpu->deschedule(tickCompare); 1134483Sgblack@eecs.umich.edu cpu->schedule(tickCompare, curTick + time * cpu->ticks(1)); 1144483Sgblack@eecs.umich.edu } 1154483Sgblack@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 1164483Sgblack@eecs.umich.edu break; 1174483Sgblack@eecs.umich.edu 1184483Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 1194483Sgblack@eecs.umich.edu if (sTickCompare == NULL) 1204483Sgblack@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 1214483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1224483Sgblack@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1234483Sgblack@eecs.umich.edu cpu->deschedule(sTickCompare); 1244483Sgblack@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1254483Sgblack@eecs.umich.edu cpu->instCount(); 1264483Sgblack@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) { 1274483Sgblack@eecs.umich.edu if (sTickCompare->scheduled()) 1284483Sgblack@eecs.umich.edu cpu->deschedule(sTickCompare); 1294483Sgblack@eecs.umich.edu cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1)); 1304483Sgblack@eecs.umich.edu } 1314483Sgblack@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1324483Sgblack@eecs.umich.edu break; 1334483Sgblack@eecs.umich.edu 1344483Sgblack@eecs.umich.edu case MISCREG_PSTATE: 1354483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1364483Sgblack@eecs.umich.edu 1374483Sgblack@eecs.umich.edu case MISCREG_PIL: 1384483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1394483Sgblack@eecs.umich.edu checkSoftInt(tc); 1404483Sgblack@eecs.umich.edu break; 1414483Sgblack@eecs.umich.edu 1424483Sgblack@eecs.umich.edu case MISCREG_HVER: 1434483Sgblack@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 1444483Sgblack@eecs.umich.edu 1454483Sgblack@eecs.umich.edu case MISCREG_HINTP: 1464483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1474503Sgblack@eecs.umich.edu if (hintp) 1484483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_HINTP, 0); 1494483Sgblack@eecs.umich.edu else 1504483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_HINTP, 0); 1514483Sgblack@eecs.umich.edu break; 1524483Sgblack@eecs.umich.edu 1534483Sgblack@eecs.umich.edu case MISCREG_HTBA: 1544483Sgblack@eecs.umich.edu // clear lower 7 bits on writes. 1554483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1564483Sgblack@eecs.umich.edu break; 1574483Sgblack@eecs.umich.edu 1584483Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1594483Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1604483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1614483Sgblack@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 1624483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_CPU_MONDO, 0); 1634483Sgblack@eecs.umich.edu else 1644483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_CPU_MONDO, 0); 1654483Sgblack@eecs.umich.edu break; 1664483Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1674483Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1684483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1694483Sgblack@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 1704483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_DEV_MONDO, 0); 1714483Sgblack@eecs.umich.edu else 1724483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_DEV_MONDO, 0); 1734483Sgblack@eecs.umich.edu break; 1744483Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1754483Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1764483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1774483Sgblack@eecs.umich.edu if (res_error_head != res_error_tail) 1784483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_RES_ERROR, 0); 1794483Sgblack@eecs.umich.edu else 1804483Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_RES_ERROR, 0); 1814483Sgblack@eecs.umich.edu break; 1824483Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1834483Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1844483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1854483Sgblack@eecs.umich.edu // This one doesn't have an interrupt to report to the guest OS 1864483Sgblack@eecs.umich.edu break; 1874483Sgblack@eecs.umich.edu 1884483Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1894483Sgblack@eecs.umich.edu if (hSTickCompare == NULL) 1904483Sgblack@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1914483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 1924483Sgblack@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1934483Sgblack@eecs.umich.edu cpu->deschedule(hSTickCompare); 1944483Sgblack@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1954483Sgblack@eecs.umich.edu cpu->instCount(); 1964483Sgblack@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) { 1974483Sgblack@eecs.umich.edu if (hSTickCompare->scheduled()) 1984483Sgblack@eecs.umich.edu cpu->deschedule(hSTickCompare); 1994483Sgblack@eecs.umich.edu cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1)); 2004502Sgblack@eecs.umich.edu } 2014502Sgblack@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2024502Sgblack@eecs.umich.edu break; 2034502Sgblack@eecs.umich.edu 2044502Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 2054502Sgblack@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 2064502Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val | HPSTATE::id); 2074502Sgblack@eecs.umich.edu#if FULL_SYSTEM 2084483Sgblack@eecs.umich.edu if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 2094483Sgblack@eecs.umich.edu cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2104483Sgblack@eecs.umich.edu else 2114502Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2124483Sgblack@eecs.umich.edu#endif 2134483Sgblack@eecs.umich.edu break; 2144483Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 2154483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, val); 2164483Sgblack@eecs.umich.edu break; 2174483Sgblack@eecs.umich.edu 2184502Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2194483Sgblack@eecs.umich.edu if (bits(val,2,2)) 2204483Sgblack@eecs.umich.edu panic("No support for setting spec_en bit\n"); 2214483Sgblack@eecs.umich.edu setRegNoEffect(miscReg, bits(val,0,0)); 2224483Sgblack@eecs.umich.edu if (!bits(val,0,0)) { 2234483Sgblack@eecs.umich.edu DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2244502Sgblack@eecs.umich.edu // Time to go to sleep 2254483Sgblack@eecs.umich.edu tc->suspend(); 2264483Sgblack@eecs.umich.edu if (tc->getKernelStats()) 2274483Sgblack@eecs.umich.edu tc->getKernelStats()->quiesce(); 2284483Sgblack@eecs.umich.edu } 2294483Sgblack@eecs.umich.edu break; 2304483Sgblack@eecs.umich.edu 2314502Sgblack@eecs.umich.edu default: 2324483Sgblack@eecs.umich.edu panic("Invalid write to FS misc register %s\n", 2334483Sgblack@eecs.umich.edu getMiscRegName(miscReg)); 2344483Sgblack@eecs.umich.edu } 2354483Sgblack@eecs.umich.edu} 2364483Sgblack@eecs.umich.edu 2374502Sgblack@eecs.umich.eduMiscReg 2384483Sgblack@eecs.umich.eduMiscRegFile::readFSReg(int miscReg, ThreadContext * tc) 2394483Sgblack@eecs.umich.edu{ 2404483Sgblack@eecs.umich.edu uint64_t temp; 2414483Sgblack@eecs.umich.edu 2424483Sgblack@eecs.umich.edu switch (miscReg) { 2434502Sgblack@eecs.umich.edu /* Privileged registers. */ 2444483Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2454483Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2464483Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2474483Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2484483Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2494502Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2504483Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2514483Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2524483Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 2534483Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 2544502Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 2554483Sgblack@eecs.umich.edu case MISCREG_PIL: 2564483Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 2574483Sgblack@eecs.umich.edu case MISCREG_HINTP: 2584483Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 2594483Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2604483Sgblack@eecs.umich.edu return readRegNoEffect(miscReg) ; 2614502Sgblack@eecs.umich.edu 2624483Sgblack@eecs.umich.edu case MISCREG_HTBA: 2634483Sgblack@eecs.umich.edu return readRegNoEffect(miscReg) & ULL(~0x7FFF); 2644483Sgblack@eecs.umich.edu case MISCREG_HVER: 2654483Sgblack@eecs.umich.edu // XXX set to match Legion 2664483Sgblack@eecs.umich.edu return ULL(0x3e) << 48 | 2674502Sgblack@eecs.umich.edu ULL(0x23) << 32 | 2684483Sgblack@eecs.umich.edu ULL(0x20) << 24 | 2694483Sgblack@eecs.umich.edu //MaxGL << 16 | XXX For some reason legion doesn't set GL 2704483Sgblack@eecs.umich.edu MaxTL << 8 | 2714483Sgblack@eecs.umich.edu (NWindows -1) << 0; 2724483Sgblack@eecs.umich.edu 2734483Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2744483Sgblack@eecs.umich.edu System *sys; 2754483Sgblack@eecs.umich.edu int x; 2764483Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 2774483Sgblack@eecs.umich.edu 2784483Sgblack@eecs.umich.edu temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); 2794483Sgblack@eecs.umich.edu // Check that the CPU array is fully populated 2804483Sgblack@eecs.umich.edu // (by calling getNumCPus()) 2814483Sgblack@eecs.umich.edu assert(sys->numContexts() > tc->contextId()); 2824483Sgblack@eecs.umich.edu 2834483Sgblack@eecs.umich.edu temp |= tc->contextId() << STS::shft_id; 2844483Sgblack@eecs.umich.edu 2854483Sgblack@eecs.umich.edu for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 2864483Sgblack@eecs.umich.edu switch (sys->threadContexts[x]->status()) { 2874483Sgblack@eecs.umich.edu case ThreadContext::Active: 2884483Sgblack@eecs.umich.edu temp |= STS::st_run << (STS::shft_fsm0 - 2894483Sgblack@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2904483Sgblack@eecs.umich.edu break; 2914483Sgblack@eecs.umich.edu case ThreadContext::Suspended: 2924483Sgblack@eecs.umich.edu // should this be idle? 2934483Sgblack@eecs.umich.edu temp |= STS::st_idle << (STS::shft_fsm0 - 2944483Sgblack@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2954483Sgblack@eecs.umich.edu break; 2964483Sgblack@eecs.umich.edu case ThreadContext::Halted: 2974483Sgblack@eecs.umich.edu temp |= STS::st_halt << (STS::shft_fsm0 - 2984483Sgblack@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2994483Sgblack@eecs.umich.edu break; 3004483Sgblack@eecs.umich.edu default: 3014483Sgblack@eecs.umich.edu panic("What state are we in?!\n"); 3024483Sgblack@eecs.umich.edu } // switch 3034483Sgblack@eecs.umich.edu } // for 3044483Sgblack@eecs.umich.edu 3054483Sgblack@eecs.umich.edu return temp; 3064483Sgblack@eecs.umich.edu default: 3074483Sgblack@eecs.umich.edu panic("Invalid read to FS misc register\n"); 3084483Sgblack@eecs.umich.edu } 3094483Sgblack@eecs.umich.edu} 3104483Sgblack@eecs.umich.edu 3114483Sgblack@eecs.umich.eduvoid 3124483Sgblack@eecs.umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 3134483Sgblack@eecs.umich.edu{ 3144483Sgblack@eecs.umich.edu panic("tick compare not implemented\n"); 3154483Sgblack@eecs.umich.edu} 3164483Sgblack@eecs.umich.edu 3174483Sgblack@eecs.umich.eduvoid 3184483Sgblack@eecs.umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 3194483Sgblack@eecs.umich.edu{ 3204483Sgblack@eecs.umich.edu BaseCPU *cpu = tc->getCpuPtr(); 3214507Sgblack@eecs.umich.edu 3224507Sgblack@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3234507Sgblack@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3244483Sgblack@eecs.umich.edu // more 3254483Sgblack@eecs.umich.edu int ticks; 3264483Sgblack@eecs.umich.edu ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 3274483Sgblack@eecs.umich.edu cpu->instCount(); 3284483Sgblack@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 3294483Sgblack@eecs.umich.edu 3304502Sgblack@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3314507Sgblack@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 3324507Sgblack@eecs.umich.edu (stick_cmpr & mask(63))); 3334507Sgblack@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 3344507Sgblack@eecs.umich.edu setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 3354508Sgblack@eecs.umich.edu } 3364507Sgblack@eecs.umich.edu } else 3374483Sgblack@eecs.umich.edu cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); 3384483Sgblack@eecs.umich.edu} 3394483Sgblack@eecs.umich.edu 3404483Sgblack@eecs.umich.eduvoid 3414483Sgblack@eecs.umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 3424483Sgblack@eecs.umich.edu{ 3434483Sgblack@eecs.umich.edu BaseCPU *cpu = tc->getCpuPtr(); 3444483Sgblack@eecs.umich.edu 3454483Sgblack@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3464483Sgblack@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3474483Sgblack@eecs.umich.edu // more 3484502Sgblack@eecs.umich.edu int ticks; 3494483Sgblack@eecs.umich.edu if ( tc->status() == ThreadContext::Halted) 3504483Sgblack@eecs.umich.edu return; 3514483Sgblack@eecs.umich.edu 3524483Sgblack@eecs.umich.edu ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 3534483Sgblack@eecs.umich.edu cpu->instCount(); 3544483Sgblack@eecs.umich.edu assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 3554483Sgblack@eecs.umich.edu 3564483Sgblack@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3574483Sgblack@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 3584483Sgblack@eecs.umich.edu (stick_cmpr & mask(63))); 3594483Sgblack@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 3604483Sgblack@eecs.umich.edu setReg(MISCREG_HINTP, 1, tc); 3614483Sgblack@eecs.umich.edu } 3624483Sgblack@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 3634483Sgblack@eecs.umich.edu } else 3644483Sgblack@eecs.umich.edu cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1)); 3654483Sgblack@eecs.umich.edu} 3664483Sgblack@eecs.umich.edu 3674483Sgblack@eecs.umich.edu