ua2005.cc revision 3827 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/miscregfile.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36
37using namespace SparcISA;
38
39void
40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
41        ThreadContext *tc)
42{
43    int64_t time;
44    switch (miscReg) {
45        /* Full system only ASRs */
46        case MISCREG_SOFTINT:
47          // Check if we are going to interrupt because of something
48          setReg(miscReg, val);
49          tc->getCpuPtr()->checkInterrupts = true;
50          break;
51
52        case MISCREG_SOFTINT_CLR:
53          return setRegWithEffect(miscReg, ~val & softint, tc);
54        case MISCREG_SOFTINT_SET:
55          return setRegWithEffect(miscReg, val | softint, tc);
56
57        case MISCREG_TICK_CMPR:
58          if (tickCompare == NULL)
59              tickCompare = new TickCompareEvent(this, tc);
60          setReg(miscReg, val);
61          if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
62                  tickCompare->deschedule();
63          time = (tick_cmpr & mask(63)) - (tick & mask(63));
64          if (!(tick_cmpr & ~mask(63)) && time > 0)
65              tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
66          break;
67
68        case MISCREG_STICK_CMPR:
69          if (sTickCompare == NULL)
70              sTickCompare = new STickCompareEvent(this, tc);
71          setReg(miscReg, val);
72          if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
73                  sTickCompare->deschedule();
74          time = (stick_cmpr & mask(63)) - (stick & mask(63));
75          if (!(stick_cmpr & ~mask(63)) && time > 0)
76              sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
77          break;
78
79        case MISCREG_PSTATE:
80          if (val & ie && !(pstate & ie)) {
81              tc->getCpuPtr()->checkInterrupts = true;
82          }
83          setReg(miscReg, val);
84
85        case MISCREG_PIL:
86          if (val < pil) {
87              tc->getCpuPtr()->checkInterrupts = true;
88          }
89          setReg(miscReg, val);
90          break;
91
92        case MISCREG_HVER:
93          panic("Shouldn't be writing HVER\n");
94
95        case MISCREG_HTBA:
96          // clear lower 7 bits on writes.
97          setReg(miscReg, val & ULL(~0x7FFF));
98          break;
99
100        case MISCREG_HSTICK_CMPR:
101          if (hSTickCompare == NULL)
102              hSTickCompare = new HSTickCompareEvent(this, tc);
103          setReg(miscReg, val);
104          if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
105                  hSTickCompare->deschedule();
106          time = (hstick_cmpr & mask(63)) - (stick & mask(63));
107          if (!(hstick_cmpr & ~mask(63)) && time > 0)
108              hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
109          break;
110
111        case MISCREG_HPSTATE:
112          // T1000 spec says impl. dependent val must always be 1
113          setReg(miscReg, val | id);
114
115        case MISCREG_HTSTATE:
116        case MISCREG_STRAND_STS_REG:
117          setReg(miscReg, val);
118          break;
119
120        default:
121          panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
122    }
123}
124
125MiscReg
126MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
127{
128    switch (miscReg) {
129
130        /* Privileged registers. */
131        case MISCREG_SOFTINT:
132        case MISCREG_TICK_CMPR:
133        case MISCREG_STICK_CMPR:
134        case MISCREG_PIL:
135        case MISCREG_HPSTATE:
136        case MISCREG_HINTP:
137        case MISCREG_HTSTATE:
138        case MISCREG_STRAND_STS_REG:
139        case MISCREG_HSTICK_CMPR:
140           return readReg(miscReg) ;
141
142        case MISCREG_HTBA:
143          return readReg(miscReg) & ULL(~0x7FFF);
144        case MISCREG_HVER:
145          return NWindows | MaxTL << 8 | MaxGL << 16;
146
147        default:
148          panic("Invalid read to FS misc register\n");
149    }
150}
151/*
152        In Niagra STICK==TICK so this isn't needed
153        case MISCREG_STICK:
154          SparcSystem *sys;
155          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
156          assert(sys != NULL);
157          return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
158*/
159
160
161
162void
163MiscRegFile::processTickCompare(ThreadContext *tc)
164{
165    panic("tick compare not implemented\n");
166}
167
168void
169MiscRegFile::processSTickCompare(ThreadContext *tc)
170{
171    panic("tick compare not implemented\n");
172}
173
174void
175MiscRegFile::processHSTickCompare(ThreadContext *tc)
176{
177    panic("tick compare not implemented\n");
178}
179
180