ua2005.cc revision 2665:a124942bacb8
112391Sjason@lowepower.com/* 214299Sbbruce@ucdavis.edu * Copyright (c) 2006 The Regents of The University of Michigan 312391Sjason@lowepower.com * All rights reserved. 412391Sjason@lowepower.com * 512391Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 612391Sjason@lowepower.com * modification, are permitted provided that the following conditions are 712391Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 812391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 912391Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 1012391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 1112391Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 1212391Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 1312391Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 1412391Sjason@lowepower.com * this software without specific prior written permission. 1512391Sjason@lowepower.com * 1612391Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1714299Sbbruce@ucdavis.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1814299Sbbruce@ucdavis.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1914299Sbbruce@ucdavis.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2014299Sbbruce@ucdavis.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2114299Sbbruce@ucdavis.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212391Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2314299Sbbruce@ucdavis.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2414299Sbbruce@ucdavis.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2514299Sbbruce@ucdavis.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2614299Sbbruce@ucdavis.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712391Sjason@lowepower.com * 2814299Sbbruce@ucdavis.edu * Authors: Ali Saidi 2914299Sbbruce@ucdavis.edu */ 3012391Sjason@lowepower.com 3114299Sbbruce@ucdavis.edu#include "arch/sparc/regfile.hh" 3214299Sbbruce@ucdavis.edu 3314299Sbbruce@ucdavis.eduFault 3414299Sbbruce@ucdavis.eduSparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 3514299Sbbruce@ucdavis.edu ExecContext *xc) 3614299Sbbruce@ucdavis.edu{ 3714299Sbbruce@ucdavis.edu int64_t time; 3814299Sbbruce@ucdavis.edu SparcSystem *sys; 3912391Sjason@lowepower.com switch (miscReg) { 4012391Sjason@lowepower.com /** Full system only ASRs */ 4112391Sjason@lowepower.com case MISCREG_SOFTINT: 4214299Sbbruce@ucdavis.edu if (isNonPriv()) 4314299Sbbruce@ucdavis.edu return new PrivilegedOpcode; 4414299Sbbruce@ucdavis.edu // Check if we are going to interrupt because of something 4514299Sbbruce@ucdavis.edu int oldLevel = InterruptLevel(softint); 4612391Sjason@lowepower.com int newLevel = InterruptLevel(val); 4712391Sjason@lowepower.com setReg(miscReg, val); 4814299Sbbruce@ucdavis.edu if (newLevel > oldLevel) 4914299Sbbruce@ucdavis.edu ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 5014299Sbbruce@ucdavis.edu //xc->getCpuPtr()->checkInterrupts = true; 5114299Sbbruce@ucdavis.edu return NoFault; 5214299Sbbruce@ucdavis.edu 5314299Sbbruce@ucdavis.edu case MISCREG_SOFTINT_CLR: 5414299Sbbruce@ucdavis.edu return setRegWithEffect(miscReg, ~val & softint, xc); 5514299Sbbruce@ucdavis.edu case MISCREG_SOFTINT_SET: 5614299Sbbruce@ucdavis.edu return setRegWithEffect(miscReg, val | softint, xc); 5712391Sjason@lowepower.com 5812391Sjason@lowepower.com case MISCREG_TICK_CMPR: 5914299Sbbruce@ucdavis.edu if (isNonPriv()) 6012391Sjason@lowepower.com return new PrivilegedOpcode; 6112391Sjason@lowepower.com if (tickCompare == NULL) 6212391Sjason@lowepower.com tickCompare = new TickCompareEvent(this, xc); 6314299Sbbruce@ucdavis.edu setReg(miscReg, val); 6414299Sbbruce@ucdavis.edu if (tick_cmprFields.int_dis && tickCompare.scheduled()) 6512391Sjason@lowepower.com tickCompare.deschedule(); 6612391Sjason@lowepower.com time = tick_cmprFields.tick_cmpr - tickFields.counter; 6714299Sbbruce@ucdavis.edu if (!tick_cmprFields.int_dis && time > 0) 6814299Sbbruce@ucdavis.edu tickCompare.schedule(time * xc->getCpuPtr()->cycles(1)); 6912391Sjason@lowepower.com return NoFault; 7012391Sjason@lowepower.com 7114299Sbbruce@ucdavis.edu case MISCREG_STICK: 7214299Sbbruce@ucdavis.edu if (isNonPriv()) 7314299Sbbruce@ucdavis.edu return new PrivilegedOpcode; 7414299Sbbruce@ucdavis.edu if (isPriv()) 7514299Sbbruce@ucdavis.edu return new PrivilegedAction; 7612391Sjason@lowepower.com sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 7712391Sjason@lowepower.com assert(sys != NULL); 7812391Sjason@lowepower.com sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; 7912391Sjason@lowepower.com stickFields.npt = val & Bit64 ? 1 : 0; 8012391Sjason@lowepower.com return NoFault; 8114299Sbbruce@ucdavis.edu 8214299Sbbruce@ucdavis.edu case MISCREG_STICK_CMPR: 8314299Sbbruce@ucdavis.edu if (isNonPriv()) 8414299Sbbruce@ucdavis.edu return new PrivilegedOpcode; 8514299Sbbruce@ucdavis.edu if (sTickCompare == NULL) 8614299Sbbruce@ucdavis.edu sTickCompare = new STickCompareEvent(this, xc); 8714299Sbbruce@ucdavis.edu sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 8814299Sbbruce@ucdavis.edu assert(sys != NULL); 8914299Sbbruce@ucdavis.edu setReg(miscReg, val); 9014299Sbbruce@ucdavis.edu if (stick_cmprFields.int_dis && sTickCompare.scheduled()) 9114299Sbbruce@ucdavis.edu sTickCompare.deschedule(); 9212391Sjason@lowepower.com time = stick_cmprFields.tick_cmpr - sys->sysTick; 9312391Sjason@lowepower.com if (!stick_cmprFields.int_dis && time > 0) 9414299Sbbruce@ucdavis.edu sTickCompare.schedule(time * Clock::Int::ns); 9514299Sbbruce@ucdavis.edu return NoFault; 9614299Sbbruce@ucdavis.edu 9712391Sjason@lowepower.com /** Fullsystem only Priv registers. */ 9812391Sjason@lowepower.com case MISCREG_PIL: 9912391Sjason@lowepower.com if (FULL_SYSTEM) { 10012391Sjason@lowepower.com setReg(miscReg, val); 101 //xc->getCpuPtr()->checkInterrupts; 102 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 103 return NoFault; 104 } else 105 panic("PIL not implemented for syscall emulation\n"); 106 107 /** Hyper privileged registers */ 108 case MISCREG_HPSTATE: 109 case MISCREG_HINTP: 110 setReg(miscReg, val); 111 return NoFault; 112 case MISCREG_HTSTATE: 113 if (tl == 0) 114 return new IllegalInstruction; 115 setReg(miscReg, val); 116 return NoFault; 117 118 case MISCREG_HTBA: 119 // clear lower 7 bits on writes. 120 setReg(miscReg, val & ULL(~0x7FFF)); 121 return NoFault; 122 123 case MISCREG_STRAND_STS_REG: 124 setReg(miscReg, strandStatusReg); 125 return NoFault; 126 case MISCREG_HSTICK_CMPR: 127 if (isNonPriv()) 128 return new PrivilegedOpcode; 129 if (hSTickCompare == NULL) 130 hSTickCompare = new HSTickCompareEvent(this, xc); 131 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 132 assert(sys != NULL); 133 setReg(miscReg, val); 134 if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) 135 hSTickCompare.deschedule(); 136 int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; 137 if (!hstick_cmprFields.int_dis && time > 0) 138 hSTickCompare.schedule(time * Clock::Int::ns); 139 return NoFault; 140 default: 141 return new IllegalInstruction; 142 } 143} 144 145MiscReg 146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) 147{ 148 switch (miscReg) { 149 150 /** Privileged registers. */ 151 case MISCREG_SOFTINT: 152 if (isNonPriv()) { 153 fault = new PrivilegedOpcode; 154 return 0; 155 } 156 return readReg(miscReg); 157 case MISCREG_TICK_CMPR: 158 if (isNonPriv()) { 159 fault = new PrivilegedOpcode; 160 return 0; 161 } 162 return readReg(miscReg); 163 case MISCREG_STICK: 164 SparcSystem *sys; 165 if (stickFields.npt && !isNonPriv()) { 166 fault = new PrivilegedAction; 167 return 0; 168 } 169 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 170 assert(sys != NULL); 171 return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; 172 case MISCREG_STICK_CMPR: 173 if (isNonPriv()) { 174 fault = new PrivilegedOpcode; 175 return 0; 176 } 177 return readReg(miscReg); 178 179 180 /** Hyper privileged registers */ 181 case MISCREG_HPSTATE: 182 case MISCREG_HINTP: 183 return readReg(miscReg); 184 case MISCREG_HTSTATE: 185 if (tl == 0) { 186 fault = new IllegalInstruction; 187 return 0; 188 } 189 return readReg(miscReg); 190 191 case MISCREG_HTBA: 192 return readReg(miscReg) & ULL(~0x7FFF); 193 case MISCREG_HVER: 194 return NWindows | MaxTL << 8 | MaxGL << 16; 195 case MISCREG_STRAND_STS_REG: 196 return strandStatusReg; 197 case MISCREG_HSTICK_CMPR: 198 return hstick_cmpr; 199 200 default: 201 fault = new IllegalInstruction; 202 return 0; 203 } 204} 205 206void 207MiscRegFile::processTickCompare(ExecContext *xc) 208{ 209 panic("tick compare not implemented\n"); 210} 211 212void 213MiscRegFile::processSTickCompare(ExecContext *xc) 214{ 215 panic("tick compare not implemented\n"); 216} 217 218void 219MiscRegFile::processHSTickCompare(ExecContext *xc) 220{ 221 panic("tick compare not implemented\n"); 222} 223 224}; // namespace SparcISA 225