ua2005.cc revision 2665:a124942bacb8 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/regfile.hh"
32
33Fault
34SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
35        ExecContext *xc)
36{
37    int64_t time;
38    SparcSystem *sys;
39    switch (miscReg) {
40        /** Full system only ASRs */
41        case MISCREG_SOFTINT:
42          if (isNonPriv())
43              return new PrivilegedOpcode;
44          // Check if we are going to interrupt because of something
45          int oldLevel = InterruptLevel(softint);
46          int newLevel = InterruptLevel(val);
47          setReg(miscReg, val);
48          if (newLevel > oldLevel)
49              ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
50              //xc->getCpuPtr()->checkInterrupts = true;
51          return NoFault;
52
53        case MISCREG_SOFTINT_CLR:
54          return setRegWithEffect(miscReg, ~val & softint, xc);
55        case MISCREG_SOFTINT_SET:
56          return setRegWithEffect(miscReg, val | softint, xc);
57
58        case MISCREG_TICK_CMPR:
59          if (isNonPriv())
60              return new PrivilegedOpcode;
61          if (tickCompare == NULL)
62              tickCompare = new TickCompareEvent(this, xc);
63          setReg(miscReg, val);
64          if (tick_cmprFields.int_dis && tickCompare.scheduled())
65                  tickCompare.deschedule();
66          time = tick_cmprFields.tick_cmpr - tickFields.counter;
67          if (!tick_cmprFields.int_dis && time > 0)
68              tickCompare.schedule(time * xc->getCpuPtr()->cycles(1));
69          return NoFault;
70
71        case MISCREG_STICK:
72          if (isNonPriv())
73              return new PrivilegedOpcode;
74          if (isPriv())
75              return new PrivilegedAction;
76          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
77          assert(sys != NULL);
78          sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
79          stickFields.npt = val & Bit64 ? 1 : 0;
80          return NoFault;
81
82        case MISCREG_STICK_CMPR:
83          if (isNonPriv())
84              return new PrivilegedOpcode;
85          if (sTickCompare == NULL)
86              sTickCompare = new STickCompareEvent(this, xc);
87          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
88          assert(sys != NULL);
89          setReg(miscReg, val);
90          if (stick_cmprFields.int_dis && sTickCompare.scheduled())
91                  sTickCompare.deschedule();
92          time = stick_cmprFields.tick_cmpr - sys->sysTick;
93          if (!stick_cmprFields.int_dis && time > 0)
94              sTickCompare.schedule(time * Clock::Int::ns);
95          return NoFault;
96
97        /** Fullsystem only Priv registers. */
98        case MISCREG_PIL:
99          if (FULL_SYSTEM) {
100              setReg(miscReg, val);
101              //xc->getCpuPtr()->checkInterrupts;
102               // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
103              return NoFault;
104          } else
105              panic("PIL not implemented for syscall emulation\n");
106
107        /** Hyper privileged registers */
108        case MISCREG_HPSTATE:
109        case MISCREG_HINTP:
110          setReg(miscReg, val);
111          return NoFault;
112        case MISCREG_HTSTATE:
113          if (tl == 0)
114              return new IllegalInstruction;
115          setReg(miscReg, val);
116          return NoFault;
117
118        case MISCREG_HTBA:
119          // clear lower 7 bits on writes.
120          setReg(miscReg, val & ULL(~0x7FFF));
121          return NoFault;
122
123        case MISCREG_STRAND_STS_REG:
124          setReg(miscReg, strandStatusReg);
125          return NoFault;
126        case MISCREG_HSTICK_CMPR:
127          if (isNonPriv())
128              return new PrivilegedOpcode;
129          if (hSTickCompare == NULL)
130              hSTickCompare = new HSTickCompareEvent(this, xc);
131          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
132          assert(sys != NULL);
133          setReg(miscReg, val);
134          if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
135                  hSTickCompare.deschedule();
136          int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
137          if (!hstick_cmprFields.int_dis && time > 0)
138              hSTickCompare.schedule(time * Clock::Int::ns);
139          return NoFault;
140        default:
141          return new IllegalInstruction;
142    }
143}
144
145MiscReg
146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
147{
148    switch (miscReg) {
149
150        /** Privileged registers. */
151        case MISCREG_SOFTINT:
152           if (isNonPriv()) {
153               fault = new PrivilegedOpcode;
154               return 0;
155           }
156           return readReg(miscReg);
157        case MISCREG_TICK_CMPR:
158           if (isNonPriv()) {
159               fault =  new PrivilegedOpcode;
160               return 0;
161           }
162           return readReg(miscReg);
163        case MISCREG_STICK:
164          SparcSystem *sys;
165          if (stickFields.npt && !isNonPriv()) {
166              fault = new PrivilegedAction;
167              return 0;
168          }
169          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
170          assert(sys != NULL);
171          return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
172        case MISCREG_STICK_CMPR:
173           if (isNonPriv()) {
174               fault =  new PrivilegedOpcode;
175               return 0;
176           }
177           return readReg(miscReg);
178
179
180        /** Hyper privileged registers */
181        case MISCREG_HPSTATE:
182        case MISCREG_HINTP:
183          return readReg(miscReg);
184        case MISCREG_HTSTATE:
185          if (tl == 0) {
186              fault = new IllegalInstruction;
187              return 0;
188          }
189          return readReg(miscReg);
190
191        case MISCREG_HTBA:
192          return readReg(miscReg) & ULL(~0x7FFF);
193        case MISCREG_HVER:
194          return NWindows | MaxTL << 8 | MaxGL << 16;
195        case MISCREG_STRAND_STS_REG:
196          return strandStatusReg;
197        case MISCREG_HSTICK_CMPR:
198          return hstick_cmpr;
199
200        default:
201          fault = new IllegalInstruction;
202          return 0;
203    }
204}
205
206void
207MiscRegFile::processTickCompare(ExecContext *xc)
208{
209    panic("tick compare not implemented\n");
210}
211
212void
213MiscRegFile::processSTickCompare(ExecContext *xc)
214{
215    panic("tick compare not implemented\n");
216}
217
218void
219MiscRegFile::processHSTickCompare(ExecContext *xc)
220{
221    panic("tick compare not implemented\n");
222}
223
224}; // namespace SparcISA
225