ua2005.cc revision 13583:f7482392b097
12SN/A/* 210349Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 310349Sandreas.hansson@arm.com * All rights reserved. 410349Sandreas.hansson@arm.com * 510349Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 610349Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 710349Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 810349Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 910349Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1010349Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1110349Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1210349Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 1310349Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#include "arch/sparc/isa.hh" 302SN/A#include "arch/sparc/kernel_stats.hh" 312SN/A#include "arch/sparc/registers.hh" 322SN/A#include "base/bitfield.hh" 332SN/A#include "base/trace.hh" 342SN/A#include "cpu/base.hh" 352SN/A#include "cpu/thread_context.hh" 362SN/A#include "debug/Quiesce.hh" 372SN/A#include "debug/Timer.hh" 382SN/A#include "sim/full_system.hh" 392665Ssaidi@eecs.umich.edu#include "sim/system.hh" 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.eduusing namespace SparcISA; 4210349Sandreas.hansson@arm.comusing namespace std; 432SN/A 442SN/A 457771Snate@binkert.orgvoid 4610349Sandreas.hansson@arm.comISA::checkSoftInt(ThreadContext *tc) 477771Snate@binkert.org{ 487771Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 491296SN/A 501296SN/A // If PIL < 14, copy over the tm and sm bits 512SN/A if (pil < 14 && softint & 0x10000) 5210349Sandreas.hansson@arm.com cpu->postInterrupt(0, IT_SOFT_INT, 16); 535190Ssaidi@eecs.umich.edu else 5410349Sandreas.hansson@arm.com cpu->clearInterrupt(0, IT_SOFT_INT, 16); 555190Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x1) 5610905Sandreas.sandberg@arm.com cpu->postInterrupt(0, IT_SOFT_INT, 0); 576214Snate@binkert.org else 5810905Sandreas.sandberg@arm.com cpu->clearInterrupt(0, IT_SOFT_INT, 0); 592SN/A 605190Ssaidi@eecs.umich.edu // Copy over any of the other bits that are set 612SN/A for (int bit = 15; bit > 0; --bit) { 6210905Sandreas.sandberg@arm.com if (1 << bit & softint && bit > pil) 635190Ssaidi@eecs.umich.edu cpu->postInterrupt(0, IT_SOFT_INT, bit); 642SN/A else 6510349Sandreas.hansson@arm.com cpu->clearInterrupt(0, IT_SOFT_INT, bit); 661954SN/A } 6710349Sandreas.hansson@arm.com} 685190Ssaidi@eecs.umich.edu 695190Ssaidi@eecs.umich.edu// These functions map register indices to names 7010349Sandreas.hansson@arm.comstatic inline string 715190Ssaidi@eecs.umich.edugetMiscRegName(RegIndex index) 725190Ssaidi@eecs.umich.edu{ 735190Ssaidi@eecs.umich.edu static string miscRegName[NumMiscRegs] = 745190Ssaidi@eecs.umich.edu {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 755190Ssaidi@eecs.umich.edu "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 765190Ssaidi@eecs.umich.edu "stick", "stick_cmpr", 7710349Sandreas.hansson@arm.com "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 7810349Sandreas.hansson@arm.com "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 7910349Sandreas.hansson@arm.com "wstate",*/ "gl", 8010349Sandreas.hansson@arm.com "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 815190Ssaidi@eecs.umich.edu "hstick_cmpr", 8210349Sandreas.hansson@arm.com "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 835190Ssaidi@eecs.umich.edu "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 845190Ssaidi@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 8510349Sandreas.hansson@arm.com "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 8610349Sandreas.hansson@arm.com "nresErrorHead", "nresErrorTail", "TlbData" }; 8710349Sandreas.hansson@arm.com return miscRegName[index]; 885190Ssaidi@eecs.umich.edu} 895190Ssaidi@eecs.umich.edu 905190Ssaidi@eecs.umich.eduvoid 9110349Sandreas.hansson@arm.comISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) 9210349Sandreas.hansson@arm.com{ 9310349Sandreas.hansson@arm.com BaseCPU *cpu = tc->getCpuPtr(); 9410349Sandreas.hansson@arm.com 9510349Sandreas.hansson@arm.com int64_t time; 9610349Sandreas.hansson@arm.com switch (miscReg) { 9710349Sandreas.hansson@arm.com /* Full system only ASRs */ 9810349Sandreas.hansson@arm.com case MISCREG_SOFTINT: 9910349Sandreas.hansson@arm.com setMiscRegNoEffect(miscReg, val);; 10010349Sandreas.hansson@arm.com checkSoftInt(tc); 1015190Ssaidi@eecs.umich.edu break; 1025190Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_CLR: 10310349Sandreas.hansson@arm.com return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 10410349Sandreas.hansson@arm.com case MISCREG_SOFTINT_SET: 1055190Ssaidi@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 1065190Ssaidi@eecs.umich.edu 10710905Sandreas.sandberg@arm.com case MISCREG_TICK_CMPR: 10810905Sandreas.sandberg@arm.com if (tickCompare == NULL) 1092SN/A tickCompare = new TickCompareEvent(this, tc); 1102SN/A setMiscRegNoEffect(miscReg, val); 1115190Ssaidi@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1122SN/A cpu->deschedule(tickCompare); 1131296SN/A time = (tick_cmpr & mask(63)) - (tick & mask(63)); 114 if (!(tick_cmpr & ~mask(63)) && time > 0) { 115 if (tickCompare->scheduled()) 116 cpu->deschedule(tickCompare); 117 cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time))); 118 } 119 DPRINTF(Timer, "writing to TICK compare register value %#X\n", val); 120 break; 121 122 case MISCREG_STICK_CMPR: 123 if (sTickCompare == NULL) 124 sTickCompare = new STickCompareEvent(this, tc); 125 setMiscRegNoEffect(miscReg, val); 126 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 127 cpu->deschedule(sTickCompare); 128 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 129 cpu->instCount(); 130 if (!(stick_cmpr & ~mask(63)) && time > 0) { 131 if (sTickCompare->scheduled()) 132 cpu->deschedule(sTickCompare); 133 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time))); 134 } 135 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 136 break; 137 138 case MISCREG_PSTATE: 139 setMiscRegNoEffect(miscReg, val); 140 break; 141 142 case MISCREG_PIL: 143 setMiscRegNoEffect(miscReg, val); 144 checkSoftInt(tc); 145 break; 146 147 case MISCREG_HVER: 148 panic("Shouldn't be writing HVER\n"); 149 150 case MISCREG_HINTP: 151 setMiscRegNoEffect(miscReg, val); 152 if (hintp) 153 cpu->postInterrupt(0, IT_HINTP, 0); 154 else 155 cpu->clearInterrupt(0, IT_HINTP, 0); 156 break; 157 158 case MISCREG_HTBA: 159 // clear lower 7 bits on writes. 160 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 161 break; 162 163 case MISCREG_QUEUE_CPU_MONDO_HEAD: 164 case MISCREG_QUEUE_CPU_MONDO_TAIL: 165 setMiscRegNoEffect(miscReg, val); 166 if (cpu_mondo_head != cpu_mondo_tail) 167 cpu->postInterrupt(0, IT_CPU_MONDO, 0); 168 else 169 cpu->clearInterrupt(0, IT_CPU_MONDO, 0); 170 break; 171 case MISCREG_QUEUE_DEV_MONDO_HEAD: 172 case MISCREG_QUEUE_DEV_MONDO_TAIL: 173 setMiscRegNoEffect(miscReg, val); 174 if (dev_mondo_head != dev_mondo_tail) 175 cpu->postInterrupt(0, IT_DEV_MONDO, 0); 176 else 177 cpu->clearInterrupt(0, IT_DEV_MONDO, 0); 178 break; 179 case MISCREG_QUEUE_RES_ERROR_HEAD: 180 case MISCREG_QUEUE_RES_ERROR_TAIL: 181 setMiscRegNoEffect(miscReg, val); 182 if (res_error_head != res_error_tail) 183 cpu->postInterrupt(0, IT_RES_ERROR, 0); 184 else 185 cpu->clearInterrupt(0, IT_RES_ERROR, 0); 186 break; 187 case MISCREG_QUEUE_NRES_ERROR_HEAD: 188 case MISCREG_QUEUE_NRES_ERROR_TAIL: 189 setMiscRegNoEffect(miscReg, val); 190 // This one doesn't have an interrupt to report to the guest OS 191 break; 192 193 case MISCREG_HSTICK_CMPR: 194 if (hSTickCompare == NULL) 195 hSTickCompare = new HSTickCompareEvent(this, tc); 196 setMiscRegNoEffect(miscReg, val); 197 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 198 cpu->deschedule(hSTickCompare); 199 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 200 cpu->instCount(); 201 if (!(hstick_cmpr & ~mask(63)) && time > 0) { 202 if (hSTickCompare->scheduled()) 203 cpu->deschedule(hSTickCompare); 204 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time))); 205 } 206 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 207 break; 208 209 case MISCREG_HPSTATE: 210 { 211 HPSTATE newVal = val; 212 newVal.id = 1; 213 // T1000 spec says impl. dependent val must always be 1 214 setMiscRegNoEffect(miscReg, newVal); 215 newVal = hpstate; 216 if (newVal.tlz && tl == 0 && !newVal.hpriv) 217 cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); 218 else 219 cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); 220 break; 221 } 222 case MISCREG_HTSTATE: 223 setMiscRegNoEffect(miscReg, val); 224 break; 225 226 case MISCREG_STRAND_STS_REG: 227 if (bits(val,2,2)) 228 panic("No support for setting spec_en bit\n"); 229 setMiscRegNoEffect(miscReg, bits(val,0,0)); 230 if (!bits(val,0,0)) { 231 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 232 // Time to go to sleep 233 tc->suspend(); 234 if (FullSystem && tc->getKernelStats()) 235 tc->getKernelStats()->quiesce(); 236 } 237 break; 238 239 default: 240 panic("Invalid write to FS misc register %s\n", 241 getMiscRegName(miscReg)); 242 } 243} 244 245RegVal 246ISA::readFSReg(int miscReg, ThreadContext * tc) 247{ 248 uint64_t temp; 249 250 switch (miscReg) { 251 /* Privileged registers. */ 252 case MISCREG_QUEUE_CPU_MONDO_HEAD: 253 case MISCREG_QUEUE_CPU_MONDO_TAIL: 254 case MISCREG_QUEUE_DEV_MONDO_HEAD: 255 case MISCREG_QUEUE_DEV_MONDO_TAIL: 256 case MISCREG_QUEUE_RES_ERROR_HEAD: 257 case MISCREG_QUEUE_RES_ERROR_TAIL: 258 case MISCREG_QUEUE_NRES_ERROR_HEAD: 259 case MISCREG_QUEUE_NRES_ERROR_TAIL: 260 case MISCREG_SOFTINT: 261 case MISCREG_TICK_CMPR: 262 case MISCREG_STICK_CMPR: 263 case MISCREG_PIL: 264 case MISCREG_HPSTATE: 265 case MISCREG_HINTP: 266 case MISCREG_HTSTATE: 267 case MISCREG_HSTICK_CMPR: 268 return readMiscRegNoEffect(miscReg) ; 269 270 case MISCREG_HTBA: 271 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); 272 case MISCREG_HVER: 273 // XXX set to match Legion 274 return ULL(0x3e) << 48 | 275 ULL(0x23) << 32 | 276 ULL(0x20) << 24 | 277 // MaxGL << 16 | XXX For some reason legion doesn't set GL 278 MaxTL << 8 | 279 (NWindows -1) << 0; 280 281 case MISCREG_STRAND_STS_REG: 282 System *sys; 283 int x; 284 sys = tc->getSystemPtr(); 285 286 temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); 287 // Check that the CPU array is fully populated 288 // (by calling getNumCPus()) 289 assert(sys->numContexts() > tc->contextId()); 290 291 temp |= tc->contextId() << STS::shft_id; 292 293 for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 294 switch (sys->threadContexts[x]->status()) { 295 case ThreadContext::Active: 296 temp |= STS::st_run << (STS::shft_fsm0 - 297 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 298 break; 299 case ThreadContext::Suspended: 300 // should this be idle? 301 temp |= STS::st_idle << (STS::shft_fsm0 - 302 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 303 break; 304 case ThreadContext::Halted: 305 temp |= STS::st_halt << (STS::shft_fsm0 - 306 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 307 break; 308 default: 309 panic("What state are we in?!\n"); 310 } // switch 311 } // for 312 313 return temp; 314 default: 315 panic("Invalid read to FS misc register\n"); 316 } 317} 318 319void 320ISA::processTickCompare(ThreadContext *tc) 321{ 322 panic("tick compare not implemented\n"); 323} 324 325void 326ISA::processSTickCompare(ThreadContext *tc) 327{ 328 BaseCPU *cpu = tc->getCpuPtr(); 329 330 // since our microcode instructions take two cycles we need to check if 331 // we're actually at the correct cycle or we need to wait a little while 332 // more 333 int delay; 334 delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 335 cpu->instCount(); 336 assert(delay >= 0 && "stick compare missed interrupt cycle"); 337 338 if (delay == 0 || tc->status() == ThreadContext::Suspended) { 339 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 340 (stick_cmpr & mask(63))); 341 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 342 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 343 } 344 } else { 345 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay))); 346 } 347} 348 349void 350ISA::processHSTickCompare(ThreadContext *tc) 351{ 352 BaseCPU *cpu = tc->getCpuPtr(); 353 354 // since our microcode instructions take two cycles we need to check if 355 // we're actually at the correct cycle or we need to wait a little while 356 // more 357 int delay; 358 if ( tc->status() == ThreadContext::Halted) 359 return; 360 361 delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 362 cpu->instCount(); 363 assert(delay >= 0 && "hstick compare missed interrupt cycle"); 364 365 if (delay == 0 || tc->status() == ThreadContext::Suspended) { 366 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 367 (stick_cmpr & mask(63))); 368 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 369 setMiscReg(MISCREG_HINTP, 1, tc); 370 } 371 // Need to do something to cause interrupt to happen here !!! @todo 372 } else { 373 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay))); 374 } 375} 376 377