ua2005.cc revision 8829
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu */ 282650Ssaidi@eecs.umich.edu 296335Sgblack@eecs.umich.edu#include "arch/sparc/isa.hh" 304194Ssaidi@eecs.umich.edu#include "arch/sparc/kernel_stats.hh" 316335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 368232Snate@binkert.org#include "debug/Quiesce.hh" 378232Snate@binkert.org#include "debug/Timer.hh" 384194Ssaidi@eecs.umich.edu#include "sim/system.hh" 398778Sgblack@eecs.umich.edu#include "sim/full_system.hh" 402650Ssaidi@eecs.umich.edu 413817Ssaidi@eecs.umich.eduusing namespace SparcISA; 425946Sgblack@eecs.umich.eduusing namespace std; 433817Ssaidi@eecs.umich.edu 444103Ssaidi@eecs.umich.edu 454103Ssaidi@eecs.umich.eduvoid 466335Sgblack@eecs.umich.eduISA::checkSoftInt(ThreadContext *tc) 474103Ssaidi@eecs.umich.edu{ 485531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 495531Snate@binkert.org 504103Ssaidi@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 514103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x10000) 525704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 16); 534103Ssaidi@eecs.umich.edu else 545704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 16); 554103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x1) 565704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 0); 574103Ssaidi@eecs.umich.edu else 585704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 0); 594103Ssaidi@eecs.umich.edu 604103Ssaidi@eecs.umich.edu // Copy over any of the other bits that are set 614103Ssaidi@eecs.umich.edu for (int bit = 15; bit > 0; --bit) { 624103Ssaidi@eecs.umich.edu if (1 << bit & softint && bit > pil) 635704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, bit); 644103Ssaidi@eecs.umich.edu else 655704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, bit); 664103Ssaidi@eecs.umich.edu } 674103Ssaidi@eecs.umich.edu} 684103Ssaidi@eecs.umich.edu 697741Sgblack@eecs.umich.edu// These functions map register indices to names 705946Sgblack@eecs.umich.edustatic inline string 715946Sgblack@eecs.umich.edugetMiscRegName(RegIndex index) 725946Sgblack@eecs.umich.edu{ 735946Sgblack@eecs.umich.edu static string miscRegName[NumMiscRegs] = 745946Sgblack@eecs.umich.edu {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 755946Sgblack@eecs.umich.edu "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 765946Sgblack@eecs.umich.edu "stick", "stick_cmpr", 775946Sgblack@eecs.umich.edu "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 785946Sgblack@eecs.umich.edu "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 795946Sgblack@eecs.umich.edu "wstate",*/ "gl", 805946Sgblack@eecs.umich.edu "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 815946Sgblack@eecs.umich.edu "hstick_cmpr", 825946Sgblack@eecs.umich.edu "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 835946Sgblack@eecs.umich.edu "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 845946Sgblack@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 855946Sgblack@eecs.umich.edu "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 865946Sgblack@eecs.umich.edu "nresErrorHead", "nresErrorTail", "TlbData" }; 875946Sgblack@eecs.umich.edu return miscRegName[index]; 885946Sgblack@eecs.umich.edu} 894103Ssaidi@eecs.umich.edu 903817Ssaidi@eecs.umich.eduvoid 916335Sgblack@eecs.umich.eduISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 922650Ssaidi@eecs.umich.edu{ 935531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 945531Snate@binkert.org 952650Ssaidi@eecs.umich.edu int64_t time; 962650Ssaidi@eecs.umich.edu switch (miscReg) { 972982Sstever@eecs.umich.edu /* Full system only ASRs */ 983919Shsul@eecs.umich.edu case MISCREG_SOFTINT: 996335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val);; 1004103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1013919Shsul@eecs.umich.edu break; 1023919Shsul@eecs.umich.edu case MISCREG_SOFTINT_CLR: 1036335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 1043919Shsul@eecs.umich.edu case MISCREG_SOFTINT_SET: 1056335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 1062650Ssaidi@eecs.umich.edu 1073919Shsul@eecs.umich.edu case MISCREG_TICK_CMPR: 1083919Shsul@eecs.umich.edu if (tickCompare == NULL) 1093919Shsul@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 1106335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1114103Ssaidi@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1125606Snate@binkert.org cpu->deschedule(tickCompare); 1133919Shsul@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1144103Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 1154103Ssaidi@eecs.umich.edu if (tickCompare->scheduled()) 1165606Snate@binkert.org cpu->deschedule(tickCompare); 1177823Ssteve.reinhardt@amd.com cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1)); 1184103Ssaidi@eecs.umich.edu } 1193919Shsul@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 1203919Shsul@eecs.umich.edu break; 1212650Ssaidi@eecs.umich.edu 1223919Shsul@eecs.umich.edu case MISCREG_STICK_CMPR: 1233919Shsul@eecs.umich.edu if (sTickCompare == NULL) 1243919Shsul@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 1256335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1263919Shsul@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1275606Snate@binkert.org cpu->deschedule(sTickCompare); 1283919Shsul@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1295531Snate@binkert.org cpu->instCount(); 1304103Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) { 1314103Ssaidi@eecs.umich.edu if (sTickCompare->scheduled()) 1325606Snate@binkert.org cpu->deschedule(sTickCompare); 1337823Ssteve.reinhardt@amd.com cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1)); 1344103Ssaidi@eecs.umich.edu } 1353919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1363919Shsul@eecs.umich.edu break; 1372650Ssaidi@eecs.umich.edu 1383919Shsul@eecs.umich.edu case MISCREG_PSTATE: 1396335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1403827Shsul@eecs.umich.edu 1413919Shsul@eecs.umich.edu case MISCREG_PIL: 1426335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1434103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1443919Shsul@eecs.umich.edu break; 1452650Ssaidi@eecs.umich.edu 1463919Shsul@eecs.umich.edu case MISCREG_HVER: 1473919Shsul@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 1482650Ssaidi@eecs.umich.edu 1493921Shsul@eecs.umich.edu case MISCREG_HINTP: 1506335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1514103Ssaidi@eecs.umich.edu if (hintp) 1525704Snate@binkert.org cpu->postInterrupt(IT_HINTP, 0); 1534103Ssaidi@eecs.umich.edu else 1545704Snate@binkert.org cpu->clearInterrupt(IT_HINTP, 0); 1554103Ssaidi@eecs.umich.edu break; 1563921Shsul@eecs.umich.edu 1573919Shsul@eecs.umich.edu case MISCREG_HTBA: 1583919Shsul@eecs.umich.edu // clear lower 7 bits on writes. 1596335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1603919Shsul@eecs.umich.edu break; 1612650Ssaidi@eecs.umich.edu 1623919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1633919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1646335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1654103Ssaidi@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 1665704Snate@binkert.org cpu->postInterrupt(IT_CPU_MONDO, 0); 1674103Ssaidi@eecs.umich.edu else 1685704Snate@binkert.org cpu->clearInterrupt(IT_CPU_MONDO, 0); 1694103Ssaidi@eecs.umich.edu break; 1703919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1713919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1726335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1734103Ssaidi@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 1745704Snate@binkert.org cpu->postInterrupt(IT_DEV_MONDO, 0); 1754103Ssaidi@eecs.umich.edu else 1765704Snate@binkert.org cpu->clearInterrupt(IT_DEV_MONDO, 0); 1774103Ssaidi@eecs.umich.edu break; 1783919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1793919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1806335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1814103Ssaidi@eecs.umich.edu if (res_error_head != res_error_tail) 1825704Snate@binkert.org cpu->postInterrupt(IT_RES_ERROR, 0); 1834103Ssaidi@eecs.umich.edu else 1845704Snate@binkert.org cpu->clearInterrupt(IT_RES_ERROR, 0); 1854103Ssaidi@eecs.umich.edu break; 1863919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1873919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1886335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1894103Ssaidi@eecs.umich.edu // This one doesn't have an interrupt to report to the guest OS 1903919Shsul@eecs.umich.edu break; 1913828Shsul@eecs.umich.edu 1923919Shsul@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1933919Shsul@eecs.umich.edu if (hSTickCompare == NULL) 1943919Shsul@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1956335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1963919Shsul@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1975606Snate@binkert.org cpu->deschedule(hSTickCompare); 1983919Shsul@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1995531Snate@binkert.org cpu->instCount(); 2004103Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) { 2014103Ssaidi@eecs.umich.edu if (hSTickCompare->scheduled()) 2025606Snate@binkert.org cpu->deschedule(hSTickCompare); 2037823Ssteve.reinhardt@amd.com cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1)); 2044103Ssaidi@eecs.umich.edu } 2053919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2063919Shsul@eecs.umich.edu break; 2073817Ssaidi@eecs.umich.edu 2083919Shsul@eecs.umich.edu case MISCREG_HPSTATE: 2098829Sgblack@eecs.umich.edu { 2108829Sgblack@eecs.umich.edu HPSTATE newVal = val; 2118829Sgblack@eecs.umich.edu newVal.id = 1; 2128829Sgblack@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 2138829Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, newVal); 2148829Sgblack@eecs.umich.edu newVal = hpstate; 2158829Sgblack@eecs.umich.edu if (newVal.tlz && tl == 0 && !newVal.hpriv) 2168829Sgblack@eecs.umich.edu cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2178829Sgblack@eecs.umich.edu else 2188829Sgblack@eecs.umich.edu cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2198829Sgblack@eecs.umich.edu break; 2208829Sgblack@eecs.umich.edu } 2213919Shsul@eecs.umich.edu case MISCREG_HTSTATE: 2226335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 2234194Ssaidi@eecs.umich.edu break; 2244194Ssaidi@eecs.umich.edu 2253919Shsul@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2264194Ssaidi@eecs.umich.edu if (bits(val,2,2)) 2274194Ssaidi@eecs.umich.edu panic("No support for setting spec_en bit\n"); 2286335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, bits(val,0,0)); 2294194Ssaidi@eecs.umich.edu if (!bits(val,0,0)) { 2304216Ssaidi@eecs.umich.edu DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2314194Ssaidi@eecs.umich.edu // Time to go to sleep 2324194Ssaidi@eecs.umich.edu tc->suspend(); 2338778Sgblack@eecs.umich.edu if (FullSystem && tc->getKernelStats()) 2344194Ssaidi@eecs.umich.edu tc->getKernelStats()->quiesce(); 2355531Snate@binkert.org } 2363919Shsul@eecs.umich.edu break; 2373817Ssaidi@eecs.umich.edu 2383919Shsul@eecs.umich.edu default: 2395531Snate@binkert.org panic("Invalid write to FS misc register %s\n", 2405531Snate@binkert.org getMiscRegName(miscReg)); 2412650Ssaidi@eecs.umich.edu } 2422650Ssaidi@eecs.umich.edu} 2432650Ssaidi@eecs.umich.edu 2442650Ssaidi@eecs.umich.eduMiscReg 2456335Sgblack@eecs.umich.eduISA::readFSReg(int miscReg, ThreadContext * tc) 2462650Ssaidi@eecs.umich.edu{ 2474194Ssaidi@eecs.umich.edu uint64_t temp; 2484194Ssaidi@eecs.umich.edu 2492650Ssaidi@eecs.umich.edu switch (miscReg) { 2503919Shsul@eecs.umich.edu /* Privileged registers. */ 2513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2543825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2553825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2563825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2573825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2583825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2593825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 2603825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 2613825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 2623825Ssaidi@eecs.umich.edu case MISCREG_PIL: 2633825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 2643825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 2653825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 2663825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2676335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) ; 2682650Ssaidi@eecs.umich.edu 2693825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 2706335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); 2713825Ssaidi@eecs.umich.edu case MISCREG_HVER: 2724207Ssaidi@eecs.umich.edu // XXX set to match Legion 2734207Ssaidi@eecs.umich.edu return ULL(0x3e) << 48 | 2744207Ssaidi@eecs.umich.edu ULL(0x23) << 32 | 2754207Ssaidi@eecs.umich.edu ULL(0x20) << 24 | 2767741Sgblack@eecs.umich.edu // MaxGL << 16 | XXX For some reason legion doesn't set GL 2774207Ssaidi@eecs.umich.edu MaxTL << 8 | 2784207Ssaidi@eecs.umich.edu (NWindows -1) << 0; 2792650Ssaidi@eecs.umich.edu 2804194Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2814194Ssaidi@eecs.umich.edu System *sys; 2824194Ssaidi@eecs.umich.edu int x; 2834194Ssaidi@eecs.umich.edu sys = tc->getSystemPtr(); 2844194Ssaidi@eecs.umich.edu 2856335Sgblack@eecs.umich.edu temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); 2865531Snate@binkert.org // Check that the CPU array is fully populated 2875531Snate@binkert.org // (by calling getNumCPus()) 2885720Snate@binkert.org assert(sys->numContexts() > tc->contextId()); 2894194Ssaidi@eecs.umich.edu 2905714Shsul@eecs.umich.edu temp |= tc->contextId() << STS::shft_id; 2914194Ssaidi@eecs.umich.edu 2925714Shsul@eecs.umich.edu for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 2934194Ssaidi@eecs.umich.edu switch (sys->threadContexts[x]->status()) { 2944194Ssaidi@eecs.umich.edu case ThreadContext::Active: 2954194Ssaidi@eecs.umich.edu temp |= STS::st_run << (STS::shft_fsm0 - 2964194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2974194Ssaidi@eecs.umich.edu break; 2984194Ssaidi@eecs.umich.edu case ThreadContext::Suspended: 2994194Ssaidi@eecs.umich.edu // should this be idle? 3004194Ssaidi@eecs.umich.edu temp |= STS::st_idle << (STS::shft_fsm0 - 3014194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 3024194Ssaidi@eecs.umich.edu break; 3034194Ssaidi@eecs.umich.edu case ThreadContext::Halted: 3044194Ssaidi@eecs.umich.edu temp |= STS::st_halt << (STS::shft_fsm0 - 3054194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 3064194Ssaidi@eecs.umich.edu break; 3074194Ssaidi@eecs.umich.edu default: 3084194Ssaidi@eecs.umich.edu panic("What state are we in?!\n"); 3094194Ssaidi@eecs.umich.edu } // switch 3104194Ssaidi@eecs.umich.edu } // for 3114194Ssaidi@eecs.umich.edu 3124194Ssaidi@eecs.umich.edu return temp; 3133825Ssaidi@eecs.umich.edu default: 3143825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 3152650Ssaidi@eecs.umich.edu } 3162650Ssaidi@eecs.umich.edu} 3172650Ssaidi@eecs.umich.edu 3182651Ssaidi@eecs.umich.eduvoid 3196335Sgblack@eecs.umich.eduISA::processTickCompare(ThreadContext *tc) 3202651Ssaidi@eecs.umich.edu{ 3212651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 3222651Ssaidi@eecs.umich.edu} 3232651Ssaidi@eecs.umich.edu 3242651Ssaidi@eecs.umich.eduvoid 3256335Sgblack@eecs.umich.eduISA::processSTickCompare(ThreadContext *tc) 3262651Ssaidi@eecs.umich.edu{ 3275606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3285606Snate@binkert.org 3293888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3303888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3313888Ssaidi@eecs.umich.edu // more 3323888Ssaidi@eecs.umich.edu int ticks; 3333890Ssaidi@eecs.umich.edu ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 3345606Snate@binkert.org cpu->instCount(); 3353888Ssaidi@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 3363888Ssaidi@eecs.umich.edu 3374216Ssaidi@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3383888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 3393888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3404172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 3416335Sgblack@eecs.umich.edu setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 3423921Shsul@eecs.umich.edu } 3437741Sgblack@eecs.umich.edu } else { 3447823Ssteve.reinhardt@amd.com cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1)); 3457741Sgblack@eecs.umich.edu } 3462651Ssaidi@eecs.umich.edu} 3472651Ssaidi@eecs.umich.edu 3482651Ssaidi@eecs.umich.eduvoid 3496335Sgblack@eecs.umich.eduISA::processHSTickCompare(ThreadContext *tc) 3502651Ssaidi@eecs.umich.edu{ 3515606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3525606Snate@binkert.org 3533891Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3543891Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3553891Ssaidi@eecs.umich.edu // more 3563891Ssaidi@eecs.umich.edu int ticks; 3576029Ssteve.reinhardt@amd.com if ( tc->status() == ThreadContext::Halted) 3584216Ssaidi@eecs.umich.edu return; 3594216Ssaidi@eecs.umich.edu 3603891Ssaidi@eecs.umich.edu ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 3615606Snate@binkert.org cpu->instCount(); 3623891Ssaidi@eecs.umich.edu assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 3633891Ssaidi@eecs.umich.edu 3644216Ssaidi@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3653891Ssaidi@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 3663891Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3674172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 3686335Sgblack@eecs.umich.edu setMiscReg(MISCREG_HINTP, 1, tc); 3693921Shsul@eecs.umich.edu } 3703891Ssaidi@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 3717741Sgblack@eecs.umich.edu } else { 3727823Ssteve.reinhardt@amd.com cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1)); 3737741Sgblack@eecs.umich.edu } 3742651Ssaidi@eecs.umich.edu} 3752650Ssaidi@eecs.umich.edu 376