ua2005.cc revision 8232
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu */ 282650Ssaidi@eecs.umich.edu 296335Sgblack@eecs.umich.edu#include "arch/sparc/isa.hh" 304194Ssaidi@eecs.umich.edu#include "arch/sparc/kernel_stats.hh" 316335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 368232Snate@binkert.org#include "debug/Quiesce.hh" 378232Snate@binkert.org#include "debug/Timer.hh" 384194Ssaidi@eecs.umich.edu#include "sim/system.hh" 392650Ssaidi@eecs.umich.edu 403817Ssaidi@eecs.umich.eduusing namespace SparcISA; 415946Sgblack@eecs.umich.eduusing namespace std; 423817Ssaidi@eecs.umich.edu 434103Ssaidi@eecs.umich.edu 444103Ssaidi@eecs.umich.eduvoid 456335Sgblack@eecs.umich.eduISA::checkSoftInt(ThreadContext *tc) 464103Ssaidi@eecs.umich.edu{ 475531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 485531Snate@binkert.org 494103Ssaidi@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 504103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x10000) 515704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 16); 524103Ssaidi@eecs.umich.edu else 535704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 16); 544103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x1) 555704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 0); 564103Ssaidi@eecs.umich.edu else 575704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 0); 584103Ssaidi@eecs.umich.edu 594103Ssaidi@eecs.umich.edu // Copy over any of the other bits that are set 604103Ssaidi@eecs.umich.edu for (int bit = 15; bit > 0; --bit) { 614103Ssaidi@eecs.umich.edu if (1 << bit & softint && bit > pil) 625704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, bit); 634103Ssaidi@eecs.umich.edu else 645704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, bit); 654103Ssaidi@eecs.umich.edu } 664103Ssaidi@eecs.umich.edu} 674103Ssaidi@eecs.umich.edu 687741Sgblack@eecs.umich.edu// These functions map register indices to names 695946Sgblack@eecs.umich.edustatic inline string 705946Sgblack@eecs.umich.edugetMiscRegName(RegIndex index) 715946Sgblack@eecs.umich.edu{ 725946Sgblack@eecs.umich.edu static string miscRegName[NumMiscRegs] = 735946Sgblack@eecs.umich.edu {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 745946Sgblack@eecs.umich.edu "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 755946Sgblack@eecs.umich.edu "stick", "stick_cmpr", 765946Sgblack@eecs.umich.edu "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 775946Sgblack@eecs.umich.edu "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 785946Sgblack@eecs.umich.edu "wstate",*/ "gl", 795946Sgblack@eecs.umich.edu "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 805946Sgblack@eecs.umich.edu "hstick_cmpr", 815946Sgblack@eecs.umich.edu "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 825946Sgblack@eecs.umich.edu "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 835946Sgblack@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 845946Sgblack@eecs.umich.edu "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 855946Sgblack@eecs.umich.edu "nresErrorHead", "nresErrorTail", "TlbData" }; 865946Sgblack@eecs.umich.edu return miscRegName[index]; 875946Sgblack@eecs.umich.edu} 884103Ssaidi@eecs.umich.edu 893817Ssaidi@eecs.umich.eduvoid 906335Sgblack@eecs.umich.eduISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 912650Ssaidi@eecs.umich.edu{ 925531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 935531Snate@binkert.org 942650Ssaidi@eecs.umich.edu int64_t time; 952650Ssaidi@eecs.umich.edu switch (miscReg) { 962982Sstever@eecs.umich.edu /* Full system only ASRs */ 973919Shsul@eecs.umich.edu case MISCREG_SOFTINT: 986335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val);; 994103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1003919Shsul@eecs.umich.edu break; 1013919Shsul@eecs.umich.edu case MISCREG_SOFTINT_CLR: 1026335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 1033919Shsul@eecs.umich.edu case MISCREG_SOFTINT_SET: 1046335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 1052650Ssaidi@eecs.umich.edu 1063919Shsul@eecs.umich.edu case MISCREG_TICK_CMPR: 1073919Shsul@eecs.umich.edu if (tickCompare == NULL) 1083919Shsul@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 1096335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1104103Ssaidi@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1115606Snate@binkert.org cpu->deschedule(tickCompare); 1123919Shsul@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1134103Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 1144103Ssaidi@eecs.umich.edu if (tickCompare->scheduled()) 1155606Snate@binkert.org cpu->deschedule(tickCompare); 1167823Ssteve.reinhardt@amd.com cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1)); 1174103Ssaidi@eecs.umich.edu } 1183919Shsul@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 1193919Shsul@eecs.umich.edu break; 1202650Ssaidi@eecs.umich.edu 1213919Shsul@eecs.umich.edu case MISCREG_STICK_CMPR: 1223919Shsul@eecs.umich.edu if (sTickCompare == NULL) 1233919Shsul@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 1246335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1253919Shsul@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1265606Snate@binkert.org cpu->deschedule(sTickCompare); 1273919Shsul@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1285531Snate@binkert.org cpu->instCount(); 1294103Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) { 1304103Ssaidi@eecs.umich.edu if (sTickCompare->scheduled()) 1315606Snate@binkert.org cpu->deschedule(sTickCompare); 1327823Ssteve.reinhardt@amd.com cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1)); 1334103Ssaidi@eecs.umich.edu } 1343919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1353919Shsul@eecs.umich.edu break; 1362650Ssaidi@eecs.umich.edu 1373919Shsul@eecs.umich.edu case MISCREG_PSTATE: 1386335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1393827Shsul@eecs.umich.edu 1403919Shsul@eecs.umich.edu case MISCREG_PIL: 1416335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1424103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1433919Shsul@eecs.umich.edu break; 1442650Ssaidi@eecs.umich.edu 1453919Shsul@eecs.umich.edu case MISCREG_HVER: 1463919Shsul@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 1472650Ssaidi@eecs.umich.edu 1483921Shsul@eecs.umich.edu case MISCREG_HINTP: 1496335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1504103Ssaidi@eecs.umich.edu if (hintp) 1515704Snate@binkert.org cpu->postInterrupt(IT_HINTP, 0); 1524103Ssaidi@eecs.umich.edu else 1535704Snate@binkert.org cpu->clearInterrupt(IT_HINTP, 0); 1544103Ssaidi@eecs.umich.edu break; 1553921Shsul@eecs.umich.edu 1563919Shsul@eecs.umich.edu case MISCREG_HTBA: 1573919Shsul@eecs.umich.edu // clear lower 7 bits on writes. 1586335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1593919Shsul@eecs.umich.edu break; 1602650Ssaidi@eecs.umich.edu 1613919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1623919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1636335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1644103Ssaidi@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 1655704Snate@binkert.org cpu->postInterrupt(IT_CPU_MONDO, 0); 1664103Ssaidi@eecs.umich.edu else 1675704Snate@binkert.org cpu->clearInterrupt(IT_CPU_MONDO, 0); 1684103Ssaidi@eecs.umich.edu break; 1693919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1703919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1716335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1724103Ssaidi@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 1735704Snate@binkert.org cpu->postInterrupt(IT_DEV_MONDO, 0); 1744103Ssaidi@eecs.umich.edu else 1755704Snate@binkert.org cpu->clearInterrupt(IT_DEV_MONDO, 0); 1764103Ssaidi@eecs.umich.edu break; 1773919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1783919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1796335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1804103Ssaidi@eecs.umich.edu if (res_error_head != res_error_tail) 1815704Snate@binkert.org cpu->postInterrupt(IT_RES_ERROR, 0); 1824103Ssaidi@eecs.umich.edu else 1835704Snate@binkert.org cpu->clearInterrupt(IT_RES_ERROR, 0); 1844103Ssaidi@eecs.umich.edu break; 1853919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1863919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1876335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1884103Ssaidi@eecs.umich.edu // This one doesn't have an interrupt to report to the guest OS 1893919Shsul@eecs.umich.edu break; 1903828Shsul@eecs.umich.edu 1913919Shsul@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1923919Shsul@eecs.umich.edu if (hSTickCompare == NULL) 1933919Shsul@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1946335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1953919Shsul@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1965606Snate@binkert.org cpu->deschedule(hSTickCompare); 1973919Shsul@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1985531Snate@binkert.org cpu->instCount(); 1994103Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) { 2004103Ssaidi@eecs.umich.edu if (hSTickCompare->scheduled()) 2015606Snate@binkert.org cpu->deschedule(hSTickCompare); 2027823Ssteve.reinhardt@amd.com cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1)); 2034103Ssaidi@eecs.umich.edu } 2043919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2053919Shsul@eecs.umich.edu break; 2063817Ssaidi@eecs.umich.edu 2073919Shsul@eecs.umich.edu case MISCREG_HPSTATE: 2083919Shsul@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 2096335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val | HPSTATE::id); 2104103Ssaidi@eecs.umich.edu#if FULL_SYSTEM 2114103Ssaidi@eecs.umich.edu if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 2125704Snate@binkert.org cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2134103Ssaidi@eecs.umich.edu else 2145704Snate@binkert.org cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2154103Ssaidi@eecs.umich.edu#endif 2163919Shsul@eecs.umich.edu break; 2173919Shsul@eecs.umich.edu case MISCREG_HTSTATE: 2186335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 2194194Ssaidi@eecs.umich.edu break; 2204194Ssaidi@eecs.umich.edu 2213919Shsul@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2224194Ssaidi@eecs.umich.edu if (bits(val,2,2)) 2234194Ssaidi@eecs.umich.edu panic("No support for setting spec_en bit\n"); 2246335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, bits(val,0,0)); 2254194Ssaidi@eecs.umich.edu if (!bits(val,0,0)) { 2264216Ssaidi@eecs.umich.edu DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2274194Ssaidi@eecs.umich.edu // Time to go to sleep 2284194Ssaidi@eecs.umich.edu tc->suspend(); 2294194Ssaidi@eecs.umich.edu if (tc->getKernelStats()) 2304194Ssaidi@eecs.umich.edu tc->getKernelStats()->quiesce(); 2315531Snate@binkert.org } 2323919Shsul@eecs.umich.edu break; 2333817Ssaidi@eecs.umich.edu 2343919Shsul@eecs.umich.edu default: 2355531Snate@binkert.org panic("Invalid write to FS misc register %s\n", 2365531Snate@binkert.org getMiscRegName(miscReg)); 2372650Ssaidi@eecs.umich.edu } 2382650Ssaidi@eecs.umich.edu} 2392650Ssaidi@eecs.umich.edu 2402650Ssaidi@eecs.umich.eduMiscReg 2416335Sgblack@eecs.umich.eduISA::readFSReg(int miscReg, ThreadContext * tc) 2422650Ssaidi@eecs.umich.edu{ 2434194Ssaidi@eecs.umich.edu uint64_t temp; 2444194Ssaidi@eecs.umich.edu 2452650Ssaidi@eecs.umich.edu switch (miscReg) { 2463919Shsul@eecs.umich.edu /* Privileged registers. */ 2473825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2483825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2493825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2503825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2543825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2553825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 2563825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 2573825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 2583825Ssaidi@eecs.umich.edu case MISCREG_PIL: 2593825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 2603825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 2613825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 2623825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2636335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) ; 2642650Ssaidi@eecs.umich.edu 2653825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 2666335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); 2673825Ssaidi@eecs.umich.edu case MISCREG_HVER: 2684207Ssaidi@eecs.umich.edu // XXX set to match Legion 2694207Ssaidi@eecs.umich.edu return ULL(0x3e) << 48 | 2704207Ssaidi@eecs.umich.edu ULL(0x23) << 32 | 2714207Ssaidi@eecs.umich.edu ULL(0x20) << 24 | 2727741Sgblack@eecs.umich.edu // MaxGL << 16 | XXX For some reason legion doesn't set GL 2734207Ssaidi@eecs.umich.edu MaxTL << 8 | 2744207Ssaidi@eecs.umich.edu (NWindows -1) << 0; 2752650Ssaidi@eecs.umich.edu 2764194Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2774194Ssaidi@eecs.umich.edu System *sys; 2784194Ssaidi@eecs.umich.edu int x; 2794194Ssaidi@eecs.umich.edu sys = tc->getSystemPtr(); 2804194Ssaidi@eecs.umich.edu 2816335Sgblack@eecs.umich.edu temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); 2825531Snate@binkert.org // Check that the CPU array is fully populated 2835531Snate@binkert.org // (by calling getNumCPus()) 2845720Snate@binkert.org assert(sys->numContexts() > tc->contextId()); 2854194Ssaidi@eecs.umich.edu 2865714Shsul@eecs.umich.edu temp |= tc->contextId() << STS::shft_id; 2874194Ssaidi@eecs.umich.edu 2885714Shsul@eecs.umich.edu for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 2894194Ssaidi@eecs.umich.edu switch (sys->threadContexts[x]->status()) { 2904194Ssaidi@eecs.umich.edu case ThreadContext::Active: 2914194Ssaidi@eecs.umich.edu temp |= STS::st_run << (STS::shft_fsm0 - 2924194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2934194Ssaidi@eecs.umich.edu break; 2944194Ssaidi@eecs.umich.edu case ThreadContext::Suspended: 2954194Ssaidi@eecs.umich.edu // should this be idle? 2964194Ssaidi@eecs.umich.edu temp |= STS::st_idle << (STS::shft_fsm0 - 2974194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2984194Ssaidi@eecs.umich.edu break; 2994194Ssaidi@eecs.umich.edu case ThreadContext::Halted: 3004194Ssaidi@eecs.umich.edu temp |= STS::st_halt << (STS::shft_fsm0 - 3014194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 3024194Ssaidi@eecs.umich.edu break; 3034194Ssaidi@eecs.umich.edu default: 3044194Ssaidi@eecs.umich.edu panic("What state are we in?!\n"); 3054194Ssaidi@eecs.umich.edu } // switch 3064194Ssaidi@eecs.umich.edu } // for 3074194Ssaidi@eecs.umich.edu 3084194Ssaidi@eecs.umich.edu return temp; 3093825Ssaidi@eecs.umich.edu default: 3103825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 3112650Ssaidi@eecs.umich.edu } 3122650Ssaidi@eecs.umich.edu} 3132650Ssaidi@eecs.umich.edu 3142651Ssaidi@eecs.umich.eduvoid 3156335Sgblack@eecs.umich.eduISA::processTickCompare(ThreadContext *tc) 3162651Ssaidi@eecs.umich.edu{ 3172651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 3182651Ssaidi@eecs.umich.edu} 3192651Ssaidi@eecs.umich.edu 3202651Ssaidi@eecs.umich.eduvoid 3216335Sgblack@eecs.umich.eduISA::processSTickCompare(ThreadContext *tc) 3222651Ssaidi@eecs.umich.edu{ 3235606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3245606Snate@binkert.org 3253888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3263888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3273888Ssaidi@eecs.umich.edu // more 3283888Ssaidi@eecs.umich.edu int ticks; 3293890Ssaidi@eecs.umich.edu ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 3305606Snate@binkert.org cpu->instCount(); 3313888Ssaidi@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 3323888Ssaidi@eecs.umich.edu 3334216Ssaidi@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3343888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 3353888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3364172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 3376335Sgblack@eecs.umich.edu setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 3383921Shsul@eecs.umich.edu } 3397741Sgblack@eecs.umich.edu } else { 3407823Ssteve.reinhardt@amd.com cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1)); 3417741Sgblack@eecs.umich.edu } 3422651Ssaidi@eecs.umich.edu} 3432651Ssaidi@eecs.umich.edu 3442651Ssaidi@eecs.umich.eduvoid 3456335Sgblack@eecs.umich.eduISA::processHSTickCompare(ThreadContext *tc) 3462651Ssaidi@eecs.umich.edu{ 3475606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3485606Snate@binkert.org 3493891Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3503891Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3513891Ssaidi@eecs.umich.edu // more 3523891Ssaidi@eecs.umich.edu int ticks; 3536029Ssteve.reinhardt@amd.com if ( tc->status() == ThreadContext::Halted) 3544216Ssaidi@eecs.umich.edu return; 3554216Ssaidi@eecs.umich.edu 3563891Ssaidi@eecs.umich.edu ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 3575606Snate@binkert.org cpu->instCount(); 3583891Ssaidi@eecs.umich.edu assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 3593891Ssaidi@eecs.umich.edu 3604216Ssaidi@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3613891Ssaidi@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 3623891Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3634172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 3646335Sgblack@eecs.umich.edu setMiscReg(MISCREG_HINTP, 1, tc); 3653921Shsul@eecs.umich.edu } 3663891Ssaidi@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 3677741Sgblack@eecs.umich.edu } else { 3687823Ssteve.reinhardt@amd.com cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1)); 3697741Sgblack@eecs.umich.edu } 3702651Ssaidi@eecs.umich.edu} 3712650Ssaidi@eecs.umich.edu 372