ua2005.cc revision 6335
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu */ 282650Ssaidi@eecs.umich.edu 296335Sgblack@eecs.umich.edu#include "arch/sparc/isa.hh" 304194Ssaidi@eecs.umich.edu#include "arch/sparc/kernel_stats.hh" 316335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 364194Ssaidi@eecs.umich.edu#include "sim/system.hh" 372650Ssaidi@eecs.umich.edu 383817Ssaidi@eecs.umich.eduusing namespace SparcISA; 395946Sgblack@eecs.umich.eduusing namespace std; 403817Ssaidi@eecs.umich.edu 414103Ssaidi@eecs.umich.edu 424103Ssaidi@eecs.umich.eduvoid 436335Sgblack@eecs.umich.eduISA::checkSoftInt(ThreadContext *tc) 444103Ssaidi@eecs.umich.edu{ 455531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 465531Snate@binkert.org 474103Ssaidi@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 484103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x10000) 495704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 16); 504103Ssaidi@eecs.umich.edu else 515704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 16); 524103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x1) 535704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 0); 544103Ssaidi@eecs.umich.edu else 555704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 0); 564103Ssaidi@eecs.umich.edu 574103Ssaidi@eecs.umich.edu // Copy over any of the other bits that are set 584103Ssaidi@eecs.umich.edu for (int bit = 15; bit > 0; --bit) { 594103Ssaidi@eecs.umich.edu if (1 << bit & softint && bit > pil) 605704Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, bit); 614103Ssaidi@eecs.umich.edu else 625704Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, bit); 634103Ssaidi@eecs.umich.edu } 644103Ssaidi@eecs.umich.edu} 654103Ssaidi@eecs.umich.edu 665946Sgblack@eecs.umich.edu//These functions map register indices to names 675946Sgblack@eecs.umich.edustatic inline string 685946Sgblack@eecs.umich.edugetMiscRegName(RegIndex index) 695946Sgblack@eecs.umich.edu{ 705946Sgblack@eecs.umich.edu static string miscRegName[NumMiscRegs] = 715946Sgblack@eecs.umich.edu {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 725946Sgblack@eecs.umich.edu "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 735946Sgblack@eecs.umich.edu "stick", "stick_cmpr", 745946Sgblack@eecs.umich.edu "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 755946Sgblack@eecs.umich.edu "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 765946Sgblack@eecs.umich.edu "wstate",*/ "gl", 775946Sgblack@eecs.umich.edu "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 785946Sgblack@eecs.umich.edu "hstick_cmpr", 795946Sgblack@eecs.umich.edu "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 805946Sgblack@eecs.umich.edu "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 815946Sgblack@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 825946Sgblack@eecs.umich.edu "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 835946Sgblack@eecs.umich.edu "nresErrorHead", "nresErrorTail", "TlbData" }; 845946Sgblack@eecs.umich.edu return miscRegName[index]; 855946Sgblack@eecs.umich.edu} 864103Ssaidi@eecs.umich.edu 873817Ssaidi@eecs.umich.eduvoid 886335Sgblack@eecs.umich.eduISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 892650Ssaidi@eecs.umich.edu{ 905531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 915531Snate@binkert.org 922650Ssaidi@eecs.umich.edu int64_t time; 932650Ssaidi@eecs.umich.edu switch (miscReg) { 942982Sstever@eecs.umich.edu /* Full system only ASRs */ 953919Shsul@eecs.umich.edu case MISCREG_SOFTINT: 966335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val);; 974103Ssaidi@eecs.umich.edu checkSoftInt(tc); 983919Shsul@eecs.umich.edu break; 993919Shsul@eecs.umich.edu case MISCREG_SOFTINT_CLR: 1006335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 1013919Shsul@eecs.umich.edu case MISCREG_SOFTINT_SET: 1026335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 1032650Ssaidi@eecs.umich.edu 1043919Shsul@eecs.umich.edu case MISCREG_TICK_CMPR: 1053919Shsul@eecs.umich.edu if (tickCompare == NULL) 1063919Shsul@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 1076335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1084103Ssaidi@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1095606Snate@binkert.org cpu->deschedule(tickCompare); 1103919Shsul@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1114103Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 1124103Ssaidi@eecs.umich.edu if (tickCompare->scheduled()) 1135606Snate@binkert.org cpu->deschedule(tickCompare); 1145606Snate@binkert.org cpu->schedule(tickCompare, curTick + time * cpu->ticks(1)); 1154103Ssaidi@eecs.umich.edu } 1163919Shsul@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 1173919Shsul@eecs.umich.edu break; 1182650Ssaidi@eecs.umich.edu 1193919Shsul@eecs.umich.edu case MISCREG_STICK_CMPR: 1203919Shsul@eecs.umich.edu if (sTickCompare == NULL) 1213919Shsul@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 1226335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1233919Shsul@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1245606Snate@binkert.org cpu->deschedule(sTickCompare); 1253919Shsul@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1265531Snate@binkert.org cpu->instCount(); 1274103Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) { 1284103Ssaidi@eecs.umich.edu if (sTickCompare->scheduled()) 1295606Snate@binkert.org cpu->deschedule(sTickCompare); 1305606Snate@binkert.org cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1)); 1314103Ssaidi@eecs.umich.edu } 1323919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1333919Shsul@eecs.umich.edu break; 1342650Ssaidi@eecs.umich.edu 1353919Shsul@eecs.umich.edu case MISCREG_PSTATE: 1366335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1373827Shsul@eecs.umich.edu 1383919Shsul@eecs.umich.edu case MISCREG_PIL: 1396335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1404103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1413919Shsul@eecs.umich.edu break; 1422650Ssaidi@eecs.umich.edu 1433919Shsul@eecs.umich.edu case MISCREG_HVER: 1443919Shsul@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 1452650Ssaidi@eecs.umich.edu 1463921Shsul@eecs.umich.edu case MISCREG_HINTP: 1476335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1484103Ssaidi@eecs.umich.edu if (hintp) 1495704Snate@binkert.org cpu->postInterrupt(IT_HINTP, 0); 1504103Ssaidi@eecs.umich.edu else 1515704Snate@binkert.org cpu->clearInterrupt(IT_HINTP, 0); 1524103Ssaidi@eecs.umich.edu break; 1533921Shsul@eecs.umich.edu 1543919Shsul@eecs.umich.edu case MISCREG_HTBA: 1553919Shsul@eecs.umich.edu // clear lower 7 bits on writes. 1566335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1573919Shsul@eecs.umich.edu break; 1582650Ssaidi@eecs.umich.edu 1593919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1603919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1616335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1624103Ssaidi@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 1635704Snate@binkert.org cpu->postInterrupt(IT_CPU_MONDO, 0); 1644103Ssaidi@eecs.umich.edu else 1655704Snate@binkert.org cpu->clearInterrupt(IT_CPU_MONDO, 0); 1664103Ssaidi@eecs.umich.edu break; 1673919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1683919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1696335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1704103Ssaidi@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 1715704Snate@binkert.org cpu->postInterrupt(IT_DEV_MONDO, 0); 1724103Ssaidi@eecs.umich.edu else 1735704Snate@binkert.org cpu->clearInterrupt(IT_DEV_MONDO, 0); 1744103Ssaidi@eecs.umich.edu break; 1753919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1763919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1776335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1784103Ssaidi@eecs.umich.edu if (res_error_head != res_error_tail) 1795704Snate@binkert.org cpu->postInterrupt(IT_RES_ERROR, 0); 1804103Ssaidi@eecs.umich.edu else 1815704Snate@binkert.org cpu->clearInterrupt(IT_RES_ERROR, 0); 1824103Ssaidi@eecs.umich.edu break; 1833919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1843919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1856335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1864103Ssaidi@eecs.umich.edu // This one doesn't have an interrupt to report to the guest OS 1873919Shsul@eecs.umich.edu break; 1883828Shsul@eecs.umich.edu 1893919Shsul@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1903919Shsul@eecs.umich.edu if (hSTickCompare == NULL) 1913919Shsul@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1926335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1933919Shsul@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1945606Snate@binkert.org cpu->deschedule(hSTickCompare); 1953919Shsul@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1965531Snate@binkert.org cpu->instCount(); 1974103Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) { 1984103Ssaidi@eecs.umich.edu if (hSTickCompare->scheduled()) 1995606Snate@binkert.org cpu->deschedule(hSTickCompare); 2005606Snate@binkert.org cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1)); 2014103Ssaidi@eecs.umich.edu } 2023919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2033919Shsul@eecs.umich.edu break; 2043817Ssaidi@eecs.umich.edu 2053919Shsul@eecs.umich.edu case MISCREG_HPSTATE: 2063919Shsul@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 2076335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val | HPSTATE::id); 2084103Ssaidi@eecs.umich.edu#if FULL_SYSTEM 2094103Ssaidi@eecs.umich.edu if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 2105704Snate@binkert.org cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2114103Ssaidi@eecs.umich.edu else 2125704Snate@binkert.org cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2134103Ssaidi@eecs.umich.edu#endif 2143919Shsul@eecs.umich.edu break; 2153919Shsul@eecs.umich.edu case MISCREG_HTSTATE: 2166335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 2174194Ssaidi@eecs.umich.edu break; 2184194Ssaidi@eecs.umich.edu 2193919Shsul@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2204194Ssaidi@eecs.umich.edu if (bits(val,2,2)) 2214194Ssaidi@eecs.umich.edu panic("No support for setting spec_en bit\n"); 2226335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, bits(val,0,0)); 2234194Ssaidi@eecs.umich.edu if (!bits(val,0,0)) { 2244216Ssaidi@eecs.umich.edu DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2254194Ssaidi@eecs.umich.edu // Time to go to sleep 2264194Ssaidi@eecs.umich.edu tc->suspend(); 2274194Ssaidi@eecs.umich.edu if (tc->getKernelStats()) 2284194Ssaidi@eecs.umich.edu tc->getKernelStats()->quiesce(); 2295531Snate@binkert.org } 2303919Shsul@eecs.umich.edu break; 2313817Ssaidi@eecs.umich.edu 2323919Shsul@eecs.umich.edu default: 2335531Snate@binkert.org panic("Invalid write to FS misc register %s\n", 2345531Snate@binkert.org getMiscRegName(miscReg)); 2352650Ssaidi@eecs.umich.edu } 2362650Ssaidi@eecs.umich.edu} 2372650Ssaidi@eecs.umich.edu 2382650Ssaidi@eecs.umich.eduMiscReg 2396335Sgblack@eecs.umich.eduISA::readFSReg(int miscReg, ThreadContext * tc) 2402650Ssaidi@eecs.umich.edu{ 2414194Ssaidi@eecs.umich.edu uint64_t temp; 2424194Ssaidi@eecs.umich.edu 2432650Ssaidi@eecs.umich.edu switch (miscReg) { 2443919Shsul@eecs.umich.edu /* Privileged registers. */ 2453825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2463825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2473825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2483825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2493825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2503825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2533825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 2543825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 2553825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 2563825Ssaidi@eecs.umich.edu case MISCREG_PIL: 2573825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 2583825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 2593825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 2603825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2616335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) ; 2622650Ssaidi@eecs.umich.edu 2633825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 2646335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); 2653825Ssaidi@eecs.umich.edu case MISCREG_HVER: 2664207Ssaidi@eecs.umich.edu // XXX set to match Legion 2674207Ssaidi@eecs.umich.edu return ULL(0x3e) << 48 | 2684207Ssaidi@eecs.umich.edu ULL(0x23) << 32 | 2694207Ssaidi@eecs.umich.edu ULL(0x20) << 24 | 2704207Ssaidi@eecs.umich.edu //MaxGL << 16 | XXX For some reason legion doesn't set GL 2714207Ssaidi@eecs.umich.edu MaxTL << 8 | 2724207Ssaidi@eecs.umich.edu (NWindows -1) << 0; 2732650Ssaidi@eecs.umich.edu 2744194Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2754194Ssaidi@eecs.umich.edu System *sys; 2764194Ssaidi@eecs.umich.edu int x; 2774194Ssaidi@eecs.umich.edu sys = tc->getSystemPtr(); 2784194Ssaidi@eecs.umich.edu 2796335Sgblack@eecs.umich.edu temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); 2805531Snate@binkert.org // Check that the CPU array is fully populated 2815531Snate@binkert.org // (by calling getNumCPus()) 2825720Snate@binkert.org assert(sys->numContexts() > tc->contextId()); 2834194Ssaidi@eecs.umich.edu 2845714Shsul@eecs.umich.edu temp |= tc->contextId() << STS::shft_id; 2854194Ssaidi@eecs.umich.edu 2865714Shsul@eecs.umich.edu for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 2874194Ssaidi@eecs.umich.edu switch (sys->threadContexts[x]->status()) { 2884194Ssaidi@eecs.umich.edu case ThreadContext::Active: 2894194Ssaidi@eecs.umich.edu temp |= STS::st_run << (STS::shft_fsm0 - 2904194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2914194Ssaidi@eecs.umich.edu break; 2924194Ssaidi@eecs.umich.edu case ThreadContext::Suspended: 2934194Ssaidi@eecs.umich.edu // should this be idle? 2944194Ssaidi@eecs.umich.edu temp |= STS::st_idle << (STS::shft_fsm0 - 2954194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2964194Ssaidi@eecs.umich.edu break; 2974194Ssaidi@eecs.umich.edu case ThreadContext::Halted: 2984194Ssaidi@eecs.umich.edu temp |= STS::st_halt << (STS::shft_fsm0 - 2994194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 3004194Ssaidi@eecs.umich.edu break; 3014194Ssaidi@eecs.umich.edu default: 3024194Ssaidi@eecs.umich.edu panic("What state are we in?!\n"); 3034194Ssaidi@eecs.umich.edu } // switch 3044194Ssaidi@eecs.umich.edu } // for 3054194Ssaidi@eecs.umich.edu 3064194Ssaidi@eecs.umich.edu return temp; 3073825Ssaidi@eecs.umich.edu default: 3083825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 3092650Ssaidi@eecs.umich.edu } 3102650Ssaidi@eecs.umich.edu} 3112650Ssaidi@eecs.umich.edu 3122651Ssaidi@eecs.umich.eduvoid 3136335Sgblack@eecs.umich.eduISA::processTickCompare(ThreadContext *tc) 3142651Ssaidi@eecs.umich.edu{ 3152651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 3162651Ssaidi@eecs.umich.edu} 3172651Ssaidi@eecs.umich.edu 3182651Ssaidi@eecs.umich.eduvoid 3196335Sgblack@eecs.umich.eduISA::processSTickCompare(ThreadContext *tc) 3202651Ssaidi@eecs.umich.edu{ 3215606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3225606Snate@binkert.org 3233888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3243888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3253888Ssaidi@eecs.umich.edu // more 3263888Ssaidi@eecs.umich.edu int ticks; 3273890Ssaidi@eecs.umich.edu ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 3285606Snate@binkert.org cpu->instCount(); 3293888Ssaidi@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 3303888Ssaidi@eecs.umich.edu 3314216Ssaidi@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3323888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 3333888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3344172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 3356335Sgblack@eecs.umich.edu setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 3363921Shsul@eecs.umich.edu } 3373888Ssaidi@eecs.umich.edu } else 3385606Snate@binkert.org cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); 3392651Ssaidi@eecs.umich.edu} 3402651Ssaidi@eecs.umich.edu 3412651Ssaidi@eecs.umich.eduvoid 3426335Sgblack@eecs.umich.eduISA::processHSTickCompare(ThreadContext *tc) 3432651Ssaidi@eecs.umich.edu{ 3445606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3455606Snate@binkert.org 3463891Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3473891Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3483891Ssaidi@eecs.umich.edu // more 3493891Ssaidi@eecs.umich.edu int ticks; 3506029Ssteve.reinhardt@amd.com if ( tc->status() == ThreadContext::Halted) 3514216Ssaidi@eecs.umich.edu return; 3524216Ssaidi@eecs.umich.edu 3533891Ssaidi@eecs.umich.edu ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 3545606Snate@binkert.org cpu->instCount(); 3553891Ssaidi@eecs.umich.edu assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 3563891Ssaidi@eecs.umich.edu 3574216Ssaidi@eecs.umich.edu if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3583891Ssaidi@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 3593891Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3604172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 3616335Sgblack@eecs.umich.edu setMiscReg(MISCREG_HINTP, 1, tc); 3623921Shsul@eecs.umich.edu } 3633891Ssaidi@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 3643891Ssaidi@eecs.umich.edu } else 3655606Snate@binkert.org cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1)); 3662651Ssaidi@eecs.umich.edu} 3672650Ssaidi@eecs.umich.edu 368