ua2005.cc revision 6029
19651SAndreas.Sandberg@ARM.com/* 29651SAndreas.Sandberg@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan 39651SAndreas.Sandberg@ARM.com * All rights reserved. 49651SAndreas.Sandberg@ARM.com * 59651SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 69651SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 79651SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 89651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 99651SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 109651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 119651SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 129651SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 139651SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 149651SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 159651SAndreas.Sandberg@ARM.com * 169651SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179651SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189651SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199651SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209651SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219651SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229651SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239651SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249651SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259651SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269651SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279651SAndreas.Sandberg@ARM.com */ 289651SAndreas.Sandberg@ARM.com 299651SAndreas.Sandberg@ARM.com#include "arch/sparc/kernel_stats.hh" 309651SAndreas.Sandberg@ARM.com#include "arch/sparc/miscregfile.hh" 319651SAndreas.Sandberg@ARM.com#include "base/bitfield.hh" 329651SAndreas.Sandberg@ARM.com#include "base/trace.hh" 339651SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 349651SAndreas.Sandberg@ARM.com#include "cpu/thread_context.hh" 359651SAndreas.Sandberg@ARM.com#include "sim/system.hh" 369651SAndreas.Sandberg@ARM.com 379651SAndreas.Sandberg@ARM.comusing namespace SparcISA; 389651SAndreas.Sandberg@ARM.comusing namespace std; 399651SAndreas.Sandberg@ARM.com 409651SAndreas.Sandberg@ARM.com 419651SAndreas.Sandberg@ARM.comvoid 429651SAndreas.Sandberg@ARM.comMiscRegFile::checkSoftInt(ThreadContext *tc) 439651SAndreas.Sandberg@ARM.com{ 449753Sandreas@sandberg.pp.se BaseCPU *cpu = tc->getCpuPtr(); 459651SAndreas.Sandberg@ARM.com 469651SAndreas.Sandberg@ARM.com // If PIL < 14, copy over the tm and sm bits 479651SAndreas.Sandberg@ARM.com if (pil < 14 && softint & 0x10000) 489651SAndreas.Sandberg@ARM.com cpu->postInterrupt(IT_SOFT_INT, 16); 499651SAndreas.Sandberg@ARM.com else 509651SAndreas.Sandberg@ARM.com cpu->clearInterrupt(IT_SOFT_INT, 16); 519651SAndreas.Sandberg@ARM.com if (pil < 14 && softint & 0x1) 529651SAndreas.Sandberg@ARM.com cpu->postInterrupt(IT_SOFT_INT, 0); 539651SAndreas.Sandberg@ARM.com else 549651SAndreas.Sandberg@ARM.com cpu->clearInterrupt(IT_SOFT_INT, 0); 559651SAndreas.Sandberg@ARM.com 569892Sandreas@sandberg.pp.se // Copy over any of the other bits that are set 579892Sandreas@sandberg.pp.se for (int bit = 15; bit > 0; --bit) { 589892Sandreas@sandberg.pp.se if (1 << bit & softint && bit > pil) 599651SAndreas.Sandberg@ARM.com cpu->postInterrupt(IT_SOFT_INT, bit); 609651SAndreas.Sandberg@ARM.com else 619651SAndreas.Sandberg@ARM.com cpu->clearInterrupt(IT_SOFT_INT, bit); 629651SAndreas.Sandberg@ARM.com } 639651SAndreas.Sandberg@ARM.com} 649651SAndreas.Sandberg@ARM.com 659651SAndreas.Sandberg@ARM.com//These functions map register indices to names 669651SAndreas.Sandberg@ARM.comstatic inline string 679651SAndreas.Sandberg@ARM.comgetMiscRegName(RegIndex index) 689651SAndreas.Sandberg@ARM.com{ 699651SAndreas.Sandberg@ARM.com static string miscRegName[NumMiscRegs] = 709651SAndreas.Sandberg@ARM.com {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 719651SAndreas.Sandberg@ARM.com "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 729651SAndreas.Sandberg@ARM.com "stick", "stick_cmpr", 739651SAndreas.Sandberg@ARM.com "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 749651SAndreas.Sandberg@ARM.com "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 759651SAndreas.Sandberg@ARM.com "wstate",*/ "gl", 769651SAndreas.Sandberg@ARM.com "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 779651SAndreas.Sandberg@ARM.com "hstick_cmpr", 789651SAndreas.Sandberg@ARM.com "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 799651SAndreas.Sandberg@ARM.com "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 809651SAndreas.Sandberg@ARM.com "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 819651SAndreas.Sandberg@ARM.com "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 829651SAndreas.Sandberg@ARM.com "nresErrorHead", "nresErrorTail", "TlbData" }; 839651SAndreas.Sandberg@ARM.com return miscRegName[index]; 849651SAndreas.Sandberg@ARM.com} 859651SAndreas.Sandberg@ARM.com 869651SAndreas.Sandberg@ARM.comvoid 879651SAndreas.Sandberg@ARM.comMiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 889651SAndreas.Sandberg@ARM.com{ 899651SAndreas.Sandberg@ARM.com BaseCPU *cpu = tc->getCpuPtr(); 909651SAndreas.Sandberg@ARM.com 919651SAndreas.Sandberg@ARM.com int64_t time; 929651SAndreas.Sandberg@ARM.com switch (miscReg) { 939651SAndreas.Sandberg@ARM.com /* Full system only ASRs */ 949651SAndreas.Sandberg@ARM.com case MISCREG_SOFTINT: 959651SAndreas.Sandberg@ARM.com setRegNoEffect(miscReg, val);; 969651SAndreas.Sandberg@ARM.com checkSoftInt(tc); 979651SAndreas.Sandberg@ARM.com break; 989651SAndreas.Sandberg@ARM.com case MISCREG_SOFTINT_CLR: 999651SAndreas.Sandberg@ARM.com return setReg(MISCREG_SOFTINT, ~val & softint, tc); 1009688Sandreas@sandberg.pp.se case MISCREG_SOFTINT_SET: 1019688Sandreas@sandberg.pp.se return setReg(MISCREG_SOFTINT, val | softint, tc); 1029651SAndreas.Sandberg@ARM.com 1039651SAndreas.Sandberg@ARM.com case MISCREG_TICK_CMPR: 1049651SAndreas.Sandberg@ARM.com if (tickCompare == NULL) 1059651SAndreas.Sandberg@ARM.com tickCompare = new TickCompareEvent(this, tc); 1069651SAndreas.Sandberg@ARM.com setRegNoEffect(miscReg, val); 1079651SAndreas.Sandberg@ARM.com if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1089651SAndreas.Sandberg@ARM.com cpu->deschedule(tickCompare); 1099652SAndreas.Sandberg@ARM.com time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1109652SAndreas.Sandberg@ARM.com if (!(tick_cmpr & ~mask(63)) && time > 0) { 1119651SAndreas.Sandberg@ARM.com if (tickCompare->scheduled()) 1129651SAndreas.Sandberg@ARM.com cpu->deschedule(tickCompare); 1139651SAndreas.Sandberg@ARM.com cpu->schedule(tickCompare, curTick + time * cpu->ticks(1)); 1149651SAndreas.Sandberg@ARM.com } 1159651SAndreas.Sandberg@ARM.com panic("writing to TICK compare register %#X\n", val); 1169651SAndreas.Sandberg@ARM.com break; 1179652SAndreas.Sandberg@ARM.com 1189652SAndreas.Sandberg@ARM.com case MISCREG_STICK_CMPR: 1199652SAndreas.Sandberg@ARM.com if (sTickCompare == NULL) 1209652SAndreas.Sandberg@ARM.com sTickCompare = new STickCompareEvent(this, tc); 1219652SAndreas.Sandberg@ARM.com setRegNoEffect(miscReg, val); 1229652SAndreas.Sandberg@ARM.com if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1239652SAndreas.Sandberg@ARM.com cpu->deschedule(sTickCompare); 1249652SAndreas.Sandberg@ARM.com time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1259652SAndreas.Sandberg@ARM.com cpu->instCount(); 1269652SAndreas.Sandberg@ARM.com if (!(stick_cmpr & ~mask(63)) && time > 0) { 1279652SAndreas.Sandberg@ARM.com if (sTickCompare->scheduled()) 1289652SAndreas.Sandberg@ARM.com cpu->deschedule(sTickCompare); 1299652SAndreas.Sandberg@ARM.com cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1)); 1309651SAndreas.Sandberg@ARM.com } 1319651SAndreas.Sandberg@ARM.com DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1329651SAndreas.Sandberg@ARM.com break; 1339651SAndreas.Sandberg@ARM.com 1349651SAndreas.Sandberg@ARM.com case MISCREG_PSTATE: 1359651SAndreas.Sandberg@ARM.com setRegNoEffect(miscReg, val); 1369651SAndreas.Sandberg@ARM.com 1379651SAndreas.Sandberg@ARM.com case MISCREG_PIL: 1389651SAndreas.Sandberg@ARM.com setRegNoEffect(miscReg, val); 1399651SAndreas.Sandberg@ARM.com checkSoftInt(tc); 1409753Sandreas@sandberg.pp.se break; 1419753Sandreas@sandberg.pp.se 1429753Sandreas@sandberg.pp.se case MISCREG_HVER: 1439753Sandreas@sandberg.pp.se panic("Shouldn't be writing HVER\n"); 1449753Sandreas@sandberg.pp.se 1459753Sandreas@sandberg.pp.se case MISCREG_HINTP: 1469753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 1479753Sandreas@sandberg.pp.se if (hintp) 1489753Sandreas@sandberg.pp.se cpu->postInterrupt(IT_HINTP, 0); 1499753Sandreas@sandberg.pp.se else 1509753Sandreas@sandberg.pp.se cpu->clearInterrupt(IT_HINTP, 0); 1519753Sandreas@sandberg.pp.se break; 1529753Sandreas@sandberg.pp.se 1539753Sandreas@sandberg.pp.se case MISCREG_HTBA: 1549753Sandreas@sandberg.pp.se // clear lower 7 bits on writes. 1559753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1569753Sandreas@sandberg.pp.se break; 1579753Sandreas@sandberg.pp.se 1589753Sandreas@sandberg.pp.se case MISCREG_QUEUE_CPU_MONDO_HEAD: 1599753Sandreas@sandberg.pp.se case MISCREG_QUEUE_CPU_MONDO_TAIL: 1609753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 1619753Sandreas@sandberg.pp.se if (cpu_mondo_head != cpu_mondo_tail) 1629651SAndreas.Sandberg@ARM.com cpu->postInterrupt(IT_CPU_MONDO, 0); 1639753Sandreas@sandberg.pp.se else 1649753Sandreas@sandberg.pp.se cpu->clearInterrupt(IT_CPU_MONDO, 0); 1659753Sandreas@sandberg.pp.se break; 1669753Sandreas@sandberg.pp.se case MISCREG_QUEUE_DEV_MONDO_HEAD: 1679753Sandreas@sandberg.pp.se case MISCREG_QUEUE_DEV_MONDO_TAIL: 1689753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 1699753Sandreas@sandberg.pp.se if (dev_mondo_head != dev_mondo_tail) 1709753Sandreas@sandberg.pp.se cpu->postInterrupt(IT_DEV_MONDO, 0); 1719753Sandreas@sandberg.pp.se else 1729651SAndreas.Sandberg@ARM.com cpu->clearInterrupt(IT_DEV_MONDO, 0); 1739753Sandreas@sandberg.pp.se break; 1749753Sandreas@sandberg.pp.se case MISCREG_QUEUE_RES_ERROR_HEAD: 1759753Sandreas@sandberg.pp.se case MISCREG_QUEUE_RES_ERROR_TAIL: 1769753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 1779753Sandreas@sandberg.pp.se if (res_error_head != res_error_tail) 1789651SAndreas.Sandberg@ARM.com cpu->postInterrupt(IT_RES_ERROR, 0); 1799753Sandreas@sandberg.pp.se else 1809753Sandreas@sandberg.pp.se cpu->clearInterrupt(IT_RES_ERROR, 0); 1819753Sandreas@sandberg.pp.se break; 1829753Sandreas@sandberg.pp.se case MISCREG_QUEUE_NRES_ERROR_HEAD: 1839753Sandreas@sandberg.pp.se case MISCREG_QUEUE_NRES_ERROR_TAIL: 1849753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 1859753Sandreas@sandberg.pp.se // This one doesn't have an interrupt to report to the guest OS 1869753Sandreas@sandberg.pp.se break; 1879753Sandreas@sandberg.pp.se 1889753Sandreas@sandberg.pp.se case MISCREG_HSTICK_CMPR: 1899753Sandreas@sandberg.pp.se if (hSTickCompare == NULL) 1909753Sandreas@sandberg.pp.se hSTickCompare = new HSTickCompareEvent(this, tc); 1919753Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 1929753Sandreas@sandberg.pp.se if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1939753Sandreas@sandberg.pp.se cpu->deschedule(hSTickCompare); 1949753Sandreas@sandberg.pp.se time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1959753Sandreas@sandberg.pp.se cpu->instCount(); 1969753Sandreas@sandberg.pp.se if (!(hstick_cmpr & ~mask(63)) && time > 0) { 1979753Sandreas@sandberg.pp.se if (hSTickCompare->scheduled()) 1989753Sandreas@sandberg.pp.se cpu->deschedule(hSTickCompare); 1999753Sandreas@sandberg.pp.se cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1)); 2009753Sandreas@sandberg.pp.se } 2019651SAndreas.Sandberg@ARM.com DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2029651SAndreas.Sandberg@ARM.com break; 2039651SAndreas.Sandberg@ARM.com 2049651SAndreas.Sandberg@ARM.com case MISCREG_HPSTATE: 2059651SAndreas.Sandberg@ARM.com // T1000 spec says impl. dependent val must always be 1 2069651SAndreas.Sandberg@ARM.com setRegNoEffect(miscReg, val | HPSTATE::id); 2079651SAndreas.Sandberg@ARM.com#if FULL_SYSTEM 2089651SAndreas.Sandberg@ARM.com if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 2099651SAndreas.Sandberg@ARM.com cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2109753Sandreas@sandberg.pp.se else 2119651SAndreas.Sandberg@ARM.com cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2129651SAndreas.Sandberg@ARM.com#endif 2139735Sandreas@sandberg.pp.se break; 2149735Sandreas@sandberg.pp.se case MISCREG_HTSTATE: 2159735Sandreas@sandberg.pp.se setRegNoEffect(miscReg, val); 2169735Sandreas@sandberg.pp.se break; 2179735Sandreas@sandberg.pp.se 2189735Sandreas@sandberg.pp.se case MISCREG_STRAND_STS_REG: 2199735Sandreas@sandberg.pp.se if (bits(val,2,2)) 2209735Sandreas@sandberg.pp.se panic("No support for setting spec_en bit\n"); 2219735Sandreas@sandberg.pp.se setRegNoEffect(miscReg, bits(val,0,0)); 2229735Sandreas@sandberg.pp.se if (!bits(val,0,0)) { 2239735Sandreas@sandberg.pp.se DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2249735Sandreas@sandberg.pp.se // Time to go to sleep 2259735Sandreas@sandberg.pp.se tc->suspend(); 2269735Sandreas@sandberg.pp.se if (tc->getKernelStats()) 2279735Sandreas@sandberg.pp.se tc->getKernelStats()->quiesce(); 2289651SAndreas.Sandberg@ARM.com } 2299651SAndreas.Sandberg@ARM.com break; 2309651SAndreas.Sandberg@ARM.com 2319651SAndreas.Sandberg@ARM.com default: 2329651SAndreas.Sandberg@ARM.com panic("Invalid write to FS misc register %s\n", 2339651SAndreas.Sandberg@ARM.com getMiscRegName(miscReg)); 2349651SAndreas.Sandberg@ARM.com } 2359651SAndreas.Sandberg@ARM.com} 2369753Sandreas@sandberg.pp.se 2379753Sandreas@sandberg.pp.seMiscReg 2389753Sandreas@sandberg.pp.seMiscRegFile::readFSReg(int miscReg, ThreadContext * tc) 2399753Sandreas@sandberg.pp.se{ 2409753Sandreas@sandberg.pp.se uint64_t temp; 2419753Sandreas@sandberg.pp.se 2429753Sandreas@sandberg.pp.se switch (miscReg) { 2439753Sandreas@sandberg.pp.se /* Privileged registers. */ 24410112Sandreas@sandberg.pp.se case MISCREG_QUEUE_CPU_MONDO_HEAD: 24510112Sandreas@sandberg.pp.se case MISCREG_QUEUE_CPU_MONDO_TAIL: 24610112Sandreas@sandberg.pp.se case MISCREG_QUEUE_DEV_MONDO_HEAD: 24710112Sandreas@sandberg.pp.se case MISCREG_QUEUE_DEV_MONDO_TAIL: 24810112Sandreas@sandberg.pp.se case MISCREG_QUEUE_RES_ERROR_HEAD: 2499753Sandreas@sandberg.pp.se case MISCREG_QUEUE_RES_ERROR_TAIL: 2509753Sandreas@sandberg.pp.se case MISCREG_QUEUE_NRES_ERROR_HEAD: 2519651SAndreas.Sandberg@ARM.com case MISCREG_QUEUE_NRES_ERROR_TAIL: 2529651SAndreas.Sandberg@ARM.com case MISCREG_SOFTINT: 2539753Sandreas@sandberg.pp.se case MISCREG_TICK_CMPR: 2549753Sandreas@sandberg.pp.se case MISCREG_STICK_CMPR: 2559753Sandreas@sandberg.pp.se case MISCREG_PIL: 2569753Sandreas@sandberg.pp.se case MISCREG_HPSTATE: 2579753Sandreas@sandberg.pp.se case MISCREG_HINTP: 2589753Sandreas@sandberg.pp.se case MISCREG_HTSTATE: 2599753Sandreas@sandberg.pp.se case MISCREG_HSTICK_CMPR: 2609753Sandreas@sandberg.pp.se return readRegNoEffect(miscReg) ; 2619753Sandreas@sandberg.pp.se 2629753Sandreas@sandberg.pp.se case MISCREG_HTBA: 2639753Sandreas@sandberg.pp.se return readRegNoEffect(miscReg) & ULL(~0x7FFF); 2649753Sandreas@sandberg.pp.se case MISCREG_HVER: 2659753Sandreas@sandberg.pp.se // XXX set to match Legion 2669753Sandreas@sandberg.pp.se return ULL(0x3e) << 48 | 2679651SAndreas.Sandberg@ARM.com ULL(0x23) << 32 | 2689651SAndreas.Sandberg@ARM.com ULL(0x20) << 24 | 2699651SAndreas.Sandberg@ARM.com //MaxGL << 16 | XXX For some reason legion doesn't set GL 2709651SAndreas.Sandberg@ARM.com MaxTL << 8 | 2719651SAndreas.Sandberg@ARM.com (NWindows -1) << 0; 2729651SAndreas.Sandberg@ARM.com 2739651SAndreas.Sandberg@ARM.com case MISCREG_STRAND_STS_REG: 2749651SAndreas.Sandberg@ARM.com System *sys; 2759651SAndreas.Sandberg@ARM.com int x; 2769651SAndreas.Sandberg@ARM.com sys = tc->getSystemPtr(); 2779651SAndreas.Sandberg@ARM.com 2789651SAndreas.Sandberg@ARM.com temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); 2799651SAndreas.Sandberg@ARM.com // Check that the CPU array is fully populated 2809651SAndreas.Sandberg@ARM.com // (by calling getNumCPus()) 2819651SAndreas.Sandberg@ARM.com assert(sys->numContexts() > tc->contextId()); 2829651SAndreas.Sandberg@ARM.com 2839651SAndreas.Sandberg@ARM.com temp |= tc->contextId() << STS::shft_id; 2849651SAndreas.Sandberg@ARM.com 2859651SAndreas.Sandberg@ARM.com for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 2869651SAndreas.Sandberg@ARM.com switch (sys->threadContexts[x]->status()) { 2879651SAndreas.Sandberg@ARM.com case ThreadContext::Active: 2889651SAndreas.Sandberg@ARM.com temp |= STS::st_run << (STS::shft_fsm0 - 2899651SAndreas.Sandberg@ARM.com ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2909651SAndreas.Sandberg@ARM.com break; 2919651SAndreas.Sandberg@ARM.com case ThreadContext::Suspended: 2929651SAndreas.Sandberg@ARM.com // should this be idle? 2939651SAndreas.Sandberg@ARM.com temp |= STS::st_idle << (STS::shft_fsm0 - 2949651SAndreas.Sandberg@ARM.com ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2959651SAndreas.Sandberg@ARM.com break; 2969651SAndreas.Sandberg@ARM.com case ThreadContext::Halted: 2979651SAndreas.Sandberg@ARM.com temp |= STS::st_halt << (STS::shft_fsm0 - 2989651SAndreas.Sandberg@ARM.com ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2999651SAndreas.Sandberg@ARM.com break; 3009651SAndreas.Sandberg@ARM.com default: 3019651SAndreas.Sandberg@ARM.com panic("What state are we in?!\n"); 3029651SAndreas.Sandberg@ARM.com } // switch 3039651SAndreas.Sandberg@ARM.com } // for 3049651SAndreas.Sandberg@ARM.com 3059651SAndreas.Sandberg@ARM.com return temp; 3069651SAndreas.Sandberg@ARM.com default: 3079651SAndreas.Sandberg@ARM.com panic("Invalid read to FS misc register\n"); 3089651SAndreas.Sandberg@ARM.com } 3099651SAndreas.Sandberg@ARM.com} 3109651SAndreas.Sandberg@ARM.com 3119651SAndreas.Sandberg@ARM.comvoid 3129651SAndreas.Sandberg@ARM.comMiscRegFile::processTickCompare(ThreadContext *tc) 3139651SAndreas.Sandberg@ARM.com{ 3149651SAndreas.Sandberg@ARM.com panic("tick compare not implemented\n"); 3159651SAndreas.Sandberg@ARM.com} 3169651SAndreas.Sandberg@ARM.com 3179651SAndreas.Sandberg@ARM.comvoid 3189651SAndreas.Sandberg@ARM.comMiscRegFile::processSTickCompare(ThreadContext *tc) 3199651SAndreas.Sandberg@ARM.com{ 3209651SAndreas.Sandberg@ARM.com BaseCPU *cpu = tc->getCpuPtr(); 3219651SAndreas.Sandberg@ARM.com 3229651SAndreas.Sandberg@ARM.com // since our microcode instructions take two cycles we need to check if 3239651SAndreas.Sandberg@ARM.com // we're actually at the correct cycle or we need to wait a little while 3249651SAndreas.Sandberg@ARM.com // more 3259651SAndreas.Sandberg@ARM.com int ticks; 3269651SAndreas.Sandberg@ARM.com ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 3279651SAndreas.Sandberg@ARM.com cpu->instCount(); 3289651SAndreas.Sandberg@ARM.com assert(ticks >= 0 && "stick compare missed interrupt cycle"); 3299651SAndreas.Sandberg@ARM.com 3309651SAndreas.Sandberg@ARM.com if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3319651SAndreas.Sandberg@ARM.com DPRINTF(Timer, "STick compare cycle reached at %#x\n", 3329651SAndreas.Sandberg@ARM.com (stick_cmpr & mask(63))); 3339651SAndreas.Sandberg@ARM.com if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 3349651SAndreas.Sandberg@ARM.com setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 3359651SAndreas.Sandberg@ARM.com } 3369651SAndreas.Sandberg@ARM.com } else 3379651SAndreas.Sandberg@ARM.com cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); 3389651SAndreas.Sandberg@ARM.com} 3399651SAndreas.Sandberg@ARM.com 3409651SAndreas.Sandberg@ARM.comvoid 3419651SAndreas.Sandberg@ARM.comMiscRegFile::processHSTickCompare(ThreadContext *tc) 3429651SAndreas.Sandberg@ARM.com{ 3439651SAndreas.Sandberg@ARM.com BaseCPU *cpu = tc->getCpuPtr(); 3449651SAndreas.Sandberg@ARM.com 3459651SAndreas.Sandberg@ARM.com // since our microcode instructions take two cycles we need to check if 3469651SAndreas.Sandberg@ARM.com // we're actually at the correct cycle or we need to wait a little while 3479651SAndreas.Sandberg@ARM.com // more 3489651SAndreas.Sandberg@ARM.com int ticks; 3499651SAndreas.Sandberg@ARM.com if ( tc->status() == ThreadContext::Halted) 3509651SAndreas.Sandberg@ARM.com return; 3519651SAndreas.Sandberg@ARM.com 3529651SAndreas.Sandberg@ARM.com ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 3539651SAndreas.Sandberg@ARM.com cpu->instCount(); 3549651SAndreas.Sandberg@ARM.com assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 3559651SAndreas.Sandberg@ARM.com 3569651SAndreas.Sandberg@ARM.com if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 3579651SAndreas.Sandberg@ARM.com DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 3589651SAndreas.Sandberg@ARM.com (stick_cmpr & mask(63))); 3599651SAndreas.Sandberg@ARM.com if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 3609651SAndreas.Sandberg@ARM.com setReg(MISCREG_HINTP, 1, tc); 3619651SAndreas.Sandberg@ARM.com } 3629651SAndreas.Sandberg@ARM.com // Need to do something to cause interrupt to happen here !!! @todo 3639651SAndreas.Sandberg@ARM.com } else 3649651SAndreas.Sandberg@ARM.com cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1)); 3659651SAndreas.Sandberg@ARM.com} 3669651SAndreas.Sandberg@ARM.com 3679651SAndreas.Sandberg@ARM.com