ua2005.cc revision 5946
12914Ssaidi@eecs.umich.edu/* 28856Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142914Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152914Ssaidi@eecs.umich.edu * 162914Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172914Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182914Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192914Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212914Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222914Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232914Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242914Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252914Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262914Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272914Ssaidi@eecs.umich.edu */ 282914Ssaidi@eecs.umich.edu 292914Ssaidi@eecs.umich.edu#include "arch/sparc/kernel_stats.hh" 302914Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 312914Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 322914Ssaidi@eecs.umich.edu#include "base/trace.hh" 332914Ssaidi@eecs.umich.edu#include "cpu/base.hh" 342914Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 352914Ssaidi@eecs.umich.edu#include "sim/system.hh" 362914Ssaidi@eecs.umich.edu 372914Ssaidi@eecs.umich.eduusing namespace SparcISA; 382914Ssaidi@eecs.umich.eduusing namespace std; 392914Ssaidi@eecs.umich.edu 402914Ssaidi@eecs.umich.edu 418856Sandreas.hansson@arm.comvoid 422914Ssaidi@eecs.umich.eduMiscRegFile::checkSoftInt(ThreadContext *tc) 432914Ssaidi@eecs.umich.edu{ 448232Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 458708Sandreas.hansson@arm.com 462914Ssaidi@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 472914Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x10000) 485740Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, 16); 495740Snate@binkert.org else 508856Sandreas.hansson@arm.com cpu->clearInterrupt(IT_SOFT_INT, 16); 518856Sandreas.hansson@arm.com if (pil < 14 && softint & 0x1) 528856Sandreas.hansson@arm.com cpu->postInterrupt(IT_SOFT_INT, 0); 535740Snate@binkert.org else 545740Snate@binkert.org cpu->clearInterrupt(IT_SOFT_INT, 0); 555740Snate@binkert.org 565740Snate@binkert.org // Copy over any of the other bits that are set 575740Snate@binkert.org for (int bit = 15; bit > 0; --bit) { 585740Snate@binkert.org if (1 << bit & softint && bit > pil) 595740Snate@binkert.org cpu->postInterrupt(IT_SOFT_INT, bit); 605740Snate@binkert.org else 614929Sstever@gmail.com cpu->clearInterrupt(IT_SOFT_INT, bit); 624490Sstever@eecs.umich.edu } 633091Sstever@eecs.umich.edu} 648856Sandreas.hansson@arm.com 658856Sandreas.hansson@arm.com//These functions map register indices to names 664490Sstever@eecs.umich.edustatic inline string 674490Sstever@eecs.umich.edugetMiscRegName(RegIndex index) 688856Sandreas.hansson@arm.com{ 693296Ssaidi@eecs.umich.edu static string miscRegName[NumMiscRegs] = 708856Sandreas.hansson@arm.com {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 718856Sandreas.hansson@arm.com "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 728856Sandreas.hansson@arm.com "stick", "stick_cmpr", 738856Sandreas.hansson@arm.com "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 748856Sandreas.hansson@arm.com "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 753284Srdreslin@umich.edu "wstate",*/ "gl", 764929Sstever@gmail.com "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 778856Sandreas.hansson@arm.com "hstick_cmpr", 788856Sandreas.hansson@arm.com "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 798856Sandreas.hansson@arm.com "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 804490Sstever@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 813342Srdreslin@umich.edu "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 824490Sstever@eecs.umich.edu "nresErrorHead", "nresErrorTail", "TlbData" }; 834490Sstever@eecs.umich.edu return miscRegName[index]; 844490Sstever@eecs.umich.edu} 854929Sstever@gmail.com 864929Sstever@gmail.comvoid 873296Ssaidi@eecs.umich.eduMiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 884929Sstever@gmail.com{ 893091Sstever@eecs.umich.edu BaseCPU *cpu = tc->getCpuPtr(); 903091Sstever@eecs.umich.edu 913091Sstever@eecs.umich.edu int64_t time; 923349Sbinkertn@umich.edu switch (miscReg) { 933091Sstever@eecs.umich.edu /* Full system only ASRs */ 943091Sstever@eecs.umich.edu case MISCREG_SOFTINT: 953091Sstever@eecs.umich.edu setRegNoEffect(miscReg, val);; 963091Sstever@eecs.umich.edu checkSoftInt(tc); 973091Sstever@eecs.umich.edu break; 983091Sstever@eecs.umich.edu case MISCREG_SOFTINT_CLR: 994670Sstever@eecs.umich.edu return setReg(MISCREG_SOFTINT, ~val & softint, tc); 1004670Sstever@eecs.umich.edu case MISCREG_SOFTINT_SET: 1014670Sstever@eecs.umich.edu return setReg(MISCREG_SOFTINT, val | softint, tc); 1024670Sstever@eecs.umich.edu 1034670Sstever@eecs.umich.edu case MISCREG_TICK_CMPR: 1044670Sstever@eecs.umich.edu if (tickCompare == NULL) 1054670Sstever@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 1064670Sstever@eecs.umich.edu setRegNoEffect(miscReg, val); 1074626Sstever@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1083091Sstever@eecs.umich.edu cpu->deschedule(tickCompare); 1093175Srdreslin@umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1104626Sstever@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 1114670Sstever@eecs.umich.edu if (tickCompare->scheduled()) 1124670Sstever@eecs.umich.edu cpu->deschedule(tickCompare); 1134626Sstever@eecs.umich.edu cpu->schedule(tickCompare, curTick + time * cpu->ticks(1)); 1147823Ssteve.reinhardt@amd.com } 1154626Sstever@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 1164490Sstever@eecs.umich.edu break; 1173309Srdreslin@umich.edu 1184670Sstever@eecs.umich.edu case MISCREG_STICK_CMPR: 1193091Sstever@eecs.umich.edu if (sTickCompare == NULL) 1203091Sstever@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 1213091Sstever@eecs.umich.edu setRegNoEffect(miscReg, val); 1228708Sandreas.hansson@arm.com if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1238708Sandreas.hansson@arm.com cpu->deschedule(sTickCompare); 1248708Sandreas.hansson@arm.com time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1258856Sandreas.hansson@arm.com cpu->instCount(); 1268856Sandreas.hansson@arm.com if (!(stick_cmpr & ~mask(63)) && time > 0) { 1278708Sandreas.hansson@arm.com if (sTickCompare->scheduled()) 1288856Sandreas.hansson@arm.com cpu->deschedule(sTickCompare); 1298708Sandreas.hansson@arm.com cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1)); 1308708Sandreas.hansson@arm.com } 1318708Sandreas.hansson@arm.com DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1328856Sandreas.hansson@arm.com break; 1338856Sandreas.hansson@arm.com 1348856Sandreas.hansson@arm.com case MISCREG_PSTATE: 1358856Sandreas.hansson@arm.com setRegNoEffect(miscReg, val); 1368708Sandreas.hansson@arm.com 1378708Sandreas.hansson@arm.com case MISCREG_PIL: 1382914Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1392914Ssaidi@eecs.umich.edu checkSoftInt(tc); 1404492Sstever@eecs.umich.edu break; 1413403Ssaidi@eecs.umich.edu 1427823Ssteve.reinhardt@amd.com case MISCREG_HVER: 1437823Ssteve.reinhardt@amd.com panic("Shouldn't be writing HVER\n"); 1444492Sstever@eecs.umich.edu 1453450Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1464666Sstever@eecs.umich.edu setRegNoEffect(miscReg, val); 1474666Sstever@eecs.umich.edu if (hintp) 1484666Sstever@eecs.umich.edu cpu->postInterrupt(IT_HINTP, 0); 1494666Sstever@eecs.umich.edu else 1504666Sstever@eecs.umich.edu cpu->clearInterrupt(IT_HINTP, 0); 1514666Sstever@eecs.umich.edu break; 1524666Sstever@eecs.umich.edu 1534666Sstever@eecs.umich.edu case MISCREG_HTBA: 1544492Sstever@eecs.umich.edu // clear lower 7 bits on writes. 1553450Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1563403Ssaidi@eecs.umich.edu break; 1573450Ssaidi@eecs.umich.edu 1584666Sstever@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1594490Sstever@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1604666Sstever@eecs.umich.edu setRegNoEffect(miscReg, val); 1614490Sstever@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 1623450Ssaidi@eecs.umich.edu cpu->postInterrupt(IT_CPU_MONDO, 0); 1634492Sstever@eecs.umich.edu else 1644492Sstever@eecs.umich.edu cpu->clearInterrupt(IT_CPU_MONDO, 0); 1654492Sstever@eecs.umich.edu break; 1664492Sstever@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1673610Srdreslin@umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1683450Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1694492Sstever@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 1703403Ssaidi@eecs.umich.edu cpu->postInterrupt(IT_DEV_MONDO, 0); 1713403Ssaidi@eecs.umich.edu else 1728856Sandreas.hansson@arm.com cpu->clearInterrupt(IT_DEV_MONDO, 0); 1738856Sandreas.hansson@arm.com break; 1748856Sandreas.hansson@arm.com case MISCREG_QUEUE_RES_ERROR_HEAD: 1758856Sandreas.hansson@arm.com case MISCREG_QUEUE_RES_ERROR_TAIL: 1768856Sandreas.hansson@arm.com setRegNoEffect(miscReg, val); 1778856Sandreas.hansson@arm.com if (res_error_head != res_error_tail) 1788856Sandreas.hansson@arm.com cpu->postInterrupt(IT_RES_ERROR, 0); 1798856Sandreas.hansson@arm.com else 1808856Sandreas.hansson@arm.com cpu->clearInterrupt(IT_RES_ERROR, 0); 1818856Sandreas.hansson@arm.com break; 1828856Sandreas.hansson@arm.com case MISCREG_QUEUE_NRES_ERROR_HEAD: 1838856Sandreas.hansson@arm.com case MISCREG_QUEUE_NRES_ERROR_TAIL: 1848856Sandreas.hansson@arm.com setRegNoEffect(miscReg, val); 1858856Sandreas.hansson@arm.com // This one doesn't have an interrupt to report to the guest OS 1868856Sandreas.hansson@arm.com break; 1878856Sandreas.hansson@arm.com 1888856Sandreas.hansson@arm.com case MISCREG_HSTICK_CMPR: 1898856Sandreas.hansson@arm.com if (hSTickCompare == NULL) 1908856Sandreas.hansson@arm.com hSTickCompare = new HSTickCompareEvent(this, tc); 1918856Sandreas.hansson@arm.com setRegNoEffect(miscReg, val); 1928856Sandreas.hansson@arm.com if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1938856Sandreas.hansson@arm.com cpu->deschedule(hSTickCompare); 1948856Sandreas.hansson@arm.com time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1958856Sandreas.hansson@arm.com cpu->instCount(); 1968856Sandreas.hansson@arm.com if (!(hstick_cmpr & ~mask(63)) && time > 0) { 1978856Sandreas.hansson@arm.com if (hSTickCompare->scheduled()) 1988856Sandreas.hansson@arm.com cpu->deschedule(hSTickCompare); 1998856Sandreas.hansson@arm.com cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1)); 2008856Sandreas.hansson@arm.com } 2018856Sandreas.hansson@arm.com DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2028856Sandreas.hansson@arm.com break; 2038856Sandreas.hansson@arm.com 2048856Sandreas.hansson@arm.com case MISCREG_HPSTATE: 2058856Sandreas.hansson@arm.com // T1000 spec says impl. dependent val must always be 1 2068856Sandreas.hansson@arm.com setRegNoEffect(miscReg, val | HPSTATE::id); 2078856Sandreas.hansson@arm.com#if FULL_SYSTEM 2088856Sandreas.hansson@arm.com if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 2098856Sandreas.hansson@arm.com cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2104492Sstever@eecs.umich.edu else 2113403Ssaidi@eecs.umich.edu cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 2124492Sstever@eecs.umich.edu#endif 2132914Ssaidi@eecs.umich.edu break; 2148856Sandreas.hansson@arm.com case MISCREG_HTSTATE: 2158856Sandreas.hansson@arm.com setRegNoEffect(miscReg, val); 2164492Sstever@eecs.umich.edu break; 2178856Sandreas.hansson@arm.com 2188856Sandreas.hansson@arm.com case MISCREG_STRAND_STS_REG: 2198856Sandreas.hansson@arm.com if (bits(val,2,2)) 2208856Sandreas.hansson@arm.com panic("No support for setting spec_en bit\n"); 2214492Sstever@eecs.umich.edu setRegNoEffect(miscReg, bits(val,0,0)); 2224492Sstever@eecs.umich.edu if (!bits(val,0,0)) { 2234492Sstever@eecs.umich.edu DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2244492Sstever@eecs.umich.edu // Time to go to sleep 2254492Sstever@eecs.umich.edu tc->suspend(); 2264492Sstever@eecs.umich.edu if (tc->getKernelStats()) 2274492Sstever@eecs.umich.edu tc->getKernelStats()->quiesce(); 2284492Sstever@eecs.umich.edu } 2298856Sandreas.hansson@arm.com break; 2308856Sandreas.hansson@arm.com 2318856Sandreas.hansson@arm.com default: 2324492Sstever@eecs.umich.edu panic("Invalid write to FS misc register %s\n", 2334492Sstever@eecs.umich.edu getMiscRegName(miscReg)); 2344492Sstever@eecs.umich.edu } 2354492Sstever@eecs.umich.edu} 2364492Sstever@eecs.umich.edu 2374492Sstever@eecs.umich.eduMiscReg 2384492Sstever@eecs.umich.eduMiscRegFile::readFSReg(int miscReg, ThreadContext * tc) 2394492Sstever@eecs.umich.edu{ 2404492Sstever@eecs.umich.edu uint64_t temp; 2414492Sstever@eecs.umich.edu 2422914Ssaidi@eecs.umich.edu switch (miscReg) { 2432914Ssaidi@eecs.umich.edu /* Privileged registers. */ 2442914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2452914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2462914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2472914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2488856Sandreas.hansson@arm.com case MISCREG_QUEUE_RES_ERROR_HEAD: 2492914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2502914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2512914Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2522914Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 253 case MISCREG_TICK_CMPR: 254 case MISCREG_STICK_CMPR: 255 case MISCREG_PIL: 256 case MISCREG_HPSTATE: 257 case MISCREG_HINTP: 258 case MISCREG_HTSTATE: 259 case MISCREG_HSTICK_CMPR: 260 return readRegNoEffect(miscReg) ; 261 262 case MISCREG_HTBA: 263 return readRegNoEffect(miscReg) & ULL(~0x7FFF); 264 case MISCREG_HVER: 265 // XXX set to match Legion 266 return ULL(0x3e) << 48 | 267 ULL(0x23) << 32 | 268 ULL(0x20) << 24 | 269 //MaxGL << 16 | XXX For some reason legion doesn't set GL 270 MaxTL << 8 | 271 (NWindows -1) << 0; 272 273 case MISCREG_STRAND_STS_REG: 274 System *sys; 275 int x; 276 sys = tc->getSystemPtr(); 277 278 temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); 279 // Check that the CPU array is fully populated 280 // (by calling getNumCPus()) 281 assert(sys->numContexts() > tc->contextId()); 282 283 temp |= tc->contextId() << STS::shft_id; 284 285 for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 286 switch (sys->threadContexts[x]->status()) { 287 case ThreadContext::Active: 288 temp |= STS::st_run << (STS::shft_fsm0 - 289 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 290 break; 291 case ThreadContext::Suspended: 292 // should this be idle? 293 temp |= STS::st_idle << (STS::shft_fsm0 - 294 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 295 break; 296 case ThreadContext::Halted: 297 temp |= STS::st_halt << (STS::shft_fsm0 - 298 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 299 break; 300 default: 301 panic("What state are we in?!\n"); 302 } // switch 303 } // for 304 305 return temp; 306 default: 307 panic("Invalid read to FS misc register\n"); 308 } 309} 310 311void 312MiscRegFile::processTickCompare(ThreadContext *tc) 313{ 314 panic("tick compare not implemented\n"); 315} 316 317void 318MiscRegFile::processSTickCompare(ThreadContext *tc) 319{ 320 BaseCPU *cpu = tc->getCpuPtr(); 321 322 // since our microcode instructions take two cycles we need to check if 323 // we're actually at the correct cycle or we need to wait a little while 324 // more 325 int ticks; 326 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 327 cpu->instCount(); 328 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 329 330 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 331 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 332 (stick_cmpr & mask(63))); 333 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 334 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 335 } 336 } else 337 cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); 338} 339 340void 341MiscRegFile::processHSTickCompare(ThreadContext *tc) 342{ 343 BaseCPU *cpu = tc->getCpuPtr(); 344 345 // since our microcode instructions take two cycles we need to check if 346 // we're actually at the correct cycle or we need to wait a little while 347 // more 348 int ticks; 349 if ( tc->status() == ThreadContext::Halted || 350 tc->status() == ThreadContext::Unallocated) 351 return; 352 353 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 354 cpu->instCount(); 355 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 356 357 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 358 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 359 (stick_cmpr & mask(63))); 360 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 361 setReg(MISCREG_HINTP, 1, tc); 362 } 363 // Need to do something to cause interrupt to happen here !!! @todo 364 } else 365 cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1)); 366} 367 368