ua2005.cc revision 4185
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu */ 282650Ssaidi@eecs.umich.edu 293817Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 303817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 313817Ssaidi@eecs.umich.edu#include "base/trace.hh" 323817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 333817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 342650Ssaidi@eecs.umich.edu 353817Ssaidi@eecs.umich.eduusing namespace SparcISA; 363817Ssaidi@eecs.umich.edu 374103Ssaidi@eecs.umich.edu 384103Ssaidi@eecs.umich.eduvoid 394103Ssaidi@eecs.umich.eduMiscRegFile::checkSoftInt(ThreadContext *tc) 404103Ssaidi@eecs.umich.edu{ 414103Ssaidi@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 424103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x10000) 434103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,16); 444103Ssaidi@eecs.umich.edu else 454103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,16); 464103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x1) 474103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,0); 484103Ssaidi@eecs.umich.edu else 494103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,0); 504103Ssaidi@eecs.umich.edu 514103Ssaidi@eecs.umich.edu // Copy over any of the other bits that are set 524103Ssaidi@eecs.umich.edu for (int bit = 15; bit > 0; --bit) { 534103Ssaidi@eecs.umich.edu if (1 << bit & softint && bit > pil) 544103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit); 554103Ssaidi@eecs.umich.edu else 564103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit); 574103Ssaidi@eecs.umich.edu } 584103Ssaidi@eecs.umich.edu} 594103Ssaidi@eecs.umich.edu 604103Ssaidi@eecs.umich.edu 613817Ssaidi@eecs.umich.eduvoid 624185Ssaidi@eecs.umich.eduMiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 632650Ssaidi@eecs.umich.edu{ 642650Ssaidi@eecs.umich.edu int64_t time; 652650Ssaidi@eecs.umich.edu switch (miscReg) { 662982Sstever@eecs.umich.edu /* Full system only ASRs */ 673919Shsul@eecs.umich.edu case MISCREG_SOFTINT: 684172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val);; 694103Ssaidi@eecs.umich.edu checkSoftInt(tc); 703919Shsul@eecs.umich.edu break; 713919Shsul@eecs.umich.edu case MISCREG_SOFTINT_CLR: 724172Ssaidi@eecs.umich.edu return setReg(MISCREG_SOFTINT, ~val & softint, tc); 733919Shsul@eecs.umich.edu case MISCREG_SOFTINT_SET: 744172Ssaidi@eecs.umich.edu return setReg(MISCREG_SOFTINT, val | softint, tc); 752650Ssaidi@eecs.umich.edu 763919Shsul@eecs.umich.edu case MISCREG_TICK_CMPR: 773919Shsul@eecs.umich.edu if (tickCompare == NULL) 783919Shsul@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 794172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 804103Ssaidi@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 813919Shsul@eecs.umich.edu tickCompare->deschedule(); 823919Shsul@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 834103Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 844103Ssaidi@eecs.umich.edu if (tickCompare->scheduled()) 854103Ssaidi@eecs.umich.edu tickCompare->deschedule(); 863919Shsul@eecs.umich.edu tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 874103Ssaidi@eecs.umich.edu } 883919Shsul@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 893919Shsul@eecs.umich.edu break; 902650Ssaidi@eecs.umich.edu 913919Shsul@eecs.umich.edu case MISCREG_STICK_CMPR: 923919Shsul@eecs.umich.edu if (sTickCompare == NULL) 933919Shsul@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 944172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 953919Shsul@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 963919Shsul@eecs.umich.edu sTickCompare->deschedule(); 973919Shsul@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 983919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 994103Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) { 1004103Ssaidi@eecs.umich.edu if (sTickCompare->scheduled()) 1014103Ssaidi@eecs.umich.edu sTickCompare->deschedule(); 1023919Shsul@eecs.umich.edu sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 1034103Ssaidi@eecs.umich.edu } 1043919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1053919Shsul@eecs.umich.edu break; 1062650Ssaidi@eecs.umich.edu 1073919Shsul@eecs.umich.edu case MISCREG_PSTATE: 1084172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1093827Shsul@eecs.umich.edu 1103919Shsul@eecs.umich.edu case MISCREG_PIL: 1114172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1124103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1133919Shsul@eecs.umich.edu break; 1142650Ssaidi@eecs.umich.edu 1153919Shsul@eecs.umich.edu case MISCREG_HVER: 1163919Shsul@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 1172650Ssaidi@eecs.umich.edu 1183921Shsul@eecs.umich.edu case MISCREG_HINTP: 1194172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1204103Ssaidi@eecs.umich.edu if (hintp) 1214103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_HINTP,0); 1224103Ssaidi@eecs.umich.edu else 1234103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_HINTP,0); 1244103Ssaidi@eecs.umich.edu break; 1253921Shsul@eecs.umich.edu 1263919Shsul@eecs.umich.edu case MISCREG_HTBA: 1273919Shsul@eecs.umich.edu // clear lower 7 bits on writes. 1284172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1293919Shsul@eecs.umich.edu break; 1302650Ssaidi@eecs.umich.edu 1313919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1323919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1334172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1344103Ssaidi@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 1354103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0); 1364103Ssaidi@eecs.umich.edu else 1374103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_CPU_MONDO,0); 1384103Ssaidi@eecs.umich.edu break; 1393919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1403919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1414172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1424103Ssaidi@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 1434103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0); 1444103Ssaidi@eecs.umich.edu else 1454103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_DEV_MONDO,0); 1464103Ssaidi@eecs.umich.edu break; 1473919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1483919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1494172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1504103Ssaidi@eecs.umich.edu if (res_error_head != res_error_tail) 1514103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0); 1524103Ssaidi@eecs.umich.edu else 1534103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_RES_ERROR,0); 1544103Ssaidi@eecs.umich.edu break; 1553919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1563919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1574172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1584103Ssaidi@eecs.umich.edu // This one doesn't have an interrupt to report to the guest OS 1593919Shsul@eecs.umich.edu break; 1603828Shsul@eecs.umich.edu 1613919Shsul@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1623919Shsul@eecs.umich.edu if (hSTickCompare == NULL) 1633919Shsul@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1644172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1653919Shsul@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1663919Shsul@eecs.umich.edu hSTickCompare->deschedule(); 1673919Shsul@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1683919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 1694103Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) { 1704103Ssaidi@eecs.umich.edu if (hSTickCompare->scheduled()) 1714103Ssaidi@eecs.umich.edu hSTickCompare->deschedule(); 1723919Shsul@eecs.umich.edu hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); 1734103Ssaidi@eecs.umich.edu } 1743919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 1753919Shsul@eecs.umich.edu break; 1763817Ssaidi@eecs.umich.edu 1773919Shsul@eecs.umich.edu case MISCREG_HPSTATE: 1783919Shsul@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 1794172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val | HPSTATE::id); 1804103Ssaidi@eecs.umich.edu#if FULL_SYSTEM 1814103Ssaidi@eecs.umich.edu if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 1824103Ssaidi@eecs.umich.edu tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0); 1834103Ssaidi@eecs.umich.edu else 1844103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0); 1854103Ssaidi@eecs.umich.edu#endif 1863919Shsul@eecs.umich.edu break; 1873919Shsul@eecs.umich.edu case MISCREG_HTSTATE: 1883919Shsul@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1894172Ssaidi@eecs.umich.edu setRegNoEffect(miscReg, val); 1903919Shsul@eecs.umich.edu break; 1913817Ssaidi@eecs.umich.edu 1923919Shsul@eecs.umich.edu default: 1933919Shsul@eecs.umich.edu panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg)); 1942650Ssaidi@eecs.umich.edu } 1952650Ssaidi@eecs.umich.edu} 1962650Ssaidi@eecs.umich.edu 1972650Ssaidi@eecs.umich.eduMiscReg 1984185Ssaidi@eecs.umich.eduMiscRegFile::readFSReg(int miscReg, ThreadContext * tc) 1992650Ssaidi@eecs.umich.edu{ 2002650Ssaidi@eecs.umich.edu switch (miscReg) { 2013919Shsul@eecs.umich.edu /* Privileged registers. */ 2023825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2033825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2043825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2053825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2063825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2073825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2083825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2093825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2103825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 2113825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 2123825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 2133825Ssaidi@eecs.umich.edu case MISCREG_PIL: 2143825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 2153825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 2163825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 2173825Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2183825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2194172Ssaidi@eecs.umich.edu return readRegNoEffect(miscReg) ; 2202650Ssaidi@eecs.umich.edu 2213825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 2224172Ssaidi@eecs.umich.edu return readRegNoEffect(miscReg) & ULL(~0x7FFF); 2233825Ssaidi@eecs.umich.edu case MISCREG_HVER: 2243825Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 2252650Ssaidi@eecs.umich.edu 2263825Ssaidi@eecs.umich.edu default: 2273825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 2282650Ssaidi@eecs.umich.edu } 2292650Ssaidi@eecs.umich.edu} 2303817Ssaidi@eecs.umich.edu/* 2313919Shsul@eecs.umich.edu In Niagra STICK==TICK so this isn't needed 2323919Shsul@eecs.umich.edu case MISCREG_STICK: 2333919Shsul@eecs.umich.edu SparcSystem *sys; 2343919Shsul@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 2353919Shsul@eecs.umich.edu assert(sys != NULL); 2363919Shsul@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 2373817Ssaidi@eecs.umich.edu*/ 2383817Ssaidi@eecs.umich.edu 2393817Ssaidi@eecs.umich.edu 2402650Ssaidi@eecs.umich.edu 2412651Ssaidi@eecs.umich.eduvoid 2422680Sktlim@umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 2432651Ssaidi@eecs.umich.edu{ 2442651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 2452651Ssaidi@eecs.umich.edu} 2462651Ssaidi@eecs.umich.edu 2472651Ssaidi@eecs.umich.eduvoid 2482680Sktlim@umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 2492651Ssaidi@eecs.umich.edu{ 2503888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 2513888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 2523888Ssaidi@eecs.umich.edu // more 2533888Ssaidi@eecs.umich.edu int ticks; 2543890Ssaidi@eecs.umich.edu ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 2553919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 2563888Ssaidi@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 2573888Ssaidi@eecs.umich.edu 2583888Ssaidi@eecs.umich.edu if (ticks == 0) { 2593888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 2603888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 2614172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 2624172Ssaidi@eecs.umich.edu setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 2633921Shsul@eecs.umich.edu } 2643888Ssaidi@eecs.umich.edu } else 2653888Ssaidi@eecs.umich.edu sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 2662651Ssaidi@eecs.umich.edu} 2672651Ssaidi@eecs.umich.edu 2682651Ssaidi@eecs.umich.eduvoid 2692680Sktlim@umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 2702651Ssaidi@eecs.umich.edu{ 2713891Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 2723891Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 2733891Ssaidi@eecs.umich.edu // more 2743891Ssaidi@eecs.umich.edu int ticks; 2753891Ssaidi@eecs.umich.edu ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 2763919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 2773891Ssaidi@eecs.umich.edu assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 2783891Ssaidi@eecs.umich.edu 2793891Ssaidi@eecs.umich.edu if (ticks == 0) { 2803891Ssaidi@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 2813891Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 2824172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 2834172Ssaidi@eecs.umich.edu setReg(MISCREG_HINTP, 1, tc); 2843921Shsul@eecs.umich.edu } 2853891Ssaidi@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 2863891Ssaidi@eecs.umich.edu } else 2874103Ssaidi@eecs.umich.edu hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 2882651Ssaidi@eecs.umich.edu} 2892650Ssaidi@eecs.umich.edu 290