ua2005.cc revision 3919
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 313817Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 362650Ssaidi@eecs.umich.edu 373817Ssaidi@eecs.umich.eduusing namespace SparcISA; 383817Ssaidi@eecs.umich.edu 393817Ssaidi@eecs.umich.eduvoid 403817Ssaidi@eecs.umich.eduMiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 413919Shsul@eecs.umich.edu ThreadContext *tc) 422650Ssaidi@eecs.umich.edu{ 432650Ssaidi@eecs.umich.edu int64_t time; 442650Ssaidi@eecs.umich.edu switch (miscReg) { 452982Sstever@eecs.umich.edu /* Full system only ASRs */ 463919Shsul@eecs.umich.edu case MISCREG_SOFTINT: 473919Shsul@eecs.umich.edu // Check if we are going to interrupt because of something 483919Shsul@eecs.umich.edu setReg(miscReg, val); 493919Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 503919Shsul@eecs.umich.edu if (val != 0x10000 && val != 0) 513919Shsul@eecs.umich.edu warn("Writing to softint not really supported, writing: %#x\n", val); 523919Shsul@eecs.umich.edu break; 532650Ssaidi@eecs.umich.edu 543919Shsul@eecs.umich.edu case MISCREG_SOFTINT_CLR: 553919Shsul@eecs.umich.edu return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); 563919Shsul@eecs.umich.edu case MISCREG_SOFTINT_SET: 573919Shsul@eecs.umich.edu return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); 582650Ssaidi@eecs.umich.edu 593919Shsul@eecs.umich.edu case MISCREG_TICK_CMPR: 603919Shsul@eecs.umich.edu if (tickCompare == NULL) 613919Shsul@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 623919Shsul@eecs.umich.edu setReg(miscReg, val); 633919Shsul@eecs.umich.edu if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 643919Shsul@eecs.umich.edu tickCompare->deschedule(); 653919Shsul@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 663919Shsul@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) 673919Shsul@eecs.umich.edu tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 683919Shsul@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 693919Shsul@eecs.umich.edu break; 702650Ssaidi@eecs.umich.edu 713919Shsul@eecs.umich.edu case MISCREG_STICK_CMPR: 723919Shsul@eecs.umich.edu if (sTickCompare == NULL) 733919Shsul@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 743919Shsul@eecs.umich.edu setReg(miscReg, val); 753919Shsul@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 763919Shsul@eecs.umich.edu sTickCompare->deschedule(); 773919Shsul@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 783919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 793919Shsul@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) 803919Shsul@eecs.umich.edu sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 813919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 823919Shsul@eecs.umich.edu break; 832650Ssaidi@eecs.umich.edu 843919Shsul@eecs.umich.edu case MISCREG_PSTATE: 853919Shsul@eecs.umich.edu if (val & ie && !(pstate & ie)) { 863919Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 873919Shsul@eecs.umich.edu } 883919Shsul@eecs.umich.edu setReg(miscReg, val); 893827Shsul@eecs.umich.edu 903919Shsul@eecs.umich.edu case MISCREG_PIL: 913919Shsul@eecs.umich.edu if (val < pil) { 923919Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 933919Shsul@eecs.umich.edu } 943919Shsul@eecs.umich.edu setReg(miscReg, val); 953919Shsul@eecs.umich.edu break; 962650Ssaidi@eecs.umich.edu 973919Shsul@eecs.umich.edu case MISCREG_HVER: 983919Shsul@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 992650Ssaidi@eecs.umich.edu 1003919Shsul@eecs.umich.edu case MISCREG_HTBA: 1013919Shsul@eecs.umich.edu // clear lower 7 bits on writes. 1023919Shsul@eecs.umich.edu setReg(miscReg, val & ULL(~0x7FFF)); 1033919Shsul@eecs.umich.edu break; 1042650Ssaidi@eecs.umich.edu 1053919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1063919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1073919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1083919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1093919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1103919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1113919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1123919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1133919Shsul@eecs.umich.edu setReg(miscReg, val); 1143919Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 1153919Shsul@eecs.umich.edu break; 1163828Shsul@eecs.umich.edu 1173919Shsul@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1183919Shsul@eecs.umich.edu if (hSTickCompare == NULL) 1193919Shsul@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1203919Shsul@eecs.umich.edu setReg(miscReg, val); 1213919Shsul@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1223919Shsul@eecs.umich.edu hSTickCompare->deschedule(); 1233919Shsul@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 1243919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 1253919Shsul@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) 1263919Shsul@eecs.umich.edu hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); 1273919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 1283919Shsul@eecs.umich.edu break; 1293817Ssaidi@eecs.umich.edu 1303919Shsul@eecs.umich.edu case MISCREG_HPSTATE: 1313919Shsul@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 1323919Shsul@eecs.umich.edu setReg(miscReg, val | id); 1333919Shsul@eecs.umich.edu break; 1343919Shsul@eecs.umich.edu case MISCREG_HTSTATE: 1353919Shsul@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1363919Shsul@eecs.umich.edu setReg(miscReg, val); 1373919Shsul@eecs.umich.edu break; 1383817Ssaidi@eecs.umich.edu 1393919Shsul@eecs.umich.edu default: 1403919Shsul@eecs.umich.edu panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg)); 1412650Ssaidi@eecs.umich.edu } 1422650Ssaidi@eecs.umich.edu} 1432650Ssaidi@eecs.umich.edu 1442650Ssaidi@eecs.umich.eduMiscReg 1453817Ssaidi@eecs.umich.eduMiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 1462650Ssaidi@eecs.umich.edu{ 1472650Ssaidi@eecs.umich.edu switch (miscReg) { 1483919Shsul@eecs.umich.edu /* Privileged registers. */ 1493825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1503825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1543825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1553825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1563825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1573825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 1583825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 1593825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 1603825Ssaidi@eecs.umich.edu case MISCREG_PIL: 1613825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1623825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1633825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1643825Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1653825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1663825Ssaidi@eecs.umich.edu return readReg(miscReg) ; 1672650Ssaidi@eecs.umich.edu 1683825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1693825Ssaidi@eecs.umich.edu return readReg(miscReg) & ULL(~0x7FFF); 1703825Ssaidi@eecs.umich.edu case MISCREG_HVER: 1713825Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 1722650Ssaidi@eecs.umich.edu 1733825Ssaidi@eecs.umich.edu default: 1743825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 1752650Ssaidi@eecs.umich.edu } 1762650Ssaidi@eecs.umich.edu} 1773817Ssaidi@eecs.umich.edu/* 1783919Shsul@eecs.umich.edu In Niagra STICK==TICK so this isn't needed 1793919Shsul@eecs.umich.edu case MISCREG_STICK: 1803919Shsul@eecs.umich.edu SparcSystem *sys; 1813919Shsul@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 1823919Shsul@eecs.umich.edu assert(sys != NULL); 1833919Shsul@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 1843817Ssaidi@eecs.umich.edu*/ 1853817Ssaidi@eecs.umich.edu 1863817Ssaidi@eecs.umich.edu 1872650Ssaidi@eecs.umich.edu 1882651Ssaidi@eecs.umich.eduvoid 1892680Sktlim@umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 1902651Ssaidi@eecs.umich.edu{ 1912651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1922651Ssaidi@eecs.umich.edu} 1932651Ssaidi@eecs.umich.edu 1942651Ssaidi@eecs.umich.eduvoid 1952680Sktlim@umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 1962651Ssaidi@eecs.umich.edu{ 1973888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 1983888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 1993888Ssaidi@eecs.umich.edu // more 2003888Ssaidi@eecs.umich.edu int ticks; 2013890Ssaidi@eecs.umich.edu ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 2023919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 2033888Ssaidi@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 2043888Ssaidi@eecs.umich.edu 2053888Ssaidi@eecs.umich.edu if (ticks == 0) { 2063888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 2073888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 2083888Ssaidi@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 2093890Ssaidi@eecs.umich.edu softint |= ULL(1) << 16; 2103888Ssaidi@eecs.umich.edu } else 2113888Ssaidi@eecs.umich.edu sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 2122651Ssaidi@eecs.umich.edu} 2132651Ssaidi@eecs.umich.edu 2142651Ssaidi@eecs.umich.eduvoid 2152680Sktlim@umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 2162651Ssaidi@eecs.umich.edu{ 2173891Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 2183891Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 2193891Ssaidi@eecs.umich.edu // more 2203891Ssaidi@eecs.umich.edu int ticks; 2213891Ssaidi@eecs.umich.edu ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 2223919Shsul@eecs.umich.edu tc->getCpuPtr()->instCount(); 2233891Ssaidi@eecs.umich.edu assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 2243891Ssaidi@eecs.umich.edu 2253891Ssaidi@eecs.umich.edu if (ticks == 0) { 2263891Ssaidi@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 2273891Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 2283891Ssaidi@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 2293891Ssaidi@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 2303891Ssaidi@eecs.umich.edu } else 2313891Ssaidi@eecs.umich.edu sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 2322651Ssaidi@eecs.umich.edu} 2332650Ssaidi@eecs.umich.edu 234