ua2005.cc revision 3897
113481Sgiacomo.travaglini@arm.com/* 213481Sgiacomo.travaglini@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 313481Sgiacomo.travaglini@arm.com * All rights reserved. 413481Sgiacomo.travaglini@arm.com * 513481Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 613481Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 713481Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 813481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 913481Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1013481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1113481Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1213481Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1313481Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1413481Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1513481Sgiacomo.travaglini@arm.com * 1613481Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713481Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813481Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913481Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013481Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113481Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213481Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313481Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413481Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513481Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613481Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713481Sgiacomo.travaglini@arm.com */ 2813481Sgiacomo.travaglini@arm.com 2913481Sgiacomo.travaglini@arm.com#include "arch/sparc/miscregfile.hh" 3013481Sgiacomo.travaglini@arm.com#include "base/bitfield.hh" 3113481Sgiacomo.travaglini@arm.com#include "base/trace.hh" 3213481Sgiacomo.travaglini@arm.com#include "cpu/base.hh" 3313481Sgiacomo.travaglini@arm.com#include "cpu/thread_context.hh" 3413481Sgiacomo.travaglini@arm.com 3513481Sgiacomo.travaglini@arm.comusing namespace SparcISA; 3613481Sgiacomo.travaglini@arm.com 3713481Sgiacomo.travaglini@arm.comvoid 3813481Sgiacomo.travaglini@arm.comMiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 3913481Sgiacomo.travaglini@arm.com ThreadContext *tc) 4013481Sgiacomo.travaglini@arm.com{ 4113481Sgiacomo.travaglini@arm.com int64_t time; 4213481Sgiacomo.travaglini@arm.com switch (miscReg) { 4313481Sgiacomo.travaglini@arm.com /* Full system only ASRs */ 4413481Sgiacomo.travaglini@arm.com case MISCREG_SOFTINT: 4513481Sgiacomo.travaglini@arm.com // Check if we are going to interrupt because of something 4613481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 4713481Sgiacomo.travaglini@arm.com tc->getCpuPtr()->post_interrupt(soft_interrupt); 4813481Sgiacomo.travaglini@arm.com warn("Writing to softint not really supported, writing: %#x\n", val); 4913481Sgiacomo.travaglini@arm.com break; 5013481Sgiacomo.travaglini@arm.com 5113481Sgiacomo.travaglini@arm.com case MISCREG_SOFTINT_CLR: 5213481Sgiacomo.travaglini@arm.com return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); 5313481Sgiacomo.travaglini@arm.com case MISCREG_SOFTINT_SET: 5413481Sgiacomo.travaglini@arm.com return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); 5513481Sgiacomo.travaglini@arm.com 5613481Sgiacomo.travaglini@arm.com case MISCREG_TICK_CMPR: 5713481Sgiacomo.travaglini@arm.com if (tickCompare == NULL) 5813481Sgiacomo.travaglini@arm.com tickCompare = new TickCompareEvent(this, tc); 5913481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 6013481Sgiacomo.travaglini@arm.com if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 6113481Sgiacomo.travaglini@arm.com tickCompare->deschedule(); 6213481Sgiacomo.travaglini@arm.com time = (tick_cmpr & mask(63)) - (tick & mask(63)); 6313481Sgiacomo.travaglini@arm.com if (!(tick_cmpr & ~mask(63)) && time > 0) 6413481Sgiacomo.travaglini@arm.com tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 6513481Sgiacomo.travaglini@arm.com panic("writing to TICK compare register %#X\n", val); 6613481Sgiacomo.travaglini@arm.com break; 6713481Sgiacomo.travaglini@arm.com 6813481Sgiacomo.travaglini@arm.com case MISCREG_STICK_CMPR: 6913481Sgiacomo.travaglini@arm.com if (sTickCompare == NULL) 7013481Sgiacomo.travaglini@arm.com sTickCompare = new STickCompareEvent(this, tc); 7113481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 7213481Sgiacomo.travaglini@arm.com if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 7313481Sgiacomo.travaglini@arm.com sTickCompare->deschedule(); 7413481Sgiacomo.travaglini@arm.com time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 7513481Sgiacomo.travaglini@arm.com tc->getCpuPtr()->instCount(); 7613481Sgiacomo.travaglini@arm.com if (!(stick_cmpr & ~mask(63)) && time > 0) 7713481Sgiacomo.travaglini@arm.com sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 7813481Sgiacomo.travaglini@arm.com DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 7913481Sgiacomo.travaglini@arm.com break; 8013481Sgiacomo.travaglini@arm.com 8113481Sgiacomo.travaglini@arm.com case MISCREG_PSTATE: 8213481Sgiacomo.travaglini@arm.com if (val & PSTATE::ie && !(pstate & PSTATE::ie)) { 8313481Sgiacomo.travaglini@arm.com tc->getCpuPtr()->checkInterrupts = true; 8413481Sgiacomo.travaglini@arm.com } 8513481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 8613481Sgiacomo.travaglini@arm.com 8713481Sgiacomo.travaglini@arm.com case MISCREG_PIL: 8813481Sgiacomo.travaglini@arm.com if (val < pil) { 8913481Sgiacomo.travaglini@arm.com tc->getCpuPtr()->checkInterrupts = true; 9013481Sgiacomo.travaglini@arm.com } 9113481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 9213481Sgiacomo.travaglini@arm.com break; 9313481Sgiacomo.travaglini@arm.com 9413481Sgiacomo.travaglini@arm.com case MISCREG_HVER: 9513481Sgiacomo.travaglini@arm.com panic("Shouldn't be writing HVER\n"); 9613481Sgiacomo.travaglini@arm.com 9713481Sgiacomo.travaglini@arm.com case MISCREG_HTBA: 9813481Sgiacomo.travaglini@arm.com // clear lower 7 bits on writes. 9913481Sgiacomo.travaglini@arm.com setReg(miscReg, val & ULL(~0x7FFF)); 10013481Sgiacomo.travaglini@arm.com break; 10113481Sgiacomo.travaglini@arm.com 10213481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_CPU_MONDO_HEAD: 10313481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_CPU_MONDO_TAIL: 10413481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_DEV_MONDO_HEAD: 10513481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_DEV_MONDO_TAIL: 10613481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_RES_ERROR_HEAD: 10713481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_RES_ERROR_TAIL: 10813481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_NRES_ERROR_HEAD: 10913481Sgiacomo.travaglini@arm.com case MISCREG_QUEUE_NRES_ERROR_TAIL: 11013481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 11113481Sgiacomo.travaglini@arm.com tc->getCpuPtr()->checkInterrupts = true; 11213481Sgiacomo.travaglini@arm.com break; 11313481Sgiacomo.travaglini@arm.com 11413481Sgiacomo.travaglini@arm.com case MISCREG_HSTICK_CMPR: 11513481Sgiacomo.travaglini@arm.com if (hSTickCompare == NULL) 11613481Sgiacomo.travaglini@arm.com hSTickCompare = new HSTickCompareEvent(this, tc); 11713481Sgiacomo.travaglini@arm.com setReg(miscReg, val); 11813481Sgiacomo.travaglini@arm.com if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 11913481Sgiacomo.travaglini@arm.com hSTickCompare->deschedule(); 12013481Sgiacomo.travaglini@arm.com time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 12113481Sgiacomo.travaglini@arm.com tc->getCpuPtr()->instCount(); 12213481Sgiacomo.travaglini@arm.com if (!(hstick_cmpr & ~mask(63)) && time > 0) 12313481Sgiacomo.travaglini@arm.com hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); 12413481Sgiacomo.travaglini@arm.com DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 12513481Sgiacomo.travaglini@arm.com break; 12613481Sgiacomo.travaglini@arm.com 127 case MISCREG_HPSTATE: 128 // T1000 spec says impl. dependent val must always be 1 129 setReg(miscReg, val | HPSTATE::id); 130 break; 131 case MISCREG_HTSTATE: 132 case MISCREG_STRAND_STS_REG: 133 setReg(miscReg, val); 134 break; 135 136 default: 137 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg)); 138 } 139} 140 141MiscReg 142MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 143{ 144 switch (miscReg) { 145 /* Privileged registers. */ 146 case MISCREG_QUEUE_CPU_MONDO_HEAD: 147 case MISCREG_QUEUE_CPU_MONDO_TAIL: 148 case MISCREG_QUEUE_DEV_MONDO_HEAD: 149 case MISCREG_QUEUE_DEV_MONDO_TAIL: 150 case MISCREG_QUEUE_RES_ERROR_HEAD: 151 case MISCREG_QUEUE_RES_ERROR_TAIL: 152 case MISCREG_QUEUE_NRES_ERROR_HEAD: 153 case MISCREG_QUEUE_NRES_ERROR_TAIL: 154 case MISCREG_SOFTINT: 155 case MISCREG_TICK_CMPR: 156 case MISCREG_STICK_CMPR: 157 case MISCREG_PIL: 158 case MISCREG_HPSTATE: 159 case MISCREG_HINTP: 160 case MISCREG_HTSTATE: 161 case MISCREG_STRAND_STS_REG: 162 case MISCREG_HSTICK_CMPR: 163 return readReg(miscReg) ; 164 165 case MISCREG_HTBA: 166 return readReg(miscReg) & ULL(~0x7FFF); 167 case MISCREG_HVER: 168 return NWindows | MaxTL << 8 | MaxGL << 16; 169 170 default: 171 panic("Invalid read to FS misc register\n"); 172 } 173} 174/* 175 In Niagra STICK==TICK so this isn't needed 176 case MISCREG_STICK: 177 SparcSystem *sys; 178 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 179 assert(sys != NULL); 180 return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 181*/ 182 183 184 185void 186MiscRegFile::processTickCompare(ThreadContext *tc) 187{ 188 panic("tick compare not implemented\n"); 189} 190 191void 192MiscRegFile::processSTickCompare(ThreadContext *tc) 193{ 194 // since our microcode instructions take two cycles we need to check if 195 // we're actually at the correct cycle or we need to wait a little while 196 // more 197 int ticks; 198 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 199 tc->getCpuPtr()->instCount(); 200 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 201 202 if (ticks == 0) { 203 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 204 (stick_cmpr & mask(63))); 205 tc->getCpuPtr()->post_interrupt(soft_interrupt); 206 tc->getCpuPtr()->checkInterrupts = true; 207 softint |= ULL(1) << 16; 208 } else 209 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 210} 211 212void 213MiscRegFile::processHSTickCompare(ThreadContext *tc) 214{ 215 // since our microcode instructions take two cycles we need to check if 216 // we're actually at the correct cycle or we need to wait a little while 217 // more 218 int ticks; 219 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 220 tc->getCpuPtr()->instCount(); 221 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 222 223 if (ticks == 0) { 224 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 225 (stick_cmpr & mask(63))); 226 tc->getCpuPtr()->post_interrupt(hstick_match); 227 tc->getCpuPtr()->checkInterrupts = true; 228 // Need to do something to cause interrupt to happen here !!! @todo 229 } else 230 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 231} 232 233