ua2005.cc revision 3891
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include "arch/sparc/miscregfile.hh" 32#include "base/bitfield.hh" 33#include "base/trace.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" 36 37using namespace SparcISA; 38 39void 40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 41 ThreadContext *tc) 42{ 43 int64_t time; 44 switch (miscReg) { 45 /* Full system only ASRs */ 46 case MISCREG_SOFTINT: 47 // Check if we are going to interrupt because of something 48 setReg(miscReg, val); 49 tc->getCpuPtr()->checkInterrupts = true; 50 warn("Writing to softint not really supported, writing: %#x\n", val); 51 break; 52 53 case MISCREG_SOFTINT_CLR: 54 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); 55 case MISCREG_SOFTINT_SET: 56 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); 57 58 case MISCREG_TICK_CMPR: 59 if (tickCompare == NULL) 60 tickCompare = new TickCompareEvent(this, tc); 61 setReg(miscReg, val); 62 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 63 tickCompare->deschedule(); 64 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 65 if (!(tick_cmpr & ~mask(63)) && time > 0) 66 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 67 panic("writing to TICK compare register %#X\n", val); 68 break; 69 70 case MISCREG_STICK_CMPR: 71 if (sTickCompare == NULL) 72 sTickCompare = new STickCompareEvent(this, tc); 73 setReg(miscReg, val); 74 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 75 sTickCompare->deschedule(); 76 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 77 tc->getCpuPtr()->instCount(); 78 if (!(stick_cmpr & ~mask(63)) && time > 0) 79 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 80 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 81 break; 82 83 case MISCREG_PSTATE: 84 if (val & ie && !(pstate & ie)) { 85 tc->getCpuPtr()->checkInterrupts = true; 86 } 87 setReg(miscReg, val); 88 89 case MISCREG_PIL: 90 if (val < pil) { 91 tc->getCpuPtr()->checkInterrupts = true; 92 } 93 setReg(miscReg, val); 94 break; 95 96 case MISCREG_HVER: 97 panic("Shouldn't be writing HVER\n"); 98 99 case MISCREG_HTBA: 100 // clear lower 7 bits on writes. 101 setReg(miscReg, val & ULL(~0x7FFF)); 102 break; 103 104 case MISCREG_QUEUE_CPU_MONDO_HEAD: 105 case MISCREG_QUEUE_CPU_MONDO_TAIL: 106 case MISCREG_QUEUE_DEV_MONDO_HEAD: 107 case MISCREG_QUEUE_DEV_MONDO_TAIL: 108 case MISCREG_QUEUE_RES_ERROR_HEAD: 109 case MISCREG_QUEUE_RES_ERROR_TAIL: 110 case MISCREG_QUEUE_NRES_ERROR_HEAD: 111 case MISCREG_QUEUE_NRES_ERROR_TAIL: 112 setReg(miscReg, val); 113 tc->getCpuPtr()->checkInterrupts = true; 114 break; 115 116 case MISCREG_HSTICK_CMPR: 117 if (hSTickCompare == NULL) 118 hSTickCompare = new HSTickCompareEvent(this, tc); 119 setReg(miscReg, val); 120 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 121 hSTickCompare->deschedule(); 122 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 123 tc->getCpuPtr()->instCount(); 124 if (!(hstick_cmpr & ~mask(63)) && time > 0) 125 hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); 126 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 127 break; 128 129 case MISCREG_HPSTATE: 130 // T1000 spec says impl. dependent val must always be 1 131 setReg(miscReg, val | id); 132 break; 133 case MISCREG_HTSTATE: 134 case MISCREG_STRAND_STS_REG: 135 setReg(miscReg, val); 136 break; 137 138 default: 139 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg)); 140 } 141} 142 143MiscReg 144MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 145{ 146 switch (miscReg) { 147 /* Privileged registers. */ 148 case MISCREG_QUEUE_CPU_MONDO_HEAD: 149 case MISCREG_QUEUE_CPU_MONDO_TAIL: 150 case MISCREG_QUEUE_DEV_MONDO_HEAD: 151 case MISCREG_QUEUE_DEV_MONDO_TAIL: 152 case MISCREG_QUEUE_RES_ERROR_HEAD: 153 case MISCREG_QUEUE_RES_ERROR_TAIL: 154 case MISCREG_QUEUE_NRES_ERROR_HEAD: 155 case MISCREG_QUEUE_NRES_ERROR_TAIL: 156 case MISCREG_SOFTINT: 157 case MISCREG_TICK_CMPR: 158 case MISCREG_STICK_CMPR: 159 case MISCREG_PIL: 160 case MISCREG_HPSTATE: 161 case MISCREG_HINTP: 162 case MISCREG_HTSTATE: 163 case MISCREG_STRAND_STS_REG: 164 case MISCREG_HSTICK_CMPR: 165 return readReg(miscReg) ; 166 167 case MISCREG_HTBA: 168 return readReg(miscReg) & ULL(~0x7FFF); 169 case MISCREG_HVER: 170 return NWindows | MaxTL << 8 | MaxGL << 16; 171 172 default: 173 panic("Invalid read to FS misc register\n"); 174 } 175} 176/* 177 In Niagra STICK==TICK so this isn't needed 178 case MISCREG_STICK: 179 SparcSystem *sys; 180 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 181 assert(sys != NULL); 182 return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 183*/ 184 185 186 187void 188MiscRegFile::processTickCompare(ThreadContext *tc) 189{ 190 panic("tick compare not implemented\n"); 191} 192 193void 194MiscRegFile::processSTickCompare(ThreadContext *tc) 195{ 196 // since our microcode instructions take two cycles we need to check if 197 // we're actually at the correct cycle or we need to wait a little while 198 // more 199 int ticks; 200 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 201 tc->getCpuPtr()->instCount(); 202 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 203 204 if (ticks == 0) { 205 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 206 (stick_cmpr & mask(63))); 207 tc->getCpuPtr()->checkInterrupts = true; 208 softint |= ULL(1) << 16; 209 } else 210 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 211} 212 213void 214MiscRegFile::processHSTickCompare(ThreadContext *tc) 215{ 216 // since our microcode instructions take two cycles we need to check if 217 // we're actually at the correct cycle or we need to wait a little while 218 // more 219 int ticks; 220 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 221 tc->getCpuPtr()->instCount(); 222 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 223 224 if (ticks == 0) { 225 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 226 (stick_cmpr & mask(63))); 227 tc->getCpuPtr()->checkInterrupts = true; 228 // Need to do something to cause interrupt to happen here !!! @todo 229 } else 230 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 231} 232 233