ua2005.cc revision 3888
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 313817Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 362650Ssaidi@eecs.umich.edu 373817Ssaidi@eecs.umich.eduusing namespace SparcISA; 383817Ssaidi@eecs.umich.edu 393817Ssaidi@eecs.umich.eduvoid 403817Ssaidi@eecs.umich.eduMiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 412680Sktlim@umich.edu ThreadContext *tc) 422650Ssaidi@eecs.umich.edu{ 432650Ssaidi@eecs.umich.edu int64_t time; 442650Ssaidi@eecs.umich.edu switch (miscReg) { 452982Sstever@eecs.umich.edu /* Full system only ASRs */ 462650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 472650Ssaidi@eecs.umich.edu // Check if we are going to interrupt because of something 482650Ssaidi@eecs.umich.edu setReg(miscReg, val); 493827Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 503828Shsul@eecs.umich.edu warn("Writing to softint not really supported, writing: %#x\n", val); 513817Ssaidi@eecs.umich.edu break; 522650Ssaidi@eecs.umich.edu 532650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_CLR: 542680Sktlim@umich.edu return setRegWithEffect(miscReg, ~val & softint, tc); 552650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_SET: 562680Sktlim@umich.edu return setRegWithEffect(miscReg, val | softint, tc); 572650Ssaidi@eecs.umich.edu 582650Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 592651Ssaidi@eecs.umich.edu if (tickCompare == NULL) 602680Sktlim@umich.edu tickCompare = new TickCompareEvent(this, tc); 612650Ssaidi@eecs.umich.edu setReg(miscReg, val); 623817Ssaidi@eecs.umich.edu if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 633817Ssaidi@eecs.umich.edu tickCompare->deschedule(); 643817Ssaidi@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 653817Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) 663817Ssaidi@eecs.umich.edu tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 673888Ssaidi@eecs.umich.edu panic("writing to TICK compare register %#X\n", val); 683817Ssaidi@eecs.umich.edu break; 692650Ssaidi@eecs.umich.edu 702650Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 712651Ssaidi@eecs.umich.edu if (sTickCompare == NULL) 722680Sktlim@umich.edu sTickCompare = new STickCompareEvent(this, tc); 732650Ssaidi@eecs.umich.edu setReg(miscReg, val); 743888Ssaidi@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 753817Ssaidi@eecs.umich.edu sTickCompare->deschedule(); 763888Ssaidi@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) + (int64_t)stick) - 773888Ssaidi@eecs.umich.edu tc->getCpuPtr()->instCount(); 783817Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) 793888Ssaidi@eecs.umich.edu sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 803888Ssaidi@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 813817Ssaidi@eecs.umich.edu break; 822650Ssaidi@eecs.umich.edu 833827Shsul@eecs.umich.edu case MISCREG_PSTATE: 843827Shsul@eecs.umich.edu if (val & ie && !(pstate & ie)) { 853827Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 863827Shsul@eecs.umich.edu } 873827Shsul@eecs.umich.edu setReg(miscReg, val); 883827Shsul@eecs.umich.edu 892650Ssaidi@eecs.umich.edu case MISCREG_PIL: 903827Shsul@eecs.umich.edu if (val < pil) { 913827Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 923827Shsul@eecs.umich.edu } 933817Ssaidi@eecs.umich.edu setReg(miscReg, val); 943817Ssaidi@eecs.umich.edu break; 952650Ssaidi@eecs.umich.edu 963817Ssaidi@eecs.umich.edu case MISCREG_HVER: 973817Ssaidi@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 982650Ssaidi@eecs.umich.edu 992650Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1002650Ssaidi@eecs.umich.edu // clear lower 7 bits on writes. 1012650Ssaidi@eecs.umich.edu setReg(miscReg, val & ULL(~0x7FFF)); 1023817Ssaidi@eecs.umich.edu break; 1032650Ssaidi@eecs.umich.edu 1043828Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1053828Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1063828Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1073828Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1083828Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1093828Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1103828Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1113828Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1123828Shsul@eecs.umich.edu setReg(miscReg, val); 1133828Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 1143828Shsul@eecs.umich.edu break; 1153828Shsul@eecs.umich.edu 1162650Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1172651Ssaidi@eecs.umich.edu if (hSTickCompare == NULL) 1182680Sktlim@umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1192650Ssaidi@eecs.umich.edu setReg(miscReg, val); 1203888Ssaidi@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1213825Ssaidi@eecs.umich.edu hSTickCompare->deschedule(); 1223888Ssaidi@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) + (int64_t)stick) - 1233888Ssaidi@eecs.umich.edu tc->getCpuPtr()->instCount(); 1243817Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) 1253888Ssaidi@eecs.umich.edu hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); 1263828Shsul@eecs.umich.edu warn ("writing to hsTICK compare register value %#X\n", val); 1273817Ssaidi@eecs.umich.edu break; 1283817Ssaidi@eecs.umich.edu 1293817Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1303827Shsul@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 1313827Shsul@eecs.umich.edu setReg(miscReg, val | id); 1323831Ssaidi@eecs.umich.edu break; 1333817Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1343817Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1353817Ssaidi@eecs.umich.edu setReg(miscReg, val); 1363817Ssaidi@eecs.umich.edu break; 1373817Ssaidi@eecs.umich.edu 1382650Ssaidi@eecs.umich.edu default: 1393827Shsul@eecs.umich.edu panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg)); 1402650Ssaidi@eecs.umich.edu } 1412650Ssaidi@eecs.umich.edu} 1422650Ssaidi@eecs.umich.edu 1432650Ssaidi@eecs.umich.eduMiscReg 1443817Ssaidi@eecs.umich.eduMiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 1452650Ssaidi@eecs.umich.edu{ 1462650Ssaidi@eecs.umich.edu switch (miscReg) { 1473825Ssaidi@eecs.umich.edu /* Privileged registers. */ 1483825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1493825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1503825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1543825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1553825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1563825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 1573825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 1583825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 1593825Ssaidi@eecs.umich.edu case MISCREG_PIL: 1603825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1613825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1623825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1633825Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1643825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1653825Ssaidi@eecs.umich.edu return readReg(miscReg) ; 1662650Ssaidi@eecs.umich.edu 1673825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1683825Ssaidi@eecs.umich.edu return readReg(miscReg) & ULL(~0x7FFF); 1693825Ssaidi@eecs.umich.edu case MISCREG_HVER: 1703825Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 1712650Ssaidi@eecs.umich.edu 1723825Ssaidi@eecs.umich.edu default: 1733825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 1742650Ssaidi@eecs.umich.edu } 1752650Ssaidi@eecs.umich.edu} 1763817Ssaidi@eecs.umich.edu/* 1773817Ssaidi@eecs.umich.edu In Niagra STICK==TICK so this isn't needed 1783817Ssaidi@eecs.umich.edu case MISCREG_STICK: 1793817Ssaidi@eecs.umich.edu SparcSystem *sys; 1803817Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 1813817Ssaidi@eecs.umich.edu assert(sys != NULL); 1823817Ssaidi@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 1833817Ssaidi@eecs.umich.edu*/ 1843817Ssaidi@eecs.umich.edu 1853817Ssaidi@eecs.umich.edu 1862650Ssaidi@eecs.umich.edu 1872651Ssaidi@eecs.umich.eduvoid 1882680Sktlim@umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 1892651Ssaidi@eecs.umich.edu{ 1902651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1912651Ssaidi@eecs.umich.edu} 1922651Ssaidi@eecs.umich.edu 1932651Ssaidi@eecs.umich.eduvoid 1942680Sktlim@umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 1952651Ssaidi@eecs.umich.edu{ 1963888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 1973888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 1983888Ssaidi@eecs.umich.edu // more 1993888Ssaidi@eecs.umich.edu int ticks; 2003888Ssaidi@eecs.umich.edu ticks = (stick_cmpr & mask(63)) - tc->getCpuPtr()->instCount(); 2013888Ssaidi@eecs.umich.edu assert(ticks >= 0 && "stick compare missed interrupt cycle"); 2023888Ssaidi@eecs.umich.edu 2033888Ssaidi@eecs.umich.edu if (ticks == 0) { 2043888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 2053888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 2063888Ssaidi@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 2073888Ssaidi@eecs.umich.edu 2083888Ssaidi@eecs.umich.edu } else 2093888Ssaidi@eecs.umich.edu sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 2102651Ssaidi@eecs.umich.edu} 2112651Ssaidi@eecs.umich.edu 2122651Ssaidi@eecs.umich.eduvoid 2132680Sktlim@umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 2142651Ssaidi@eecs.umich.edu{ 2153888Ssaidi@eecs.umich.edu panic("hstick compare not implemented\n"); 2162651Ssaidi@eecs.umich.edu} 2172650Ssaidi@eecs.umich.edu 218