ua2005.cc revision 3828
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 313817Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 362650Ssaidi@eecs.umich.edu 373817Ssaidi@eecs.umich.eduusing namespace SparcISA; 383817Ssaidi@eecs.umich.edu 393817Ssaidi@eecs.umich.eduvoid 403817Ssaidi@eecs.umich.eduMiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 412680Sktlim@umich.edu ThreadContext *tc) 422650Ssaidi@eecs.umich.edu{ 432650Ssaidi@eecs.umich.edu int64_t time; 442650Ssaidi@eecs.umich.edu switch (miscReg) { 452982Sstever@eecs.umich.edu /* Full system only ASRs */ 462650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 472650Ssaidi@eecs.umich.edu // Check if we are going to interrupt because of something 482650Ssaidi@eecs.umich.edu setReg(miscReg, val); 493827Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 503828Shsul@eecs.umich.edu warn("Writing to softint not really supported, writing: %#x\n", val); 513817Ssaidi@eecs.umich.edu break; 522650Ssaidi@eecs.umich.edu 532650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_CLR: 542680Sktlim@umich.edu return setRegWithEffect(miscReg, ~val & softint, tc); 552650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_SET: 562680Sktlim@umich.edu return setRegWithEffect(miscReg, val | softint, tc); 572650Ssaidi@eecs.umich.edu 582650Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 592651Ssaidi@eecs.umich.edu if (tickCompare == NULL) 602680Sktlim@umich.edu tickCompare = new TickCompareEvent(this, tc); 612650Ssaidi@eecs.umich.edu setReg(miscReg, val); 623817Ssaidi@eecs.umich.edu if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 633817Ssaidi@eecs.umich.edu tickCompare->deschedule(); 643817Ssaidi@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 653817Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) 663817Ssaidi@eecs.umich.edu tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 673828Shsul@eecs.umich.edu warn ("writing to TICK compare register %#X\n", val); 683817Ssaidi@eecs.umich.edu break; 692650Ssaidi@eecs.umich.edu 702650Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 712651Ssaidi@eecs.umich.edu if (sTickCompare == NULL) 722680Sktlim@umich.edu sTickCompare = new STickCompareEvent(this, tc); 732650Ssaidi@eecs.umich.edu setReg(miscReg, val); 743817Ssaidi@eecs.umich.edu if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 753817Ssaidi@eecs.umich.edu sTickCompare->deschedule(); 763817Ssaidi@eecs.umich.edu time = (stick_cmpr & mask(63)) - (stick & mask(63)); 773817Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) 783817Ssaidi@eecs.umich.edu sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 793828Shsul@eecs.umich.edu warn ("writing to sTICK compare register value %#X\n", val); 803817Ssaidi@eecs.umich.edu break; 812650Ssaidi@eecs.umich.edu 823827Shsul@eecs.umich.edu case MISCREG_PSTATE: 833827Shsul@eecs.umich.edu if (val & ie && !(pstate & ie)) { 843827Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 853827Shsul@eecs.umich.edu } 863827Shsul@eecs.umich.edu setReg(miscReg, val); 873827Shsul@eecs.umich.edu 882650Ssaidi@eecs.umich.edu case MISCREG_PIL: 893827Shsul@eecs.umich.edu if (val < pil) { 903827Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 913827Shsul@eecs.umich.edu } 923817Ssaidi@eecs.umich.edu setReg(miscReg, val); 933817Ssaidi@eecs.umich.edu break; 942650Ssaidi@eecs.umich.edu 953817Ssaidi@eecs.umich.edu case MISCREG_HVER: 963817Ssaidi@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 972650Ssaidi@eecs.umich.edu 982650Ssaidi@eecs.umich.edu case MISCREG_HTBA: 992650Ssaidi@eecs.umich.edu // clear lower 7 bits on writes. 1002650Ssaidi@eecs.umich.edu setReg(miscReg, val & ULL(~0x7FFF)); 1013817Ssaidi@eecs.umich.edu break; 1022650Ssaidi@eecs.umich.edu 1033828Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1043828Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1053828Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1063828Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1073828Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1083828Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1093828Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1103828Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1113828Shsul@eecs.umich.edu setReg(miscReg, val); 1123828Shsul@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 1133828Shsul@eecs.umich.edu break; 1143828Shsul@eecs.umich.edu 1152650Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1162651Ssaidi@eecs.umich.edu if (hSTickCompare == NULL) 1172680Sktlim@umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1182650Ssaidi@eecs.umich.edu setReg(miscReg, val); 1193817Ssaidi@eecs.umich.edu if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 1203825Ssaidi@eecs.umich.edu hSTickCompare->deschedule(); 1213817Ssaidi@eecs.umich.edu time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 1223817Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) 1233817Ssaidi@eecs.umich.edu hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 1243828Shsul@eecs.umich.edu warn ("writing to hsTICK compare register value %#X\n", val); 1253817Ssaidi@eecs.umich.edu break; 1263817Ssaidi@eecs.umich.edu 1273817Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1283827Shsul@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 1293827Shsul@eecs.umich.edu setReg(miscReg, val | id); 1303827Shsul@eecs.umich.edu 1313817Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1323817Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1333817Ssaidi@eecs.umich.edu setReg(miscReg, val); 1343817Ssaidi@eecs.umich.edu break; 1353817Ssaidi@eecs.umich.edu 1362650Ssaidi@eecs.umich.edu default: 1373827Shsul@eecs.umich.edu panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg)); 1382650Ssaidi@eecs.umich.edu } 1392650Ssaidi@eecs.umich.edu} 1402650Ssaidi@eecs.umich.edu 1412650Ssaidi@eecs.umich.eduMiscReg 1423817Ssaidi@eecs.umich.eduMiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 1432650Ssaidi@eecs.umich.edu{ 1442650Ssaidi@eecs.umich.edu switch (miscReg) { 1453825Ssaidi@eecs.umich.edu /* Privileged registers. */ 1463825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1473825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1483825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1493825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1503825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1543825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 1553825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 1563825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 1573825Ssaidi@eecs.umich.edu case MISCREG_PIL: 1583825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1593825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1603825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1613825Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1623825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1633825Ssaidi@eecs.umich.edu return readReg(miscReg) ; 1642650Ssaidi@eecs.umich.edu 1653825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1663825Ssaidi@eecs.umich.edu return readReg(miscReg) & ULL(~0x7FFF); 1673825Ssaidi@eecs.umich.edu case MISCREG_HVER: 1683825Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 1692650Ssaidi@eecs.umich.edu 1703825Ssaidi@eecs.umich.edu default: 1713825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 1722650Ssaidi@eecs.umich.edu } 1732650Ssaidi@eecs.umich.edu} 1743817Ssaidi@eecs.umich.edu/* 1753817Ssaidi@eecs.umich.edu In Niagra STICK==TICK so this isn't needed 1763817Ssaidi@eecs.umich.edu case MISCREG_STICK: 1773817Ssaidi@eecs.umich.edu SparcSystem *sys; 1783817Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 1793817Ssaidi@eecs.umich.edu assert(sys != NULL); 1803817Ssaidi@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 1813817Ssaidi@eecs.umich.edu*/ 1823817Ssaidi@eecs.umich.edu 1833817Ssaidi@eecs.umich.edu 1842650Ssaidi@eecs.umich.edu 1852651Ssaidi@eecs.umich.eduvoid 1862680Sktlim@umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 1872651Ssaidi@eecs.umich.edu{ 1882651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1892651Ssaidi@eecs.umich.edu} 1902651Ssaidi@eecs.umich.edu 1912651Ssaidi@eecs.umich.eduvoid 1922680Sktlim@umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 1932651Ssaidi@eecs.umich.edu{ 1942651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1952651Ssaidi@eecs.umich.edu} 1962651Ssaidi@eecs.umich.edu 1972651Ssaidi@eecs.umich.eduvoid 1982680Sktlim@umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 1992651Ssaidi@eecs.umich.edu{ 2002651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 2012651Ssaidi@eecs.umich.edu} 2022650Ssaidi@eecs.umich.edu 203