ua2005.cc revision 3825
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 313817Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 362650Ssaidi@eecs.umich.edu 373817Ssaidi@eecs.umich.eduusing namespace SparcISA; 383817Ssaidi@eecs.umich.edu 393817Ssaidi@eecs.umich.eduvoid 403817Ssaidi@eecs.umich.eduMiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 412680Sktlim@umich.edu ThreadContext *tc) 422650Ssaidi@eecs.umich.edu{ 432650Ssaidi@eecs.umich.edu int64_t time; 443817Ssaidi@eecs.umich.edu int oldLevel, newLevel; 452650Ssaidi@eecs.umich.edu switch (miscReg) { 463825Ssaidi@eecs.umich.edu /* Full system only ASRs */ 473825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 483825Ssaidi@eecs.umich.edu // Check if we are going to interrupt because of something 493825Ssaidi@eecs.umich.edu oldLevel = InterruptLevel(softint); 503825Ssaidi@eecs.umich.edu newLevel = InterruptLevel(val); 513825Ssaidi@eecs.umich.edu setReg(miscReg, val); 523825Ssaidi@eecs.umich.edu //if (newLevel > oldLevel) 533825Ssaidi@eecs.umich.edu ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 543825Ssaidi@eecs.umich.edu //tc->getCpuPtr()->checkInterrupts = true; 553825Ssaidi@eecs.umich.edu //panic("SOFTINT not implemented\n"); 563825Ssaidi@eecs.umich.edu warn("Writing to softint not really supported, writing: %#x\n", val); 573825Ssaidi@eecs.umich.edu break; 582650Ssaidi@eecs.umich.edu 593825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_CLR: 603825Ssaidi@eecs.umich.edu return setRegWithEffect(miscReg, ~val & softint, tc); 613825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_SET: 623825Ssaidi@eecs.umich.edu return setRegWithEffect(miscReg, val | softint, tc); 632650Ssaidi@eecs.umich.edu 643825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 653825Ssaidi@eecs.umich.edu if (tickCompare == NULL) 663825Ssaidi@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 673825Ssaidi@eecs.umich.edu setReg(miscReg, val); 683825Ssaidi@eecs.umich.edu if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 693817Ssaidi@eecs.umich.edu tickCompare->deschedule(); 703825Ssaidi@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 713825Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) 723825Ssaidi@eecs.umich.edu tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 733825Ssaidi@eecs.umich.edu warn ("writing to TICK compare register %#X\n", val); 743825Ssaidi@eecs.umich.edu break; 752650Ssaidi@eecs.umich.edu 763825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 773825Ssaidi@eecs.umich.edu if (sTickCompare == NULL) 783825Ssaidi@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 793825Ssaidi@eecs.umich.edu setReg(miscReg, val); 803825Ssaidi@eecs.umich.edu if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 813825Ssaidi@eecs.umich.edu sTickCompare->deschedule(); 823825Ssaidi@eecs.umich.edu time = (stick_cmpr & mask(63)) - (stick & mask(63)); 833825Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) 843825Ssaidi@eecs.umich.edu sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 853825Ssaidi@eecs.umich.edu warn ("writing to sTICK compare register value %#X\n", val); 863825Ssaidi@eecs.umich.edu break; 872650Ssaidi@eecs.umich.edu 883825Ssaidi@eecs.umich.edu case MISCREG_PIL: 893825Ssaidi@eecs.umich.edu setReg(miscReg, val); 903825Ssaidi@eecs.umich.edu //tc->getCpuPtr()->checkInterrupts; 913825Ssaidi@eecs.umich.edu // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 923825Ssaidi@eecs.umich.edu // panic("PIL not implemented\n"); 933825Ssaidi@eecs.umich.edu warn ("PIL not implemented writing %#X\n", val); 943825Ssaidi@eecs.umich.edu break; 952650Ssaidi@eecs.umich.edu 963825Ssaidi@eecs.umich.edu case MISCREG_HVER: 973825Ssaidi@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 982650Ssaidi@eecs.umich.edu 993825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1003825Ssaidi@eecs.umich.edu // clear lower 7 bits on writes. 1013825Ssaidi@eecs.umich.edu setReg(miscReg, val & ULL(~0x7FFF)); 1023825Ssaidi@eecs.umich.edu break; 1032650Ssaidi@eecs.umich.edu 1043825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1053825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1063825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1073825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1083825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1093825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1103825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1113825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1123825Ssaidi@eecs.umich.edu setReg(miscReg, val); 1133825Ssaidi@eecs.umich.edu tc->getCpuPtr()->checkInterrupts = true; 1143825Ssaidi@eecs.umich.edu break; 1153817Ssaidi@eecs.umich.edu 1163825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1173825Ssaidi@eecs.umich.edu if (hSTickCompare == NULL) 1183825Ssaidi@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1193825Ssaidi@eecs.umich.edu setReg(miscReg, val); 1203825Ssaidi@eecs.umich.edu if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 1213825Ssaidi@eecs.umich.edu hSTickCompare->deschedule(); 1223825Ssaidi@eecs.umich.edu time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 1233825Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) 1243825Ssaidi@eecs.umich.edu hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 1253825Ssaidi@eecs.umich.edu warn ("writing to hsTICK compare register value %#X\n", val); 1263825Ssaidi@eecs.umich.edu break; 1273817Ssaidi@eecs.umich.edu 1283825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1293825Ssaidi@eecs.umich.edu // i.d. is always set on any hpstate write 1303825Ssaidi@eecs.umich.edu setReg(miscReg, val | 1 << 11); 1313825Ssaidi@eecs.umich.edu break; 1323825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1333825Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1343825Ssaidi@eecs.umich.edu setReg(miscReg, val); 1353825Ssaidi@eecs.umich.edu break; 1363825Ssaidi@eecs.umich.edu 1373825Ssaidi@eecs.umich.edu default: 1383825Ssaidi@eecs.umich.edu panic("Invalid write to FS misc register\n"); 1392650Ssaidi@eecs.umich.edu } 1402650Ssaidi@eecs.umich.edu} 1412650Ssaidi@eecs.umich.edu 1422650Ssaidi@eecs.umich.eduMiscReg 1433817Ssaidi@eecs.umich.eduMiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 1442650Ssaidi@eecs.umich.edu{ 1452650Ssaidi@eecs.umich.edu switch (miscReg) { 1463825Ssaidi@eecs.umich.edu /* Privileged registers. */ 1473825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1483825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1493825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1503825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1513825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1523825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1543825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1553825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 1563825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 1573825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 1583825Ssaidi@eecs.umich.edu case MISCREG_PIL: 1593825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1603825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1613825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1623825Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1633825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1643825Ssaidi@eecs.umich.edu return readReg(miscReg) ; 1652650Ssaidi@eecs.umich.edu 1663825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1673825Ssaidi@eecs.umich.edu return readReg(miscReg) & ULL(~0x7FFF); 1683825Ssaidi@eecs.umich.edu case MISCREG_HVER: 1693825Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 1702650Ssaidi@eecs.umich.edu 1713825Ssaidi@eecs.umich.edu default: 1723825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 1732650Ssaidi@eecs.umich.edu } 1742650Ssaidi@eecs.umich.edu} 1753817Ssaidi@eecs.umich.edu/* 1763817Ssaidi@eecs.umich.edu In Niagra STICK==TICK so this isn't needed 1773817Ssaidi@eecs.umich.edu case MISCREG_STICK: 1783817Ssaidi@eecs.umich.edu SparcSystem *sys; 1793817Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 1803817Ssaidi@eecs.umich.edu assert(sys != NULL); 1813817Ssaidi@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 1823817Ssaidi@eecs.umich.edu*/ 1833817Ssaidi@eecs.umich.edu 1843817Ssaidi@eecs.umich.edu 1852650Ssaidi@eecs.umich.edu 1862651Ssaidi@eecs.umich.eduvoid 1872680Sktlim@umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 1882651Ssaidi@eecs.umich.edu{ 1892651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1902651Ssaidi@eecs.umich.edu} 1912651Ssaidi@eecs.umich.edu 1922651Ssaidi@eecs.umich.eduvoid 1932680Sktlim@umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 1942651Ssaidi@eecs.umich.edu{ 1952651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1962651Ssaidi@eecs.umich.edu} 1972651Ssaidi@eecs.umich.edu 1982651Ssaidi@eecs.umich.eduvoid 1992680Sktlim@umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 2002651Ssaidi@eecs.umich.edu{ 2012651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 2022651Ssaidi@eecs.umich.edu} 2032650Ssaidi@eecs.umich.edu 204