ua2005.cc revision 3817
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292650Ssaidi@eecs.umich.edu */ 302650Ssaidi@eecs.umich.edu 313817Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 323817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 333817Ssaidi@eecs.umich.edu#include "base/trace.hh" 343817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 362650Ssaidi@eecs.umich.edu 373817Ssaidi@eecs.umich.eduusing namespace SparcISA; 383817Ssaidi@eecs.umich.edu 393817Ssaidi@eecs.umich.eduvoid 403817Ssaidi@eecs.umich.eduMiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 412680Sktlim@umich.edu ThreadContext *tc) 422650Ssaidi@eecs.umich.edu{ 432650Ssaidi@eecs.umich.edu int64_t time; 443817Ssaidi@eecs.umich.edu int oldLevel, newLevel; 452650Ssaidi@eecs.umich.edu switch (miscReg) { 462982Sstever@eecs.umich.edu /* Full system only ASRs */ 472650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 482650Ssaidi@eecs.umich.edu // Check if we are going to interrupt because of something 493817Ssaidi@eecs.umich.edu oldLevel = InterruptLevel(softint); 503817Ssaidi@eecs.umich.edu newLevel = InterruptLevel(val); 512650Ssaidi@eecs.umich.edu setReg(miscReg, val); 522650Ssaidi@eecs.umich.edu if (newLevel > oldLevel) 532650Ssaidi@eecs.umich.edu ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 542680Sktlim@umich.edu //tc->getCpuPtr()->checkInterrupts = true; 553817Ssaidi@eecs.umich.edu panic("SOFTINT not implemented\n"); 563817Ssaidi@eecs.umich.edu break; 572650Ssaidi@eecs.umich.edu 582650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_CLR: 592680Sktlim@umich.edu return setRegWithEffect(miscReg, ~val & softint, tc); 602650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_SET: 612680Sktlim@umich.edu return setRegWithEffect(miscReg, val | softint, tc); 622650Ssaidi@eecs.umich.edu 632650Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 642651Ssaidi@eecs.umich.edu if (tickCompare == NULL) 652680Sktlim@umich.edu tickCompare = new TickCompareEvent(this, tc); 662650Ssaidi@eecs.umich.edu setReg(miscReg, val); 673817Ssaidi@eecs.umich.edu if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 683817Ssaidi@eecs.umich.edu tickCompare->deschedule(); 693817Ssaidi@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 703817Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) 713817Ssaidi@eecs.umich.edu tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 723817Ssaidi@eecs.umich.edu break; 732650Ssaidi@eecs.umich.edu 742650Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 752651Ssaidi@eecs.umich.edu if (sTickCompare == NULL) 762680Sktlim@umich.edu sTickCompare = new STickCompareEvent(this, tc); 772650Ssaidi@eecs.umich.edu setReg(miscReg, val); 783817Ssaidi@eecs.umich.edu if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 793817Ssaidi@eecs.umich.edu sTickCompare->deschedule(); 803817Ssaidi@eecs.umich.edu time = (stick_cmpr & mask(63)) - (stick & mask(63)); 813817Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) 823817Ssaidi@eecs.umich.edu sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 833817Ssaidi@eecs.umich.edu break; 842650Ssaidi@eecs.umich.edu 852650Ssaidi@eecs.umich.edu case MISCREG_PIL: 863817Ssaidi@eecs.umich.edu setReg(miscReg, val); 873817Ssaidi@eecs.umich.edu //tc->getCpuPtr()->checkInterrupts; 883817Ssaidi@eecs.umich.edu // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 893817Ssaidi@eecs.umich.edu panic("PIL not implemented\n"); 903817Ssaidi@eecs.umich.edu break; 912650Ssaidi@eecs.umich.edu 923817Ssaidi@eecs.umich.edu case MISCREG_HVER: 933817Ssaidi@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 942650Ssaidi@eecs.umich.edu 952650Ssaidi@eecs.umich.edu case MISCREG_HTBA: 962650Ssaidi@eecs.umich.edu // clear lower 7 bits on writes. 972650Ssaidi@eecs.umich.edu setReg(miscReg, val & ULL(~0x7FFF)); 983817Ssaidi@eecs.umich.edu break; 992650Ssaidi@eecs.umich.edu 1002650Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1012651Ssaidi@eecs.umich.edu if (hSTickCompare == NULL) 1022680Sktlim@umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1032650Ssaidi@eecs.umich.edu setReg(miscReg, val); 1043817Ssaidi@eecs.umich.edu if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 1053817Ssaidi@eecs.umich.edu hSTickCompare->deschedule(); 1063817Ssaidi@eecs.umich.edu time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 1073817Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) 1083817Ssaidi@eecs.umich.edu hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 1093817Ssaidi@eecs.umich.edu break; 1103817Ssaidi@eecs.umich.edu 1113817Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1123817Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1133817Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1143817Ssaidi@eecs.umich.edu setReg(miscReg, val); 1153817Ssaidi@eecs.umich.edu break; 1163817Ssaidi@eecs.umich.edu 1172650Ssaidi@eecs.umich.edu default: 1183817Ssaidi@eecs.umich.edu panic("Invalid write to FS misc register\n"); 1192650Ssaidi@eecs.umich.edu } 1202650Ssaidi@eecs.umich.edu} 1212650Ssaidi@eecs.umich.edu 1222650Ssaidi@eecs.umich.eduMiscReg 1233817Ssaidi@eecs.umich.eduMiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 1242650Ssaidi@eecs.umich.edu{ 1252650Ssaidi@eecs.umich.edu switch (miscReg) { 1262650Ssaidi@eecs.umich.edu 1272982Sstever@eecs.umich.edu /* Privileged registers. */ 1282650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 1292650Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 1302650Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 1313817Ssaidi@eecs.umich.edu case MISCREG_PIL: 1322650Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1332650Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1342650Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1353817Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1363817Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1373817Ssaidi@eecs.umich.edu return readReg(miscReg) ; 1382650Ssaidi@eecs.umich.edu 1392650Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1402650Ssaidi@eecs.umich.edu return readReg(miscReg) & ULL(~0x7FFF); 1412650Ssaidi@eecs.umich.edu case MISCREG_HVER: 1422650Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 1432650Ssaidi@eecs.umich.edu 1442650Ssaidi@eecs.umich.edu default: 1453817Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 1462650Ssaidi@eecs.umich.edu } 1472650Ssaidi@eecs.umich.edu} 1483817Ssaidi@eecs.umich.edu/* 1493817Ssaidi@eecs.umich.edu In Niagra STICK==TICK so this isn't needed 1503817Ssaidi@eecs.umich.edu case MISCREG_STICK: 1513817Ssaidi@eecs.umich.edu SparcSystem *sys; 1523817Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 1533817Ssaidi@eecs.umich.edu assert(sys != NULL); 1543817Ssaidi@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 1553817Ssaidi@eecs.umich.edu*/ 1563817Ssaidi@eecs.umich.edu 1573817Ssaidi@eecs.umich.edu 1582650Ssaidi@eecs.umich.edu 1592651Ssaidi@eecs.umich.eduvoid 1602680Sktlim@umich.eduMiscRegFile::processTickCompare(ThreadContext *tc) 1612651Ssaidi@eecs.umich.edu{ 1622651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1632651Ssaidi@eecs.umich.edu} 1642651Ssaidi@eecs.umich.edu 1652651Ssaidi@eecs.umich.eduvoid 1662680Sktlim@umich.eduMiscRegFile::processSTickCompare(ThreadContext *tc) 1672651Ssaidi@eecs.umich.edu{ 1682651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1692651Ssaidi@eecs.umich.edu} 1702651Ssaidi@eecs.umich.edu 1712651Ssaidi@eecs.umich.eduvoid 1722680Sktlim@umich.eduMiscRegFile::processHSTickCompare(ThreadContext *tc) 1732651Ssaidi@eecs.umich.edu{ 1742651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 1752651Ssaidi@eecs.umich.edu} 1762650Ssaidi@eecs.umich.edu 177