tlb.cc revision 8232:b28d06a175be 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/IPR.hh"
42#include "debug/TLB.hh"
43#include "mem/packet_access.hh"
44#include "mem/request.hh"
45#include "sim/system.hh"
46
47/* @todo remove some of the magic constants.  -- ali
48 * */
49namespace SparcISA {
50
51TLB::TLB(const Params *p)
52    : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
53      cacheValid(false)
54{
55    // To make this work you'll have to change the hypervisor and OS
56    if (size > 64)
57        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
58
59    tlb = new TlbEntry[size];
60    std::memset(tlb, 0, sizeof(TlbEntry) * size);
61
62    for (int x = 0; x < size; x++)
63        freeList.push_back(&tlb[x]);
64
65    c0_tsb_ps0 = 0;
66    c0_tsb_ps1 = 0;
67    c0_config = 0;
68    cx_tsb_ps0 = 0;
69    cx_tsb_ps1 = 0;
70    cx_config = 0;
71    sfsr = 0;
72    tag_access = 0;
73    sfar = 0;
74    cacheEntry[0] = NULL;
75    cacheEntry[1] = NULL;
76}
77
78void
79TLB::clearUsedBits()
80{
81    MapIter i;
82    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
83        TlbEntry *t = i->second;
84        if (!t->pte.locked()) {
85            t->used = false;
86            usedEntries--;
87        }
88    }
89}
90
91
92void
93TLB::insert(Addr va, int partition_id, int context_id, bool real,
94        const PageTableEntry& PTE, int entry)
95{
96    MapIter i;
97    TlbEntry *new_entry = NULL;
98//    TlbRange tr;
99    int x;
100
101    cacheValid = false;
102    va &= ~(PTE.size()-1);
103 /*   tr.va = va;
104    tr.size = PTE.size() - 1;
105    tr.contextId = context_id;
106    tr.partitionId = partition_id;
107    tr.real = real;
108*/
109
110    DPRINTF(TLB,
111        "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
112        va, PTE.paddr(), partition_id, context_id, (int)real, entry);
113
114    // Demap any entry that conflicts
115    for (x = 0; x < size; x++) {
116        if (tlb[x].range.real == real &&
117            tlb[x].range.partitionId == partition_id &&
118            tlb[x].range.va < va + PTE.size() - 1 &&
119            tlb[x].range.va + tlb[x].range.size >= va &&
120            (real || tlb[x].range.contextId == context_id ))
121        {
122            if (tlb[x].valid) {
123                freeList.push_front(&tlb[x]);
124                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
125
126                tlb[x].valid = false;
127                if (tlb[x].used) {
128                    tlb[x].used = false;
129                    usedEntries--;
130                }
131                lookupTable.erase(tlb[x].range);
132            }
133        }
134    }
135
136    if (entry != -1) {
137        assert(entry < size && entry >= 0);
138        new_entry = &tlb[entry];
139    } else {
140        if (!freeList.empty()) {
141            new_entry = freeList.front();
142        } else {
143            x = lastReplaced;
144            do {
145                ++x;
146                if (x == size)
147                    x = 0;
148                if (x == lastReplaced)
149                    goto insertAllLocked;
150            } while (tlb[x].pte.locked());
151            lastReplaced = x;
152            new_entry = &tlb[x];
153        }
154    }
155
156insertAllLocked:
157    // Update the last ently if their all locked
158    if (!new_entry) {
159        new_entry = &tlb[size-1];
160    }
161
162    freeList.remove(new_entry);
163    if (new_entry->valid && new_entry->used)
164        usedEntries--;
165    if (new_entry->valid)
166        lookupTable.erase(new_entry->range);
167
168
169    assert(PTE.valid());
170    new_entry->range.va = va;
171    new_entry->range.size = PTE.size() - 1;
172    new_entry->range.partitionId = partition_id;
173    new_entry->range.contextId = context_id;
174    new_entry->range.real = real;
175    new_entry->pte = PTE;
176    new_entry->used = true;;
177    new_entry->valid = true;
178    usedEntries++;
179
180    i = lookupTable.insert(new_entry->range, new_entry);
181    assert(i != lookupTable.end());
182
183    // If all entries have their used bit set, clear it on them all,
184    // but the one we just inserted
185    if (usedEntries == size) {
186        clearUsedBits();
187        new_entry->used = true;
188        usedEntries++;
189    }
190}
191
192
193TlbEntry*
194TLB::lookup(Addr va, int partition_id, bool real, int context_id,
195            bool update_used)
196{
197    MapIter i;
198    TlbRange tr;
199    TlbEntry *t;
200
201    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
202            va, partition_id, context_id, real);
203    // Assemble full address structure
204    tr.va = va;
205    tr.size = 1;
206    tr.contextId = context_id;
207    tr.partitionId = partition_id;
208    tr.real = real;
209
210    // Try to find the entry
211    i = lookupTable.find(tr);
212    if (i == lookupTable.end()) {
213        DPRINTF(TLB, "TLB: No valid entry found\n");
214        return NULL;
215    }
216
217    // Mark the entries used bit and clear other used bits in needed
218    t = i->second;
219    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
220            t->pte.size());
221
222    // Update the used bits only if this is a real access (not a fake
223    // one from virttophys()
224    if (!t->used && update_used) {
225        t->used = true;
226        usedEntries++;
227        if (usedEntries == size) {
228            clearUsedBits();
229            t->used = true;
230            usedEntries++;
231        }
232    }
233
234    return t;
235}
236
237void
238TLB::dumpAll()
239{
240    MapIter i;
241    for (int x = 0; x < size; x++) {
242        if (tlb[x].valid) {
243           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
244                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
245                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
246                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
247        }
248    }
249}
250
251void
252TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
253{
254    TlbRange tr;
255    MapIter i;
256
257    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
258            va, partition_id, context_id, real);
259
260    cacheValid = false;
261
262    // Assemble full address structure
263    tr.va = va;
264    tr.size = 1;
265    tr.contextId = context_id;
266    tr.partitionId = partition_id;
267    tr.real = real;
268
269    // Demap any entry that conflicts
270    i = lookupTable.find(tr);
271    if (i != lookupTable.end()) {
272        DPRINTF(IPR, "TLB: Demapped page\n");
273        i->second->valid = false;
274        if (i->second->used) {
275            i->second->used = false;
276            usedEntries--;
277        }
278        freeList.push_front(i->second);
279        lookupTable.erase(i);
280    }
281}
282
283void
284TLB::demapContext(int partition_id, int context_id)
285{
286    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
287            partition_id, context_id);
288    cacheValid = false;
289    for (int x = 0; x < size; x++) {
290        if (tlb[x].range.contextId == context_id &&
291            tlb[x].range.partitionId == partition_id) {
292            if (tlb[x].valid == true) {
293                freeList.push_front(&tlb[x]);
294            }
295            tlb[x].valid = false;
296            if (tlb[x].used) {
297                tlb[x].used = false;
298                usedEntries--;
299            }
300            lookupTable.erase(tlb[x].range);
301        }
302    }
303}
304
305void
306TLB::demapAll(int partition_id)
307{
308    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
309    cacheValid = false;
310    for (int x = 0; x < size; x++) {
311        if (tlb[x].valid && !tlb[x].pte.locked() &&
312                tlb[x].range.partitionId == partition_id) {
313            freeList.push_front(&tlb[x]);
314            tlb[x].valid = false;
315            if (tlb[x].used) {
316                tlb[x].used = false;
317                usedEntries--;
318            }
319            lookupTable.erase(tlb[x].range);
320        }
321    }
322}
323
324void
325TLB::invalidateAll()
326{
327    cacheValid = false;
328    lookupTable.clear();
329
330    for (int x = 0; x < size; x++) {
331        if (tlb[x].valid == true)
332            freeList.push_back(&tlb[x]);
333        tlb[x].valid = false;
334        tlb[x].used = false;
335    }
336    usedEntries = 0;
337}
338
339uint64_t
340TLB::TteRead(int entry)
341{
342    if (entry >= size)
343        panic("entry: %d\n", entry);
344
345    assert(entry < size);
346    if (tlb[entry].valid)
347        return tlb[entry].pte();
348    else
349        return (uint64_t)-1ll;
350}
351
352uint64_t
353TLB::TagRead(int entry)
354{
355    assert(entry < size);
356    uint64_t tag;
357    if (!tlb[entry].valid)
358        return (uint64_t)-1ll;
359
360    tag = tlb[entry].range.contextId;
361    tag |= tlb[entry].range.va;
362    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
363    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
364    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
365    return tag;
366}
367
368bool
369TLB::validVirtualAddress(Addr va, bool am)
370{
371    if (am)
372        return true;
373    if (va >= StartVAddrHole && va <= EndVAddrHole)
374        return false;
375    return true;
376}
377
378void
379TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
380{
381    if (sfsr & 0x1)
382        sfsr = 0x3;
383    else
384        sfsr = 1;
385
386    if (write)
387        sfsr |= 1 << 2;
388    sfsr |= ct << 4;
389    if (se)
390        sfsr |= 1 << 6;
391    sfsr |= ft << 7;
392    sfsr |= asi << 16;
393}
394
395void
396TLB::writeTagAccess(Addr va, int context)
397{
398    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
399            va, context, mbits(va, 63,13) | mbits(context,12,0));
400
401    tag_access = mbits(va, 63,13) | mbits(context,12,0);
402}
403
404void
405TLB::writeSfsr(Addr a, bool write, ContextType ct,
406        bool se, FaultTypes ft, int asi)
407{
408    DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
409            a, (int)write, ct, ft, asi);
410    TLB::writeSfsr(write, ct, se, ft, asi);
411    sfar = a;
412}
413
414Fault
415TLB::translateInst(RequestPtr req, ThreadContext *tc)
416{
417    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
418
419    Addr vaddr = req->getVaddr();
420    TlbEntry *e;
421
422    assert(req->getAsi() == ASI_IMPLICIT);
423
424    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
425            vaddr, req->getSize());
426
427    // Be fast if we can!
428    if (cacheValid && cacheState == tlbdata) {
429        if (cacheEntry[0]) {
430            if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
431                cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
432                req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
433                return NoFault;
434            }
435        } else {
436            req->setPaddr(vaddr & PAddrImplMask);
437            return NoFault;
438        }
439    }
440
441    bool hpriv = bits(tlbdata,0,0);
442    bool red = bits(tlbdata,1,1);
443    bool priv = bits(tlbdata,2,2);
444    bool addr_mask = bits(tlbdata,3,3);
445    bool lsu_im = bits(tlbdata,4,4);
446
447    int part_id = bits(tlbdata,15,8);
448    int tl = bits(tlbdata,18,16);
449    int pri_context = bits(tlbdata,47,32);
450    int context;
451    ContextType ct;
452    int asi;
453    bool real = false;
454
455    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
456           priv, hpriv, red, lsu_im, part_id);
457
458    if (tl > 0) {
459        asi = ASI_N;
460        ct = Nucleus;
461        context = 0;
462    } else {
463        asi = ASI_P;
464        ct = Primary;
465        context = pri_context;
466    }
467
468    if ( hpriv || red ) {
469        cacheValid = true;
470        cacheState = tlbdata;
471        cacheEntry[0] = NULL;
472        req->setPaddr(vaddr & PAddrImplMask);
473        return NoFault;
474    }
475
476    // If the access is unaligned trap
477    if (vaddr & 0x3) {
478        writeSfsr(false, ct, false, OtherFault, asi);
479        return new MemAddressNotAligned;
480    }
481
482    if (addr_mask)
483        vaddr = vaddr & VAddrAMask;
484
485    if (!validVirtualAddress(vaddr, addr_mask)) {
486        writeSfsr(false, ct, false, VaOutOfRange, asi);
487        return new InstructionAccessException;
488    }
489
490    if (!lsu_im) {
491        e = lookup(vaddr, part_id, true);
492        real = true;
493        context = 0;
494    } else {
495        e = lookup(vaddr, part_id, false, context);
496    }
497
498    if (e == NULL || !e->valid) {
499        writeTagAccess(vaddr, context);
500        if (real)
501            return new InstructionRealTranslationMiss;
502        else
503#if FULL_SYSTEM
504            return new FastInstructionAccessMMUMiss;
505#else
506            return new FastInstructionAccessMMUMiss(req->getVaddr());
507#endif
508    }
509
510    // were not priviledged accesing priv page
511    if (!priv && e->pte.priv()) {
512        writeTagAccess(vaddr, context);
513        writeSfsr(false, ct, false, PrivViolation, asi);
514        return new InstructionAccessException;
515    }
516
517    // cache translation date for next translation
518    cacheValid = true;
519    cacheState = tlbdata;
520    cacheEntry[0] = e;
521
522    req->setPaddr(e->pte.translate(vaddr));
523    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
524    return NoFault;
525}
526
527Fault
528TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
529{
530    /*
531     * @todo this could really use some profiling and fixing to make
532     * it faster!
533     */
534    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
535    Addr vaddr = req->getVaddr();
536    Addr size = req->getSize();
537    ASI asi;
538    asi = (ASI)req->getAsi();
539    bool implicit = false;
540    bool hpriv = bits(tlbdata,0,0);
541    bool unaligned = vaddr & (size - 1);
542
543    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
544            vaddr, size, asi);
545
546    if (lookupTable.size() != 64 - freeList.size())
547       panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
548               freeList.size());
549    if (asi == ASI_IMPLICIT)
550        implicit = true;
551
552    // Only use the fast path here if there doesn't need to be an unaligned
553    // trap later
554    if (!unaligned) {
555        if (hpriv && implicit) {
556            req->setPaddr(vaddr & PAddrImplMask);
557            return NoFault;
558        }
559
560        // Be fast if we can!
561        if (cacheValid &&  cacheState == tlbdata) {
562
563
564
565            if (cacheEntry[0]) {
566                TlbEntry *ce = cacheEntry[0];
567                Addr ce_va = ce->range.va;
568                if (cacheAsi[0] == asi &&
569                    ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
570                    (!write || ce->pte.writable())) {
571                    req->setPaddr(ce->pte.translate(vaddr));
572                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
573                        req->setFlags(Request::UNCACHEABLE);
574                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
575                    return NoFault;
576                } // if matched
577            } // if cache entry valid
578            if (cacheEntry[1]) {
579                TlbEntry *ce = cacheEntry[1];
580                Addr ce_va = ce->range.va;
581                if (cacheAsi[1] == asi &&
582                    ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
583                    (!write || ce->pte.writable())) {
584                    req->setPaddr(ce->pte.translate(vaddr));
585                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
586                        req->setFlags(Request::UNCACHEABLE);
587                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
588                    return NoFault;
589                } // if matched
590            } // if cache entry valid
591        }
592    }
593
594    bool red = bits(tlbdata,1,1);
595    bool priv = bits(tlbdata,2,2);
596    bool addr_mask = bits(tlbdata,3,3);
597    bool lsu_dm = bits(tlbdata,5,5);
598
599    int part_id = bits(tlbdata,15,8);
600    int tl = bits(tlbdata,18,16);
601    int pri_context = bits(tlbdata,47,32);
602    int sec_context = bits(tlbdata,63,48);
603
604    bool real = false;
605    ContextType ct = Primary;
606    int context = 0;
607
608    TlbEntry *e;
609
610    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
611            priv, hpriv, red, lsu_dm, part_id);
612
613    if (implicit) {
614        if (tl > 0) {
615            asi = ASI_N;
616            ct = Nucleus;
617            context = 0;
618        } else {
619            asi = ASI_P;
620            ct = Primary;
621            context = pri_context;
622        }
623    } else {
624        // We need to check for priv level/asi priv
625        if (!priv && !hpriv && !asiIsUnPriv(asi)) {
626            // It appears that context should be Nucleus in these cases?
627            writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
628            return new PrivilegedAction;
629        }
630
631        if (!hpriv && asiIsHPriv(asi)) {
632            writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
633            return new DataAccessException;
634        }
635
636        if (asiIsPrimary(asi)) {
637            context = pri_context;
638            ct = Primary;
639        } else if (asiIsSecondary(asi)) {
640            context = sec_context;
641            ct = Secondary;
642        } else if (asiIsNucleus(asi)) {
643            ct = Nucleus;
644            context = 0;
645        } else {  // ????
646            ct = Primary;
647            context = pri_context;
648        }
649    }
650
651    if (!implicit && asi != ASI_P && asi != ASI_S) {
652        if (asiIsLittle(asi))
653            panic("Little Endian ASIs not supported\n");
654
655        //XXX It's unclear from looking at the documentation how a no fault
656        // load differs from a regular one, other than what happens concerning
657        // nfo and e bits in the TTE
658//        if (asiIsNoFault(asi))
659//            panic("No Fault ASIs not supported\n");
660
661        if (asiIsPartialStore(asi))
662            panic("Partial Store ASIs not supported\n");
663
664        if (asiIsCmt(asi))
665            panic("Cmt ASI registers not implmented\n");
666
667        if (asiIsInterrupt(asi))
668            goto handleIntRegAccess;
669        if (asiIsMmu(asi))
670            goto handleMmuRegAccess;
671        if (asiIsScratchPad(asi))
672            goto handleScratchRegAccess;
673        if (asiIsQueue(asi))
674            goto handleQueueRegAccess;
675        if (asiIsSparcError(asi))
676            goto handleSparcErrorRegAccess;
677
678        if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
679                !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
680            panic("Accessing ASI %#X. Should we?\n", asi);
681    }
682
683    // If the asi is unaligned trap
684    if (unaligned) {
685        writeSfsr(vaddr, false, ct, false, OtherFault, asi);
686        return new MemAddressNotAligned;
687    }
688
689    if (addr_mask)
690        vaddr = vaddr & VAddrAMask;
691
692    if (!validVirtualAddress(vaddr, addr_mask)) {
693        writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
694        return new DataAccessException;
695    }
696
697    if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
698        real = true;
699        context = 0;
700    }
701
702    if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
703        req->setPaddr(vaddr & PAddrImplMask);
704        return NoFault;
705    }
706
707    e = lookup(vaddr, part_id, real, context);
708
709    if (e == NULL || !e->valid) {
710        writeTagAccess(vaddr, context);
711        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
712        if (real)
713            return new DataRealTranslationMiss;
714        else
715#if FULL_SYSTEM
716            return new FastDataAccessMMUMiss;
717#else
718            return new FastDataAccessMMUMiss(req->getVaddr());
719#endif
720
721    }
722
723    if (!priv && e->pte.priv()) {
724        writeTagAccess(vaddr, context);
725        writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
726        return new DataAccessException;
727    }
728
729    if (write && !e->pte.writable()) {
730        writeTagAccess(vaddr, context);
731        writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
732        return new FastDataAccessProtection;
733    }
734
735    if (e->pte.nofault() && !asiIsNoFault(asi)) {
736        writeTagAccess(vaddr, context);
737        writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
738        return new DataAccessException;
739    }
740
741    if (e->pte.sideffect() && asiIsNoFault(asi)) {
742        writeTagAccess(vaddr, context);
743        writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
744        return new DataAccessException;
745    }
746
747    if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
748        req->setFlags(Request::UNCACHEABLE);
749
750    // cache translation date for next translation
751    cacheState = tlbdata;
752    if (!cacheValid) {
753        cacheEntry[1] = NULL;
754        cacheEntry[0] = NULL;
755    }
756
757    if (cacheEntry[0] != e && cacheEntry[1] != e) {
758        cacheEntry[1] = cacheEntry[0];
759        cacheEntry[0] = e;
760        cacheAsi[1] = cacheAsi[0];
761        cacheAsi[0] = asi;
762        if (implicit)
763            cacheAsi[0] = (ASI)0;
764    }
765    cacheValid = true;
766    req->setPaddr(e->pte.translate(vaddr));
767    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
768    return NoFault;
769
770    /** Normal flow ends here. */
771handleIntRegAccess:
772    if (!hpriv) {
773        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
774        if (priv)
775            return new DataAccessException;
776         else
777            return new PrivilegedAction;
778    }
779
780    if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
781        (asi == ASI_SWVR_UDB_INTR_R && write)) {
782        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
783        return new DataAccessException;
784    }
785
786    goto regAccessOk;
787
788
789handleScratchRegAccess:
790    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
791        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
792        return new DataAccessException;
793    }
794    goto regAccessOk;
795
796handleQueueRegAccess:
797    if (!priv  && !hpriv) {
798        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
799        return new PrivilegedAction;
800    }
801    if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
802        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
803        return new DataAccessException;
804    }
805    goto regAccessOk;
806
807handleSparcErrorRegAccess:
808    if (!hpriv) {
809        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
810        if (priv)
811            return new DataAccessException;
812         else
813            return new PrivilegedAction;
814    }
815    goto regAccessOk;
816
817
818regAccessOk:
819handleMmuRegAccess:
820    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
821    req->setFlags(Request::MMAPPED_IPR);
822    req->setPaddr(req->getVaddr());
823    return NoFault;
824};
825
826Fault
827TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
828{
829    if (mode == Execute)
830        return translateInst(req, tc);
831    else
832        return translateData(req, tc, mode == Write);
833}
834
835void
836TLB::translateTiming(RequestPtr req, ThreadContext *tc,
837        Translation *translation, Mode mode)
838{
839    assert(translation);
840    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
841}
842
843#if FULL_SYSTEM
844
845Tick
846TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
847{
848    Addr va = pkt->getAddr();
849    ASI asi = (ASI)pkt->req->getAsi();
850    uint64_t temp;
851
852    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
853         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
854
855    TLB *itb = tc->getITBPtr();
856
857    switch (asi) {
858      case ASI_LSU_CONTROL_REG:
859        assert(va == 0);
860        pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
861        break;
862      case ASI_MMU:
863        switch (va) {
864          case 0x8:
865            pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
866            break;
867          case 0x10:
868            pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
869            break;
870          default:
871            goto doMmuReadError;
872        }
873        break;
874      case ASI_QUEUE:
875        pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
876                    (va >> 4) - 0x3c));
877        break;
878      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
879        assert(va == 0);
880        pkt->set(c0_tsb_ps0);
881        break;
882      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
883        assert(va == 0);
884        pkt->set(c0_tsb_ps1);
885        break;
886      case ASI_DMMU_CTXT_ZERO_CONFIG:
887        assert(va == 0);
888        pkt->set(c0_config);
889        break;
890      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
891        assert(va == 0);
892        pkt->set(itb->c0_tsb_ps0);
893        break;
894      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
895        assert(va == 0);
896        pkt->set(itb->c0_tsb_ps1);
897        break;
898      case ASI_IMMU_CTXT_ZERO_CONFIG:
899        assert(va == 0);
900        pkt->set(itb->c0_config);
901        break;
902      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
903        assert(va == 0);
904        pkt->set(cx_tsb_ps0);
905        break;
906      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
907        assert(va == 0);
908        pkt->set(cx_tsb_ps1);
909        break;
910      case ASI_DMMU_CTXT_NONZERO_CONFIG:
911        assert(va == 0);
912        pkt->set(cx_config);
913        break;
914      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
915        assert(va == 0);
916        pkt->set(itb->cx_tsb_ps0);
917        break;
918      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
919        assert(va == 0);
920        pkt->set(itb->cx_tsb_ps1);
921        break;
922      case ASI_IMMU_CTXT_NONZERO_CONFIG:
923        assert(va == 0);
924        pkt->set(itb->cx_config);
925        break;
926      case ASI_SPARC_ERROR_STATUS_REG:
927        pkt->set((uint64_t)0);
928        break;
929      case ASI_HYP_SCRATCHPAD:
930      case ASI_SCRATCHPAD:
931        pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
932        break;
933      case ASI_IMMU:
934        switch (va) {
935          case 0x0:
936            temp = itb->tag_access;
937            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
938            break;
939          case 0x18:
940            pkt->set(itb->sfsr);
941            break;
942          case 0x30:
943            pkt->set(itb->tag_access);
944            break;
945          default:
946            goto doMmuReadError;
947        }
948        break;
949      case ASI_DMMU:
950        switch (va) {
951          case 0x0:
952            temp = tag_access;
953            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
954            break;
955          case 0x18:
956            pkt->set(sfsr);
957            break;
958          case 0x20:
959            pkt->set(sfar);
960            break;
961          case 0x30:
962            pkt->set(tag_access);
963            break;
964          case 0x80:
965            pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
966            break;
967          default:
968                goto doMmuReadError;
969        }
970        break;
971      case ASI_DMMU_TSB_PS0_PTR_REG:
972        pkt->set(MakeTsbPtr(Ps0,
973            tag_access,
974            c0_tsb_ps0,
975            c0_config,
976            cx_tsb_ps0,
977            cx_config));
978        break;
979      case ASI_DMMU_TSB_PS1_PTR_REG:
980        pkt->set(MakeTsbPtr(Ps1,
981                tag_access,
982                c0_tsb_ps1,
983                c0_config,
984                cx_tsb_ps1,
985                cx_config));
986        break;
987      case ASI_IMMU_TSB_PS0_PTR_REG:
988          pkt->set(MakeTsbPtr(Ps0,
989                itb->tag_access,
990                itb->c0_tsb_ps0,
991                itb->c0_config,
992                itb->cx_tsb_ps0,
993                itb->cx_config));
994        break;
995      case ASI_IMMU_TSB_PS1_PTR_REG:
996          pkt->set(MakeTsbPtr(Ps1,
997                itb->tag_access,
998                itb->c0_tsb_ps1,
999                itb->c0_config,
1000                itb->cx_tsb_ps1,
1001                itb->cx_config));
1002        break;
1003      case ASI_SWVR_INTR_RECEIVE:
1004        {
1005            SparcISA::Interrupts * interrupts =
1006                dynamic_cast<SparcISA::Interrupts *>(
1007                        tc->getCpuPtr()->getInterruptController());
1008            pkt->set(interrupts->get_vec(IT_INT_VEC));
1009        }
1010        break;
1011      case ASI_SWVR_UDB_INTR_R:
1012        {
1013            SparcISA::Interrupts * interrupts =
1014                dynamic_cast<SparcISA::Interrupts *>(
1015                        tc->getCpuPtr()->getInterruptController());
1016            temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1017            tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
1018            pkt->set(temp);
1019        }
1020        break;
1021      default:
1022doMmuReadError:
1023        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1024            (uint32_t)asi, va);
1025    }
1026    pkt->makeAtomicResponse();
1027    return tc->getCpuPtr()->ticks(1);
1028}
1029
1030Tick
1031TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1032{
1033    uint64_t data = pkt->get<uint64_t>();
1034    Addr va = pkt->getAddr();
1035    ASI asi = (ASI)pkt->req->getAsi();
1036
1037    Addr ta_insert;
1038    Addr va_insert;
1039    Addr ct_insert;
1040    int part_insert;
1041    int entry_insert = -1;
1042    bool real_insert;
1043    bool ignore;
1044    int part_id;
1045    int ctx_id;
1046    PageTableEntry pte;
1047
1048    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1049         (uint32_t)asi, va, data);
1050
1051    TLB *itb = tc->getITBPtr();
1052
1053    switch (asi) {
1054      case ASI_LSU_CONTROL_REG:
1055        assert(va == 0);
1056        tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1057        break;
1058      case ASI_MMU:
1059        switch (va) {
1060          case 0x8:
1061            tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1062            break;
1063          case 0x10:
1064            tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1065            break;
1066          default:
1067            goto doMmuWriteError;
1068        }
1069        break;
1070      case ASI_QUEUE:
1071        assert(mbits(data,13,6) == data);
1072        tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1073                    (va >> 4) - 0x3c, data);
1074        break;
1075      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1076        assert(va == 0);
1077        c0_tsb_ps0 = data;
1078        break;
1079      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1080        assert(va == 0);
1081        c0_tsb_ps1 = data;
1082        break;
1083      case ASI_DMMU_CTXT_ZERO_CONFIG:
1084        assert(va == 0);
1085        c0_config = data;
1086        break;
1087      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1088        assert(va == 0);
1089        itb->c0_tsb_ps0 = data;
1090        break;
1091      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1092        assert(va == 0);
1093        itb->c0_tsb_ps1 = data;
1094        break;
1095      case ASI_IMMU_CTXT_ZERO_CONFIG:
1096        assert(va == 0);
1097        itb->c0_config = data;
1098        break;
1099      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1100        assert(va == 0);
1101        cx_tsb_ps0 = data;
1102        break;
1103      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1104        assert(va == 0);
1105        cx_tsb_ps1 = data;
1106        break;
1107      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1108        assert(va == 0);
1109        cx_config = data;
1110        break;
1111      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1112        assert(va == 0);
1113        itb->cx_tsb_ps0 = data;
1114        break;
1115      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1116        assert(va == 0);
1117        itb->cx_tsb_ps1 = data;
1118        break;
1119      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1120        assert(va == 0);
1121        itb->cx_config = data;
1122        break;
1123      case ASI_SPARC_ERROR_EN_REG:
1124      case ASI_SPARC_ERROR_STATUS_REG:
1125        inform("Ignoring write to SPARC ERROR regsiter\n");
1126        break;
1127      case ASI_HYP_SCRATCHPAD:
1128      case ASI_SCRATCHPAD:
1129        tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1130        break;
1131      case ASI_IMMU:
1132        switch (va) {
1133          case 0x18:
1134            itb->sfsr = data;
1135            break;
1136          case 0x30:
1137            sext<59>(bits(data, 59,0));
1138            itb->tag_access = data;
1139            break;
1140          default:
1141            goto doMmuWriteError;
1142        }
1143        break;
1144      case ASI_ITLB_DATA_ACCESS_REG:
1145        entry_insert = bits(va, 8,3);
1146      case ASI_ITLB_DATA_IN_REG:
1147        assert(entry_insert != -1 || mbits(va,10,9) == va);
1148        ta_insert = itb->tag_access;
1149        va_insert = mbits(ta_insert, 63,13);
1150        ct_insert = mbits(ta_insert, 12,0);
1151        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1152        real_insert = bits(va, 9,9);
1153        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1154                PageTableEntry::sun4u);
1155        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1156                pte, entry_insert);
1157        break;
1158      case ASI_DTLB_DATA_ACCESS_REG:
1159        entry_insert = bits(va, 8,3);
1160      case ASI_DTLB_DATA_IN_REG:
1161        assert(entry_insert != -1 || mbits(va,10,9) == va);
1162        ta_insert = tag_access;
1163        va_insert = mbits(ta_insert, 63,13);
1164        ct_insert = mbits(ta_insert, 12,0);
1165        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1166        real_insert = bits(va, 9,9);
1167        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1168                PageTableEntry::sun4u);
1169        insert(va_insert, part_insert, ct_insert, real_insert, pte,
1170               entry_insert);
1171        break;
1172      case ASI_IMMU_DEMAP:
1173        ignore = false;
1174        ctx_id = -1;
1175        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1176        switch (bits(va,5,4)) {
1177          case 0:
1178            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1179            break;
1180          case 1:
1181            ignore = true;
1182            break;
1183          case 3:
1184            ctx_id = 0;
1185            break;
1186          default:
1187            ignore = true;
1188        }
1189
1190        switch (bits(va,7,6)) {
1191          case 0: // demap page
1192            if (!ignore)
1193                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1194                        bits(va,9,9), ctx_id);
1195            break;
1196          case 1: // demap context
1197            if (!ignore)
1198                tc->getITBPtr()->demapContext(part_id, ctx_id);
1199            break;
1200          case 2:
1201            tc->getITBPtr()->demapAll(part_id);
1202            break;
1203          default:
1204            panic("Invalid type for IMMU demap\n");
1205        }
1206        break;
1207      case ASI_DMMU:
1208        switch (va) {
1209          case 0x18:
1210            sfsr = data;
1211            break;
1212          case 0x30:
1213            sext<59>(bits(data, 59,0));
1214            tag_access = data;
1215            break;
1216          case 0x80:
1217            tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1218            break;
1219          default:
1220            goto doMmuWriteError;
1221        }
1222        break;
1223      case ASI_DMMU_DEMAP:
1224        ignore = false;
1225        ctx_id = -1;
1226        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1227        switch (bits(va,5,4)) {
1228          case 0:
1229            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1230            break;
1231          case 1:
1232            ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1233            break;
1234          case 3:
1235            ctx_id = 0;
1236            break;
1237          default:
1238            ignore = true;
1239        }
1240
1241        switch (bits(va,7,6)) {
1242          case 0: // demap page
1243            if (!ignore)
1244                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1245            break;
1246          case 1: // demap context
1247            if (!ignore)
1248                demapContext(part_id, ctx_id);
1249            break;
1250          case 2:
1251            demapAll(part_id);
1252            break;
1253          default:
1254            panic("Invalid type for IMMU demap\n");
1255        }
1256        break;
1257       case ASI_SWVR_INTR_RECEIVE:
1258        {
1259            int msb;
1260            // clear all the interrupts that aren't set in the write
1261            SparcISA::Interrupts * interrupts =
1262                dynamic_cast<SparcISA::Interrupts *>(
1263                        tc->getCpuPtr()->getInterruptController());
1264            while (interrupts->get_vec(IT_INT_VEC) & data) {
1265                msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1266                tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
1267            }
1268        }
1269        break;
1270      case ASI_SWVR_UDB_INTR_W:
1271            tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1272            postInterrupt(bits(data, 5, 0), 0);
1273        break;
1274      default:
1275doMmuWriteError:
1276        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1277            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1278    }
1279    pkt->makeAtomicResponse();
1280    return tc->getCpuPtr()->ticks(1);
1281}
1282
1283#endif
1284
1285void
1286TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1287{
1288    uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1289    TLB * itb = tc->getITBPtr();
1290    ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1291                c0_tsb_ps0,
1292                c0_config,
1293                cx_tsb_ps0,
1294                cx_config);
1295    ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1296                c0_tsb_ps1,
1297                c0_config,
1298                cx_tsb_ps1,
1299                cx_config);
1300    ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1301                itb->c0_tsb_ps0,
1302                itb->c0_config,
1303                itb->cx_tsb_ps0,
1304                itb->cx_config);
1305    ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1306                itb->c0_tsb_ps1,
1307                itb->c0_config,
1308                itb->cx_tsb_ps1,
1309                itb->cx_config);
1310}
1311
1312uint64_t
1313TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1314        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1315{
1316    uint64_t tsb;
1317    uint64_t config;
1318
1319    if (bits(tag_access, 12,0) == 0) {
1320        tsb = c0_tsb;
1321        config = c0_config;
1322    } else {
1323        tsb = cX_tsb;
1324        config = cX_config;
1325    }
1326
1327    uint64_t ptr = mbits(tsb,63,13);
1328    bool split = bits(tsb,12,12);
1329    int tsb_size = bits(tsb,3,0);
1330    int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1331
1332    if (ps == Ps1  && split)
1333        ptr |= ULL(1) << (13 + tsb_size);
1334    ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1335
1336    return ptr;
1337}
1338
1339void
1340TLB::serialize(std::ostream &os)
1341{
1342    SERIALIZE_SCALAR(size);
1343    SERIALIZE_SCALAR(usedEntries);
1344    SERIALIZE_SCALAR(lastReplaced);
1345
1346    // convert the pointer based free list into an index based one
1347    int *free_list = (int*)malloc(sizeof(int) * size);
1348    int cntr = 0;
1349    std::list<TlbEntry*>::iterator i;
1350    i = freeList.begin();
1351    while (i != freeList.end()) {
1352        free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1353        i++;
1354    }
1355    SERIALIZE_SCALAR(cntr);
1356    SERIALIZE_ARRAY(free_list,  cntr);
1357
1358    SERIALIZE_SCALAR(c0_tsb_ps0);
1359    SERIALIZE_SCALAR(c0_tsb_ps1);
1360    SERIALIZE_SCALAR(c0_config);
1361    SERIALIZE_SCALAR(cx_tsb_ps0);
1362    SERIALIZE_SCALAR(cx_tsb_ps1);
1363    SERIALIZE_SCALAR(cx_config);
1364    SERIALIZE_SCALAR(sfsr);
1365    SERIALIZE_SCALAR(tag_access);
1366
1367    for (int x = 0; x < size; x++) {
1368        nameOut(os, csprintf("%s.PTE%d", name(), x));
1369        tlb[x].serialize(os);
1370    }
1371    SERIALIZE_SCALAR(sfar);
1372}
1373
1374void
1375TLB::unserialize(Checkpoint *cp, const std::string &section)
1376{
1377    int oldSize;
1378
1379    paramIn(cp, section, "size", oldSize);
1380    if (oldSize != size)
1381        panic("Don't support unserializing different sized TLBs\n");
1382    UNSERIALIZE_SCALAR(usedEntries);
1383    UNSERIALIZE_SCALAR(lastReplaced);
1384
1385    int cntr;
1386    UNSERIALIZE_SCALAR(cntr);
1387
1388    int *free_list = (int*)malloc(sizeof(int) * cntr);
1389    freeList.clear();
1390    UNSERIALIZE_ARRAY(free_list,  cntr);
1391    for (int x = 0; x < cntr; x++)
1392        freeList.push_back(&tlb[free_list[x]]);
1393
1394    UNSERIALIZE_SCALAR(c0_tsb_ps0);
1395    UNSERIALIZE_SCALAR(c0_tsb_ps1);
1396    UNSERIALIZE_SCALAR(c0_config);
1397    UNSERIALIZE_SCALAR(cx_tsb_ps0);
1398    UNSERIALIZE_SCALAR(cx_tsb_ps1);
1399    UNSERIALIZE_SCALAR(cx_config);
1400    UNSERIALIZE_SCALAR(sfsr);
1401    UNSERIALIZE_SCALAR(tag_access);
1402
1403    lookupTable.clear();
1404    for (int x = 0; x < size; x++) {
1405        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1406        if (tlb[x].valid)
1407            lookupTable.insert(tlb[x].range, &tlb[x]);
1408
1409    }
1410    UNSERIALIZE_SCALAR(sfar);
1411}
1412
1413} // namespace SparcISA
1414
1415SparcISA::TLB *
1416SparcTLBParams::create()
1417{
1418    return new SparcISA::TLB(this);
1419}
1420