tlb.cc revision 4088 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
42#include "sim/builder.hh"
43
44/* @todo remove some of the magic constants.  -- ali
45 * */
46namespace SparcISA {
47
48TLB::TLB(const std::string &name, int s)
49    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
50      cacheValid(false)
51{
52    // To make this work you'll have to change the hypervisor and OS
53    if (size > 64)
54        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
55
56    tlb = new TlbEntry[size];
57    std::memset(tlb, 0, sizeof(TlbEntry) * size);
58
59    for (int x = 0; x < size; x++)
60        freeList.push_back(&tlb[x]);
61}
62
63void
64TLB::clearUsedBits()
65{
66    MapIter i;
67    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
68        TlbEntry *t = i->second;
69        if (!t->pte.locked()) {
70            t->used = false;
71            usedEntries--;
72        }
73    }
74}
75
76
77void
78TLB::insert(Addr va, int partition_id, int context_id, bool real,
79        const PageTableEntry& PTE, int entry)
80{
81
82
83    MapIter i;
84    TlbEntry *new_entry = NULL;
85//    TlbRange tr;
86    int x;
87
88    cacheValid = false;
89    va &= ~(PTE.size()-1);
90 /*   tr.va = va;
91    tr.size = PTE.size() - 1;
92    tr.contextId = context_id;
93    tr.partitionId = partition_id;
94    tr.real = real;
95*/
96
97    DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
98            va, PTE.paddr(), partition_id, context_id, (int)real, entry);
99
100    // Demap any entry that conflicts
101    for (x = 0; x < size; x++) {
102        if (tlb[x].range.real == real &&
103            tlb[x].range.partitionId == partition_id &&
104            tlb[x].range.va < va + PTE.size() - 1 &&
105            tlb[x].range.va + tlb[x].range.size >= va &&
106            (real || tlb[x].range.contextId == context_id ))
107        {
108            if (tlb[x].valid) {
109                freeList.push_front(&tlb[x]);
110                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
111
112                tlb[x].valid = false;
113                if (tlb[x].used) {
114                    tlb[x].used = false;
115                    usedEntries--;
116                }
117                lookupTable.erase(tlb[x].range);
118            }
119        }
120    }
121
122
123/*
124    i = lookupTable.find(tr);
125    if (i != lookupTable.end()) {
126        i->second->valid = false;
127        if (i->second->used) {
128            i->second->used = false;
129            usedEntries--;
130        }
131        freeList.push_front(i->second);
132        DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
133                i->second);
134        lookupTable.erase(i);
135    }
136*/
137
138    if (entry != -1) {
139        assert(entry < size && entry >= 0);
140        new_entry = &tlb[entry];
141    } else {
142        if (!freeList.empty()) {
143            new_entry = freeList.front();
144        } else {
145            x = lastReplaced;
146            do {
147                ++x;
148                if (x == size)
149                    x = 0;
150                if (x == lastReplaced)
151                    goto insertAllLocked;
152            } while (tlb[x].pte.locked());
153            lastReplaced = x;
154            new_entry = &tlb[x];
155        }
156        /*
157        for (x = 0; x < size; x++) {
158            if (!tlb[x].valid || !tlb[x].used)  {
159                new_entry = &tlb[x];
160                break;
161            }
162        }*/
163    }
164
165insertAllLocked:
166    // Update the last ently if their all locked
167    if (!new_entry) {
168        new_entry = &tlb[size-1];
169    }
170
171    freeList.remove(new_entry);
172    if (new_entry->valid && new_entry->used)
173        usedEntries--;
174    if (new_entry->valid)
175        lookupTable.erase(new_entry->range);
176
177
178    assert(PTE.valid());
179    new_entry->range.va = va;
180    new_entry->range.size = PTE.size() - 1;
181    new_entry->range.partitionId = partition_id;
182    new_entry->range.contextId = context_id;
183    new_entry->range.real = real;
184    new_entry->pte = PTE;
185    new_entry->used = true;;
186    new_entry->valid = true;
187    usedEntries++;
188
189
190
191    i = lookupTable.insert(new_entry->range, new_entry);
192    assert(i != lookupTable.end());
193
194    // If all entries have there used bit set, clear it on them all, but the
195    // one we just inserted
196    if (usedEntries == size) {
197        clearUsedBits();
198        new_entry->used = true;
199        usedEntries++;
200    }
201
202}
203
204
205TlbEntry*
206TLB::lookup(Addr va, int partition_id, bool real, int context_id, bool
207        update_used)
208{
209    MapIter i;
210    TlbRange tr;
211    TlbEntry *t;
212
213    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214            va, partition_id, context_id, real);
215    // Assemble full address structure
216    tr.va = va;
217    tr.size = MachineBytes;
218    tr.contextId = context_id;
219    tr.partitionId = partition_id;
220    tr.real = real;
221
222    // Try to find the entry
223    i = lookupTable.find(tr);
224    if (i == lookupTable.end()) {
225        DPRINTF(TLB, "TLB: No valid entry found\n");
226        return NULL;
227    }
228
229    // Mark the entries used bit and clear other used bits in needed
230    t = i->second;
231    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
232            t->pte.size());
233
234    // Update the used bits only if this is a real access (not a fake one from
235    // virttophys()
236    if (!t->used && update_used) {
237        t->used = true;
238        usedEntries++;
239        if (usedEntries == size) {
240            clearUsedBits();
241            t->used = true;
242            usedEntries++;
243        }
244    }
245
246    return t;
247}
248
249void
250TLB::dumpAll()
251{
252    MapIter i;
253    for (int x = 0; x < size; x++) {
254        if (tlb[x].valid) {
255           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
256                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
257                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
258                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
259        }
260    }
261}
262
263void
264TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
265{
266    TlbRange tr;
267    MapIter i;
268
269    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
270            va, partition_id, context_id, real);
271
272    cacheValid = false;
273
274    // Assemble full address structure
275    tr.va = va;
276    tr.size = MachineBytes;
277    tr.contextId = context_id;
278    tr.partitionId = partition_id;
279    tr.real = real;
280
281    // Demap any entry that conflicts
282    i = lookupTable.find(tr);
283    if (i != lookupTable.end()) {
284        DPRINTF(IPR, "TLB: Demapped page\n");
285        i->second->valid = false;
286        if (i->second->used) {
287            i->second->used = false;
288            usedEntries--;
289        }
290        freeList.push_front(i->second);
291        lookupTable.erase(i);
292    }
293}
294
295void
296TLB::demapContext(int partition_id, int context_id)
297{
298    int x;
299    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
300            partition_id, context_id);
301    cacheValid = false;
302    for (x = 0; x < size; x++) {
303        if (tlb[x].range.contextId == context_id &&
304            tlb[x].range.partitionId == partition_id) {
305            if (tlb[x].valid == true) {
306                freeList.push_front(&tlb[x]);
307            }
308            tlb[x].valid = false;
309            if (tlb[x].used) {
310                tlb[x].used = false;
311                usedEntries--;
312            }
313            lookupTable.erase(tlb[x].range);
314        }
315    }
316}
317
318void
319TLB::demapAll(int partition_id)
320{
321    int x;
322    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
323    cacheValid = false;
324    for (x = 0; x < size; x++) {
325        if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
326            if (tlb[x].valid == true){
327                freeList.push_front(&tlb[x]);
328            }
329            tlb[x].valid = false;
330            if (tlb[x].used) {
331                tlb[x].used = false;
332                usedEntries--;
333            }
334            lookupTable.erase(tlb[x].range);
335        }
336    }
337}
338
339void
340TLB::invalidateAll()
341{
342    int x;
343    cacheValid = false;
344
345    freeList.clear();
346    lookupTable.clear();
347    for (x = 0; x < size; x++) {
348        if (tlb[x].valid == true)
349            freeList.push_back(&tlb[x]);
350        tlb[x].valid = false;
351        tlb[x].used = false;
352    }
353    usedEntries = 0;
354}
355
356uint64_t
357TLB::TteRead(int entry) {
358    if (entry >= size)
359        panic("entry: %d\n", entry);
360
361    assert(entry < size);
362    if (tlb[entry].valid)
363        return tlb[entry].pte();
364    else
365        return (uint64_t)-1ll;
366}
367
368uint64_t
369TLB::TagRead(int entry) {
370    assert(entry < size);
371    uint64_t tag;
372    if (!tlb[entry].valid)
373        return (uint64_t)-1ll;
374
375    tag = tlb[entry].range.contextId;
376    tag |= tlb[entry].range.va;
377    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
378    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
379    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
380    return tag;
381}
382
383bool
384TLB::validVirtualAddress(Addr va, bool am)
385{
386    if (am)
387        return true;
388    if (va >= StartVAddrHole && va <= EndVAddrHole)
389        return false;
390    return true;
391}
392
393void
394TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
395        bool se, FaultTypes ft, int asi)
396{
397    uint64_t sfsr;
398    sfsr = tc->readMiscReg(reg);
399
400    if (sfsr & 0x1)
401        sfsr = 0x3;
402    else
403        sfsr = 1;
404
405    if (write)
406        sfsr |= 1 << 2;
407    sfsr |= ct << 4;
408    if (se)
409        sfsr |= 1 << 6;
410    sfsr |= ft << 7;
411    sfsr |= asi << 16;
412    tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
418    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
419            va, context, mbits(va, 63,13) | mbits(context,12,0));
420
421    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422}
423
424void
425ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
426        bool se, FaultTypes ft, int asi)
427{
428    DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
429             (int)write, ct, ft, asi);
430    TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
431}
432
433void
434ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
435{
436    TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
437}
438
439void
440DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
441        bool se, FaultTypes ft, int asi)
442{
443    DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
444            a, (int)write, ct, ft, asi);
445    TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
446    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
447}
448
449void
450DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
451{
452    TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
453}
454
455
456
457Fault
458ITB::translate(RequestPtr &req, ThreadContext *tc)
459{
460    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
461
462    Addr vaddr = req->getVaddr();
463    TlbEntry *e;
464
465    assert(req->getAsi() == ASI_IMPLICIT);
466
467    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
468            vaddr, req->getSize());
469
470    // Be fast if we can!
471    if (cacheValid && cacheState == tlbdata) {
472        if (cacheEntry) {
473            if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
474                cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
475                    req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
476                                  vaddr & cacheEntry->pte.size()-1 );
477                    return NoFault;
478            }
479        } else {
480            req->setPaddr(vaddr & PAddrImplMask);
481            return NoFault;
482        }
483    }
484
485    bool hpriv = bits(tlbdata,0,0);
486    bool red = bits(tlbdata,1,1);
487    bool priv = bits(tlbdata,2,2);
488    bool addr_mask = bits(tlbdata,3,3);
489    bool lsu_im = bits(tlbdata,4,4);
490
491    int part_id = bits(tlbdata,15,8);
492    int tl = bits(tlbdata,18,16);
493    int pri_context = bits(tlbdata,47,32);
494    int context;
495    ContextType ct;
496    int asi;
497    bool real = false;
498
499    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
500           priv, hpriv, red, lsu_im, part_id);
501
502    if (tl > 0) {
503        asi = ASI_N;
504        ct = Nucleus;
505        context = 0;
506    } else {
507        asi = ASI_P;
508        ct = Primary;
509        context = pri_context;
510    }
511
512    if ( hpriv || red ) {
513        cacheValid = true;
514        cacheState = tlbdata;
515        cacheEntry = NULL;
516        req->setPaddr(vaddr & PAddrImplMask);
517        return NoFault;
518    }
519
520    // If the access is unaligned trap
521    if (vaddr & 0x3) {
522        writeSfsr(tc, false, ct, false, OtherFault, asi);
523        return new MemAddressNotAligned;
524    }
525
526    if (addr_mask)
527        vaddr = vaddr & VAddrAMask;
528
529    if (!validVirtualAddress(vaddr, addr_mask)) {
530        writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
531        return new InstructionAccessException;
532    }
533
534    if (!lsu_im) {
535        e = lookup(vaddr, part_id, true);
536        real = true;
537        context = 0;
538    } else {
539        e = lookup(vaddr, part_id, false, context);
540    }
541
542    if (e == NULL || !e->valid) {
543        writeTagAccess(tc, vaddr, context);
544        if (real)
545            return new InstructionRealTranslationMiss;
546        else
547            return new FastInstructionAccessMMUMiss;
548    }
549
550    // were not priviledged accesing priv page
551    if (!priv && e->pte.priv()) {
552        writeTagAccess(tc, vaddr, context);
553        writeSfsr(tc, false, ct, false, PrivViolation, asi);
554        return new InstructionAccessException;
555    }
556
557    // cache translation date for next translation
558    cacheValid = true;
559    cacheState = tlbdata;
560    cacheEntry = e;
561
562    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
563                  vaddr & e->pte.size()-1 );
564    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
565    return NoFault;
566}
567
568
569
570Fault
571DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
572{
573    /* @todo this could really use some profiling and fixing to make it faster! */
574    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
575    Addr vaddr = req->getVaddr();
576    Addr size = req->getSize();
577    ASI asi;
578    asi = (ASI)req->getAsi();
579    bool implicit = false;
580    bool hpriv = bits(tlbdata,0,0);
581
582    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
583            vaddr, size, asi);
584
585    if (lookupTable.size() != 64 - freeList.size())
586       panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
587               freeList.size());
588    if (asi == ASI_IMPLICIT)
589        implicit = true;
590
591    if (hpriv && implicit) {
592        req->setPaddr(vaddr & PAddrImplMask);
593        return NoFault;
594    }
595
596    // Be fast if we can!
597    if (cacheValid &&  cacheState == tlbdata) {
598        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
599            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
600            (!write || cacheEntry[0]->pte.writable())) {
601                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
602                              vaddr & cacheEntry[0]->pte.size()-1 );
603                return NoFault;
604        }
605        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
606            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
607            (!write || cacheEntry[1]->pte.writable())) {
608                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
609                              vaddr & cacheEntry[1]->pte.size()-1 );
610                return NoFault;
611        }
612    }
613
614    bool red = bits(tlbdata,1,1);
615    bool priv = bits(tlbdata,2,2);
616    bool addr_mask = bits(tlbdata,3,3);
617    bool lsu_dm = bits(tlbdata,5,5);
618
619    int part_id = bits(tlbdata,15,8);
620    int tl = bits(tlbdata,18,16);
621    int pri_context = bits(tlbdata,47,32);
622    int sec_context = bits(tlbdata,63,48);
623
624    bool real = false;
625    ContextType ct = Primary;
626    int context = 0;
627
628    TlbEntry *e;
629
630    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
631           priv, hpriv, red, lsu_dm, part_id);
632
633    if (implicit) {
634        if (tl > 0) {
635            asi = ASI_N;
636            ct = Nucleus;
637            context = 0;
638        } else {
639            asi = ASI_P;
640            ct = Primary;
641            context = pri_context;
642        }
643    } else {
644        // We need to check for priv level/asi priv
645        if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
646            // It appears that context should be Nucleus in these cases?
647            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
648            return new PrivilegedAction;
649        }
650
651        if (!hpriv && AsiIsHPriv(asi)) {
652            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
653            return new DataAccessException;
654        }
655
656        if (AsiIsPrimary(asi)) {
657            context = pri_context;
658            ct = Primary;
659        } else if (AsiIsSecondary(asi)) {
660            context = sec_context;
661            ct = Secondary;
662        } else if (AsiIsNucleus(asi)) {
663            ct = Nucleus;
664            context = 0;
665        } else {  // ????
666            ct = Primary;
667            context = pri_context;
668        }
669    }
670
671    if (!implicit && asi != ASI_P && asi != ASI_S) {
672        if (AsiIsLittle(asi))
673            panic("Little Endian ASIs not supported\n");
674        if (AsiIsNoFault(asi))
675            panic("No Fault ASIs not supported\n");
676
677        if (AsiIsPartialStore(asi))
678            panic("Partial Store ASIs not supported\n");
679        if (AsiIsInterrupt(asi))
680            panic("Interrupt ASIs not supported\n");
681
682        if (AsiIsMmu(asi))
683            goto handleMmuRegAccess;
684        if (AsiIsScratchPad(asi))
685            goto handleScratchRegAccess;
686        if (AsiIsQueue(asi))
687            goto handleQueueRegAccess;
688        if (AsiIsSparcError(asi))
689            goto handleSparcErrorRegAccess;
690
691        if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
692                !AsiIsTwin(asi) && !AsiIsBlock(asi))
693            panic("Accessing ASI %#X. Should we?\n", asi);
694    }
695
696    // If the asi is unaligned trap
697    if (vaddr & size-1) {
698        writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
699        return new MemAddressNotAligned;
700    }
701
702    if (addr_mask)
703        vaddr = vaddr & VAddrAMask;
704
705    if (!validVirtualAddress(vaddr, addr_mask)) {
706        writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
707        return new DataAccessException;
708    }
709
710
711    if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
712        real = true;
713        context = 0;
714    };
715
716    if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
717        req->setPaddr(vaddr & PAddrImplMask);
718        return NoFault;
719    }
720
721    e = lookup(vaddr, part_id, real, context);
722
723    if (e == NULL || !e->valid) {
724        writeTagAccess(tc, vaddr, context);
725        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
726        if (real)
727            return new DataRealTranslationMiss;
728        else
729            return new FastDataAccessMMUMiss;
730
731    }
732
733    if (!priv && e->pte.priv()) {
734        writeTagAccess(tc, vaddr, context);
735        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
736        return new DataAccessException;
737    }
738
739    if (write && !e->pte.writable()) {
740        writeTagAccess(tc, vaddr, context);
741        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
742        return new FastDataAccessProtection;
743    }
744
745    if (e->pte.nofault() && !AsiIsNoFault(asi)) {
746        writeTagAccess(tc, vaddr, context);
747        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
748        return new DataAccessException;
749    }
750
751    if (e->pte.sideffect() && AsiIsNoFault(asi)) {
752        writeTagAccess(tc, vaddr, context);
753        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
754        return new DataAccessException;
755    }
756
757
758    if (e->pte.sideffect())
759        req->setFlags(req->getFlags() | UNCACHEABLE);
760
761    // cache translation date for next translation
762    cacheState = tlbdata;
763    if (!cacheValid) {
764        cacheEntry[1] = NULL;
765        cacheEntry[0] = NULL;
766    }
767
768    if (cacheEntry[0] != e && cacheEntry[1] != e) {
769        cacheEntry[1] = cacheEntry[0];
770        cacheEntry[0] = e;
771        cacheAsi[1] = cacheAsi[0];
772        cacheAsi[0] = asi;
773        if (implicit)
774            cacheAsi[0] = (ASI)0;
775    }
776    cacheValid = true;
777    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
778                  vaddr & e->pte.size()-1);
779    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
780    return NoFault;
781    /** Normal flow ends here. */
782
783handleScratchRegAccess:
784    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
785        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
786        return new DataAccessException;
787    }
788    goto regAccessOk;
789
790handleQueueRegAccess:
791    if (!priv  && !hpriv) {
792        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
793        return new PrivilegedAction;
794    }
795    if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
796        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
797        return new DataAccessException;
798    }
799    goto regAccessOk;
800
801handleSparcErrorRegAccess:
802    if (!hpriv) {
803        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
804        if (priv)
805            return new DataAccessException;
806         else
807            return new PrivilegedAction;
808    }
809    goto regAccessOk;
810
811
812regAccessOk:
813handleMmuRegAccess:
814    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
815    req->setMmapedIpr(true);
816    req->setPaddr(req->getVaddr());
817    return NoFault;
818};
819
820Tick
821DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
822{
823    Addr va = pkt->getAddr();
824    ASI asi = (ASI)pkt->req->getAsi();
825    uint64_t temp;
826
827    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
828         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
829
830    switch (asi) {
831      case ASI_LSU_CONTROL_REG:
832        assert(va == 0);
833        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
834        break;
835      case ASI_MMU:
836        switch (va) {
837          case 0x8:
838            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
839            break;
840          case 0x10:
841            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
842            break;
843          default:
844            goto doMmuReadError;
845        }
846        break;
847      case ASI_QUEUE:
848        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
849                    (va >> 4) - 0x3c));
850        break;
851      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
852        assert(va == 0);
853        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
854        break;
855      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
856        assert(va == 0);
857        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
858        break;
859      case ASI_DMMU_CTXT_ZERO_CONFIG:
860        assert(va == 0);
861        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
862        break;
863      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
864        assert(va == 0);
865        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
866        break;
867      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
868        assert(va == 0);
869        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
870        break;
871      case ASI_IMMU_CTXT_ZERO_CONFIG:
872        assert(va == 0);
873        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
874        break;
875      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
876        assert(va == 0);
877        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
878        break;
879      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
880        assert(va == 0);
881        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
882        break;
883      case ASI_DMMU_CTXT_NONZERO_CONFIG:
884        assert(va == 0);
885        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
886        break;
887      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
888        assert(va == 0);
889        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
890        break;
891      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
892        assert(va == 0);
893        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
894        break;
895      case ASI_IMMU_CTXT_NONZERO_CONFIG:
896        assert(va == 0);
897        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
898        break;
899      case ASI_SPARC_ERROR_STATUS_REG:
900        pkt->set((uint64_t)0);
901        break;
902      case ASI_HYP_SCRATCHPAD:
903      case ASI_SCRATCHPAD:
904        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
905        break;
906      case ASI_IMMU:
907        switch (va) {
908          case 0x0:
909            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
910            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
911            break;
912          case 0x18:
913            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
914            break;
915          case 0x30:
916            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
917            break;
918          default:
919            goto doMmuReadError;
920        }
921        break;
922      case ASI_DMMU:
923        switch (va) {
924          case 0x0:
925            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
926            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
927            break;
928          case 0x18:
929            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
930            break;
931          case 0x20:
932            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
933            break;
934          case 0x30:
935            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
936            break;
937          case 0x80:
938            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
939            break;
940          default:
941                goto doMmuReadError;
942        }
943        break;
944      case ASI_DMMU_TSB_PS0_PTR_REG:
945        pkt->set(MakeTsbPtr(Ps0,
946            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
947            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
948            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
949            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
950            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
951        break;
952      case ASI_DMMU_TSB_PS1_PTR_REG:
953        pkt->set(MakeTsbPtr(Ps1,
954                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
955                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
956                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
957                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
958                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
959        break;
960      case ASI_IMMU_TSB_PS0_PTR_REG:
961          pkt->set(MakeTsbPtr(Ps0,
962                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
963                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
964                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
965                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
966                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
967        break;
968      case ASI_IMMU_TSB_PS1_PTR_REG:
969          pkt->set(MakeTsbPtr(Ps1,
970                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
971                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
972                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
973                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
974                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
975        break;
976
977      default:
978doMmuReadError:
979        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
980            (uint32_t)asi, va);
981    }
982    pkt->result = Packet::Success;
983    return tc->getCpuPtr()->cycles(1);
984}
985
986Tick
987DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
988{
989    uint64_t data = gtoh(pkt->get<uint64_t>());
990    Addr va = pkt->getAddr();
991    ASI asi = (ASI)pkt->req->getAsi();
992
993    Addr ta_insert;
994    Addr va_insert;
995    Addr ct_insert;
996    int part_insert;
997    int entry_insert = -1;
998    bool real_insert;
999    bool ignore;
1000    int part_id;
1001    int ctx_id;
1002    PageTableEntry pte;
1003
1004    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1005         (uint32_t)asi, va, data);
1006
1007    switch (asi) {
1008      case ASI_LSU_CONTROL_REG:
1009        assert(va == 0);
1010        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1011        break;
1012      case ASI_MMU:
1013        switch (va) {
1014          case 0x8:
1015            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1016            break;
1017          case 0x10:
1018            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1019            break;
1020          default:
1021            goto doMmuWriteError;
1022        }
1023        break;
1024      case ASI_QUEUE:
1025        assert(mbits(data,13,6) == data);
1026        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1027                    (va >> 4) - 0x3c, data);
1028        break;
1029      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1030        assert(va == 0);
1031        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1032        break;
1033      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1034        assert(va == 0);
1035        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1036        break;
1037      case ASI_DMMU_CTXT_ZERO_CONFIG:
1038        assert(va == 0);
1039        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1040        break;
1041      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1042        assert(va == 0);
1043        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1044        break;
1045      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1046        assert(va == 0);
1047        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1048        break;
1049      case ASI_IMMU_CTXT_ZERO_CONFIG:
1050        assert(va == 0);
1051        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1052        break;
1053      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1054        assert(va == 0);
1055        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1056        break;
1057      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1058        assert(va == 0);
1059        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1060        break;
1061      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1062        assert(va == 0);
1063        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1064        break;
1065      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1066        assert(va == 0);
1067        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1068        break;
1069      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1070        assert(va == 0);
1071        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1072        break;
1073      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1074        assert(va == 0);
1075        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1076        break;
1077      case ASI_SPARC_ERROR_EN_REG:
1078      case ASI_SPARC_ERROR_STATUS_REG:
1079        warn("Ignoring write to SPARC ERROR regsiter\n");
1080        break;
1081      case ASI_HYP_SCRATCHPAD:
1082      case ASI_SCRATCHPAD:
1083        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1084        break;
1085      case ASI_IMMU:
1086        switch (va) {
1087          case 0x18:
1088            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1089            break;
1090          case 0x30:
1091            sext<59>(bits(data, 59,0));
1092            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1093            break;
1094          default:
1095            goto doMmuWriteError;
1096        }
1097        break;
1098      case ASI_ITLB_DATA_ACCESS_REG:
1099        entry_insert = bits(va, 8,3);
1100      case ASI_ITLB_DATA_IN_REG:
1101        assert(entry_insert != -1 || mbits(va,10,9) == va);
1102        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1103        va_insert = mbits(ta_insert, 63,13);
1104        ct_insert = mbits(ta_insert, 12,0);
1105        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1106        real_insert = bits(va, 9,9);
1107        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1108                PageTableEntry::sun4u);
1109        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1110                pte, entry_insert);
1111        break;
1112      case ASI_DTLB_DATA_ACCESS_REG:
1113        entry_insert = bits(va, 8,3);
1114      case ASI_DTLB_DATA_IN_REG:
1115        assert(entry_insert != -1 || mbits(va,10,9) == va);
1116        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1117        va_insert = mbits(ta_insert, 63,13);
1118        ct_insert = mbits(ta_insert, 12,0);
1119        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1120        real_insert = bits(va, 9,9);
1121        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1122                PageTableEntry::sun4u);
1123        insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1124        break;
1125      case ASI_IMMU_DEMAP:
1126        ignore = false;
1127        ctx_id = -1;
1128        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1129        switch (bits(va,5,4)) {
1130          case 0:
1131            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1132            break;
1133          case 1:
1134            ignore = true;
1135            break;
1136          case 3:
1137            ctx_id = 0;
1138            break;
1139          default:
1140            ignore = true;
1141        }
1142
1143        switch(bits(va,7,6)) {
1144          case 0: // demap page
1145            if (!ignore)
1146                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1147                        bits(va,9,9), ctx_id);
1148            break;
1149          case 1: //demap context
1150            if (!ignore)
1151                tc->getITBPtr()->demapContext(part_id, ctx_id);
1152            break;
1153          case 2:
1154            tc->getITBPtr()->demapAll(part_id);
1155            break;
1156          default:
1157            panic("Invalid type for IMMU demap\n");
1158        }
1159        break;
1160      case ASI_DMMU:
1161        switch (va) {
1162          case 0x18:
1163            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1164            break;
1165          case 0x30:
1166            sext<59>(bits(data, 59,0));
1167            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1168            break;
1169          case 0x80:
1170            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1171            break;
1172          default:
1173            goto doMmuWriteError;
1174        }
1175        break;
1176      case ASI_DMMU_DEMAP:
1177        ignore = false;
1178        ctx_id = -1;
1179        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1180        switch (bits(va,5,4)) {
1181          case 0:
1182            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1183            break;
1184          case 1:
1185            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1186            break;
1187          case 3:
1188            ctx_id = 0;
1189            break;
1190          default:
1191            ignore = true;
1192        }
1193
1194        switch(bits(va,7,6)) {
1195          case 0: // demap page
1196            if (!ignore)
1197                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1198            break;
1199          case 1: //demap context
1200            if (!ignore)
1201                demapContext(part_id, ctx_id);
1202            break;
1203          case 2:
1204            demapAll(part_id);
1205            break;
1206          default:
1207            panic("Invalid type for IMMU demap\n");
1208        }
1209        break;
1210      default:
1211doMmuWriteError:
1212        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1213            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1214    }
1215    pkt->result = Packet::Success;
1216    return tc->getCpuPtr()->cycles(1);
1217}
1218
1219void
1220DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1221{
1222    uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1223    ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1224                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
1225                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
1226                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
1227                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
1228    ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1229                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
1230                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
1231                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
1232                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
1233    ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1234                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
1235                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1236                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
1237                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
1238    ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1239                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
1240                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1241                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
1242                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
1243}
1244
1245
1246
1247
1248
1249uint64_t
1250DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1251        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1252{
1253    uint64_t tsb;
1254    uint64_t config;
1255
1256    if (bits(tag_access, 12,0) == 0) {
1257        tsb = c0_tsb;
1258        config = c0_config;
1259    } else {
1260        tsb = cX_tsb;
1261        config = cX_config;
1262    }
1263
1264    uint64_t ptr = mbits(tsb,63,13);
1265    bool split = bits(tsb,12,12);
1266    int tsb_size = bits(tsb,3,0);
1267    int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1268
1269    if (ps == Ps1  && split)
1270        ptr |= ULL(1) << (13 + tsb_size);
1271    ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1272
1273    return ptr;
1274}
1275
1276
1277void
1278TLB::serialize(std::ostream &os)
1279{
1280    SERIALIZE_SCALAR(size);
1281    SERIALIZE_SCALAR(usedEntries);
1282    SERIALIZE_SCALAR(lastReplaced);
1283
1284    // convert the pointer based free list into an index based one
1285    int *free_list = (int*)malloc(sizeof(int) * size);
1286    int cntr = 0;
1287    std::list<TlbEntry*>::iterator i;
1288    i = freeList.begin();
1289    while (i != freeList.end()) {
1290        free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1291        i++;
1292    }
1293    SERIALIZE_SCALAR(cntr);
1294    SERIALIZE_ARRAY(free_list,  cntr);
1295
1296    for (int x = 0; x < size; x++) {
1297        nameOut(os, csprintf("%s.PTE%d", name(), x));
1298        tlb[x].serialize(os);
1299    }
1300}
1301
1302void
1303TLB::unserialize(Checkpoint *cp, const std::string &section)
1304{
1305    int oldSize;
1306
1307    paramIn(cp, section, "size", oldSize);
1308    if (oldSize != size)
1309        panic("Don't support unserializing different sized TLBs\n");
1310    UNSERIALIZE_SCALAR(usedEntries);
1311    UNSERIALIZE_SCALAR(lastReplaced);
1312
1313    int cntr;
1314    UNSERIALIZE_SCALAR(cntr);
1315
1316    int *free_list = (int*)malloc(sizeof(int) * cntr);
1317    freeList.clear();
1318    UNSERIALIZE_ARRAY(free_list,  cntr);
1319    for (int x = 0; x < cntr; x++)
1320        freeList.push_back(&tlb[free_list[x]]);
1321
1322    lookupTable.clear();
1323    for (int x = 0; x < size; x++) {
1324        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1325        if (tlb[x].valid)
1326            lookupTable.insert(tlb[x].range, &tlb[x]);
1327
1328    }
1329}
1330
1331/* end namespace SparcISA */ }
1332
1333using namespace SparcISA;
1334
1335DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1336
1337BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1338
1339    Param<int> size;
1340
1341END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1342
1343BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1344
1345    INIT_PARAM_DFLT(size, "TLB size", 48)
1346
1347END_INIT_SIM_OBJECT_PARAMS(ITB)
1348
1349
1350CREATE_SIM_OBJECT(ITB)
1351{
1352    return new ITB(getInstanceName(), size);
1353}
1354
1355REGISTER_SIM_OBJECT("SparcITB", ITB)
1356
1357BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1358
1359    Param<int> size;
1360
1361END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1362
1363BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1364
1365    INIT_PARAM_DFLT(size, "TLB size", 64)
1366
1367END_INIT_SIM_OBJECT_PARAMS(DTB)
1368
1369
1370CREATE_SIM_OBJECT(DTB)
1371{
1372    return new DTB(getInstanceName(), size);
1373}
1374
1375REGISTER_SIM_OBJECT("SparcDTB", DTB)
1376