tlb.cc revision 4070:74449a198a44 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
42#include "sim/builder.hh"
43
44/* @todo remove some of the magic constants.  -- ali
45 * */
46namespace SparcISA
47{
48
49TLB::TLB(const std::string &name, int s)
50    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
51      cacheValid(false)
52{
53    // To make this work you'll have to change the hypervisor and OS
54    if (size > 64)
55        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
56
57    tlb = new TlbEntry[size];
58    std::memset(tlb, 0, sizeof(TlbEntry) * size);
59
60    for (int x = 0; x < size; x++)
61        freeList.push_back(&tlb[x]);
62}
63
64void
65TLB::clearUsedBits()
66{
67    MapIter i;
68    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
69        TlbEntry *t = i->second;
70        if (!t->pte.locked()) {
71            t->used = false;
72            usedEntries--;
73        }
74    }
75}
76
77
78void
79TLB::insert(Addr va, int partition_id, int context_id, bool real,
80        const PageTableEntry& PTE, int entry)
81{
82
83
84    MapIter i;
85    TlbEntry *new_entry = NULL;
86//    TlbRange tr;
87    int x;
88
89    cacheValid = false;
90    va &= ~(PTE.size()-1);
91 /*   tr.va = va;
92    tr.size = PTE.size() - 1;
93    tr.contextId = context_id;
94    tr.partitionId = partition_id;
95    tr.real = real;
96*/
97
98    DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
99            va, PTE.paddr(), partition_id, context_id, (int)real, entry);
100
101    // Demap any entry that conflicts
102    for (x = 0; x < size; x++) {
103        if (tlb[x].range.real == real &&
104            tlb[x].range.partitionId == partition_id &&
105            tlb[x].range.va < va + PTE.size() - 1 &&
106            tlb[x].range.va + tlb[x].range.size >= va &&
107            (real || tlb[x].range.contextId == context_id ))
108        {
109            if (tlb[x].valid) {
110                freeList.push_front(&tlb[x]);
111                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
112
113                tlb[x].valid = false;
114                if (tlb[x].used) {
115                    tlb[x].used = false;
116                    usedEntries--;
117                }
118                lookupTable.erase(tlb[x].range);
119            }
120        }
121    }
122
123
124/*
125    i = lookupTable.find(tr);
126    if (i != lookupTable.end()) {
127        i->second->valid = false;
128        if (i->second->used) {
129            i->second->used = false;
130            usedEntries--;
131        }
132        freeList.push_front(i->second);
133        DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
134                i->second);
135        lookupTable.erase(i);
136    }
137*/
138
139    if (entry != -1) {
140        assert(entry < size && entry >= 0);
141        new_entry = &tlb[entry];
142    } else {
143        if (!freeList.empty()) {
144            new_entry = freeList.front();
145        } else {
146            x = lastReplaced;
147            do {
148                ++x;
149                if (x == size)
150                    x = 0;
151                if (x == lastReplaced)
152                    goto insertAllLocked;
153            } while (tlb[x].pte.locked());
154            lastReplaced = x;
155            new_entry = &tlb[x];
156        }
157        /*
158        for (x = 0; x < size; x++) {
159            if (!tlb[x].valid || !tlb[x].used)  {
160                new_entry = &tlb[x];
161                break;
162            }
163        }*/
164    }
165
166insertAllLocked:
167    // Update the last ently if their all locked
168    if (!new_entry) {
169        new_entry = &tlb[size-1];
170    }
171
172    freeList.remove(new_entry);
173    if (new_entry->valid && new_entry->used)
174        usedEntries--;
175    if (new_entry->valid)
176        lookupTable.erase(new_entry->range);
177
178
179    assert(PTE.valid());
180    new_entry->range.va = va;
181    new_entry->range.size = PTE.size() - 1;
182    new_entry->range.partitionId = partition_id;
183    new_entry->range.contextId = context_id;
184    new_entry->range.real = real;
185    new_entry->pte = PTE;
186    new_entry->used = true;;
187    new_entry->valid = true;
188    usedEntries++;
189
190
191
192    i = lookupTable.insert(new_entry->range, new_entry);
193    assert(i != lookupTable.end());
194
195    // If all entries have there used bit set, clear it on them all, but the
196    // one we just inserted
197    if (usedEntries == size) {
198        clearUsedBits();
199        new_entry->used = true;
200        usedEntries++;
201    }
202
203}
204
205
206TlbEntry*
207TLB::lookup(Addr va, int partition_id, bool real, int context_id, bool
208        update_used)
209{
210    MapIter i;
211    TlbRange tr;
212    TlbEntry *t;
213
214    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
215            va, partition_id, context_id, real);
216    // Assemble full address structure
217    tr.va = va;
218    tr.size = MachineBytes;
219    tr.contextId = context_id;
220    tr.partitionId = partition_id;
221    tr.real = real;
222
223    // Try to find the entry
224    i = lookupTable.find(tr);
225    if (i == lookupTable.end()) {
226        DPRINTF(TLB, "TLB: No valid entry found\n");
227        return NULL;
228    }
229
230    // Mark the entries used bit and clear other used bits in needed
231    t = i->second;
232    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
233            t->pte.size());
234
235    // Update the used bits only if this is a real access (not a fake one from
236    // virttophys()
237    if (!t->used && update_used) {
238        t->used = true;
239        usedEntries++;
240        if (usedEntries == size) {
241            clearUsedBits();
242            t->used = true;
243            usedEntries++;
244        }
245    }
246
247    return t;
248}
249
250void
251TLB::dumpAll()
252{
253    MapIter i;
254    for (int x = 0; x < size; x++) {
255        if (tlb[x].valid) {
256           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
257                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
258                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
259                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
260        }
261    }
262}
263
264void
265TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
266{
267    TlbRange tr;
268    MapIter i;
269
270    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
271            va, partition_id, context_id, real);
272
273    cacheValid = false;
274
275    // Assemble full address structure
276    tr.va = va;
277    tr.size = MachineBytes;
278    tr.contextId = context_id;
279    tr.partitionId = partition_id;
280    tr.real = real;
281
282    // Demap any entry that conflicts
283    i = lookupTable.find(tr);
284    if (i != lookupTable.end()) {
285        DPRINTF(IPR, "TLB: Demapped page\n");
286        i->second->valid = false;
287        if (i->second->used) {
288            i->second->used = false;
289            usedEntries--;
290        }
291        freeList.push_front(i->second);
292        lookupTable.erase(i);
293    }
294}
295
296void
297TLB::demapContext(int partition_id, int context_id)
298{
299    int x;
300    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
301            partition_id, context_id);
302    cacheValid = false;
303    for (x = 0; x < size; x++) {
304        if (tlb[x].range.contextId == context_id &&
305            tlb[x].range.partitionId == partition_id) {
306            if (tlb[x].valid == true) {
307                freeList.push_front(&tlb[x]);
308            }
309            tlb[x].valid = false;
310            if (tlb[x].used) {
311                tlb[x].used = false;
312                usedEntries--;
313            }
314            lookupTable.erase(tlb[x].range);
315        }
316    }
317}
318
319void
320TLB::demapAll(int partition_id)
321{
322    int x;
323    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
324    cacheValid = false;
325    for (x = 0; x < size; x++) {
326        if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
327            if (tlb[x].valid == true){
328                freeList.push_front(&tlb[x]);
329            }
330            tlb[x].valid = false;
331            if (tlb[x].used) {
332                tlb[x].used = false;
333                usedEntries--;
334            }
335            lookupTable.erase(tlb[x].range);
336        }
337    }
338}
339
340void
341TLB::invalidateAll()
342{
343    int x;
344    cacheValid = false;
345
346    freeList.clear();
347    lookupTable.clear();
348    for (x = 0; x < size; x++) {
349        if (tlb[x].valid == true)
350            freeList.push_back(&tlb[x]);
351        tlb[x].valid = false;
352        tlb[x].used = false;
353    }
354    usedEntries = 0;
355}
356
357uint64_t
358TLB::TteRead(int entry) {
359    if (entry >= size)
360        panic("entry: %d\n", entry);
361
362    assert(entry < size);
363    if (tlb[entry].valid)
364        return tlb[entry].pte();
365    else
366        return (uint64_t)-1ll;
367}
368
369uint64_t
370TLB::TagRead(int entry) {
371    assert(entry < size);
372    uint64_t tag;
373    if (!tlb[entry].valid)
374        return (uint64_t)-1ll;
375
376    tag = tlb[entry].range.contextId;
377    tag |= tlb[entry].range.va;
378    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
379    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
380    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
381    return tag;
382}
383
384bool
385TLB::validVirtualAddress(Addr va, bool am)
386{
387    if (am)
388        return true;
389    if (va >= StartVAddrHole && va <= EndVAddrHole)
390        return false;
391    return true;
392}
393
394void
395TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
396        bool se, FaultTypes ft, int asi)
397{
398    uint64_t sfsr;
399    sfsr = tc->readMiscReg(reg);
400
401    if (sfsr & 0x1)
402        sfsr = 0x3;
403    else
404        sfsr = 1;
405
406    if (write)
407        sfsr |= 1 << 2;
408    sfsr |= ct << 4;
409    if (se)
410        sfsr |= 1 << 6;
411    sfsr |= ft << 7;
412    sfsr |= asi << 16;
413    tc->setMiscRegWithEffect(reg, sfsr);
414}
415
416void
417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
418{
419    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
420            va, context, mbits(va, 63,13) | mbits(context,12,0));
421
422    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
423}
424
425void
426ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
427        bool se, FaultTypes ft, int asi)
428{
429    DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
430             (int)write, ct, ft, asi);
431    TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
432}
433
434void
435ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
436{
437    TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
438}
439
440void
441DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
442        bool se, FaultTypes ft, int asi)
443{
444    DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
445            a, (int)write, ct, ft, asi);
446    TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
447    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
448}
449
450void
451DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
452{
453    TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
454}
455
456
457
458Fault
459ITB::translate(RequestPtr &req, ThreadContext *tc)
460{
461    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
462
463    Addr vaddr = req->getVaddr();
464    TlbEntry *e;
465
466    assert(req->getAsi() == ASI_IMPLICIT);
467
468    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
469            vaddr, req->getSize());
470
471    // Be fast if we can!
472    if (cacheValid && cacheState == tlbdata) {
473        if (cacheEntry) {
474            if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
475                cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
476                    req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
477                                  vaddr & cacheEntry->pte.size()-1 );
478                    return NoFault;
479            }
480        } else {
481            req->setPaddr(vaddr & PAddrImplMask);
482            return NoFault;
483        }
484    }
485
486    bool hpriv = bits(tlbdata,0,0);
487    bool red = bits(tlbdata,1,1);
488    bool priv = bits(tlbdata,2,2);
489    bool addr_mask = bits(tlbdata,3,3);
490    bool lsu_im = bits(tlbdata,4,4);
491
492    int part_id = bits(tlbdata,15,8);
493    int tl = bits(tlbdata,18,16);
494    int pri_context = bits(tlbdata,47,32);
495    int context;
496    ContextType ct;
497    int asi;
498    bool real = false;
499
500    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
501           priv, hpriv, red, lsu_im, part_id);
502
503    if (tl > 0) {
504        asi = ASI_N;
505        ct = Nucleus;
506        context = 0;
507    } else {
508        asi = ASI_P;
509        ct = Primary;
510        context = pri_context;
511    }
512
513    if ( hpriv || red ) {
514        cacheValid = true;
515        cacheState = tlbdata;
516        cacheEntry = NULL;
517        req->setPaddr(vaddr & PAddrImplMask);
518        return NoFault;
519    }
520
521    // If the access is unaligned trap
522    if (vaddr & 0x3) {
523        writeSfsr(tc, false, ct, false, OtherFault, asi);
524        return new MemAddressNotAligned;
525    }
526
527    if (addr_mask)
528        vaddr = vaddr & VAddrAMask;
529
530    if (!validVirtualAddress(vaddr, addr_mask)) {
531        writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
532        return new InstructionAccessException;
533    }
534
535    if (!lsu_im) {
536        e = lookup(vaddr, part_id, true);
537        real = true;
538        context = 0;
539    } else {
540        e = lookup(vaddr, part_id, false, context);
541    }
542
543    if (e == NULL || !e->valid) {
544        writeTagAccess(tc, vaddr, context);
545        if (real)
546            return new InstructionRealTranslationMiss;
547        else
548            return new FastInstructionAccessMMUMiss;
549    }
550
551    // were not priviledged accesing priv page
552    if (!priv && e->pte.priv()) {
553        writeTagAccess(tc, vaddr, context);
554        writeSfsr(tc, false, ct, false, PrivViolation, asi);
555        return new InstructionAccessException;
556    }
557
558    // cache translation date for next translation
559    cacheValid = true;
560    cacheState = tlbdata;
561    cacheEntry = e;
562
563    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
564                  vaddr & e->pte.size()-1 );
565    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
566    return NoFault;
567}
568
569
570
571Fault
572DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
573{
574    /* @todo this could really use some profiling and fixing to make it faster! */
575    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
576    Addr vaddr = req->getVaddr();
577    Addr size = req->getSize();
578    ASI asi;
579    asi = (ASI)req->getAsi();
580    bool implicit = false;
581    bool hpriv = bits(tlbdata,0,0);
582
583    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
584            vaddr, size, asi);
585
586    if (lookupTable.size() != 64 - freeList.size())
587       panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
588               freeList.size());
589    if (asi == ASI_IMPLICIT)
590        implicit = true;
591
592    if (hpriv && implicit) {
593        req->setPaddr(vaddr & PAddrImplMask);
594        return NoFault;
595    }
596
597    // Be fast if we can!
598    if (cacheValid &&  cacheState == tlbdata) {
599        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
600            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
601            (!write || cacheEntry[0]->pte.writable())) {
602                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
603                              vaddr & cacheEntry[0]->pte.size()-1 );
604                return NoFault;
605        }
606        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
607            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
608            (!write || cacheEntry[1]->pte.writable())) {
609                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
610                              vaddr & cacheEntry[1]->pte.size()-1 );
611                return NoFault;
612        }
613    }
614
615    bool red = bits(tlbdata,1,1);
616    bool priv = bits(tlbdata,2,2);
617    bool addr_mask = bits(tlbdata,3,3);
618    bool lsu_dm = bits(tlbdata,5,5);
619
620    int part_id = bits(tlbdata,15,8);
621    int tl = bits(tlbdata,18,16);
622    int pri_context = bits(tlbdata,47,32);
623    int sec_context = bits(tlbdata,63,48);
624
625    bool real = false;
626    ContextType ct = Primary;
627    int context = 0;
628
629    TlbEntry *e;
630
631    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
632           priv, hpriv, red, lsu_dm, part_id);
633
634    if (implicit) {
635        if (tl > 0) {
636            asi = ASI_N;
637            ct = Nucleus;
638            context = 0;
639        } else {
640            asi = ASI_P;
641            ct = Primary;
642            context = pri_context;
643        }
644    } else {
645        // We need to check for priv level/asi priv
646        if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
647            // It appears that context should be Nucleus in these cases?
648            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
649            return new PrivilegedAction;
650        }
651
652        if (!hpriv && AsiIsHPriv(asi)) {
653            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
654            return new DataAccessException;
655        }
656
657        if (AsiIsPrimary(asi)) {
658            context = pri_context;
659            ct = Primary;
660        } else if (AsiIsSecondary(asi)) {
661            context = sec_context;
662            ct = Secondary;
663        } else if (AsiIsNucleus(asi)) {
664            ct = Nucleus;
665            context = 0;
666        } else {  // ????
667            ct = Primary;
668            context = pri_context;
669        }
670    }
671
672    if (!implicit && asi != ASI_P && asi != ASI_S) {
673        if (AsiIsLittle(asi))
674            panic("Little Endian ASIs not supported\n");
675        if (AsiIsNoFault(asi))
676            panic("No Fault ASIs not supported\n");
677
678        if (AsiIsPartialStore(asi))
679            panic("Partial Store ASIs not supported\n");
680        if (AsiIsInterrupt(asi))
681            panic("Interrupt ASIs not supported\n");
682
683        if (AsiIsMmu(asi))
684            goto handleMmuRegAccess;
685        if (AsiIsScratchPad(asi))
686            goto handleScratchRegAccess;
687        if (AsiIsQueue(asi))
688            goto handleQueueRegAccess;
689        if (AsiIsSparcError(asi))
690            goto handleSparcErrorRegAccess;
691
692        if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
693                !AsiIsTwin(asi) && !AsiIsBlock(asi))
694            panic("Accessing ASI %#X. Should we?\n", asi);
695    }
696
697    // If the asi is unaligned trap
698    if (vaddr & size-1) {
699        writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
700        return new MemAddressNotAligned;
701    }
702
703    if (addr_mask)
704        vaddr = vaddr & VAddrAMask;
705
706    if (!validVirtualAddress(vaddr, addr_mask)) {
707        writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
708        return new DataAccessException;
709    }
710
711
712    if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
713        real = true;
714        context = 0;
715    };
716
717    if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
718        req->setPaddr(vaddr & PAddrImplMask);
719        return NoFault;
720    }
721
722    e = lookup(vaddr, part_id, real, context);
723
724    if (e == NULL || !e->valid) {
725        writeTagAccess(tc, vaddr, context);
726        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
727        if (real)
728            return new DataRealTranslationMiss;
729        else
730            return new FastDataAccessMMUMiss;
731
732    }
733
734    if (!priv && e->pte.priv()) {
735        writeTagAccess(tc, vaddr, context);
736        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
737        return new DataAccessException;
738    }
739
740    if (write && !e->pte.writable()) {
741        writeTagAccess(tc, vaddr, context);
742        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
743        return new FastDataAccessProtection;
744    }
745
746    if (e->pte.nofault() && !AsiIsNoFault(asi)) {
747        writeTagAccess(tc, vaddr, context);
748        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
749        return new DataAccessException;
750    }
751
752    if (e->pte.sideffect() && AsiIsNoFault(asi)) {
753        writeTagAccess(tc, vaddr, context);
754        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
755        return new DataAccessException;
756    }
757
758
759    if (e->pte.sideffect())
760        req->setFlags(req->getFlags() | UNCACHEABLE);
761
762    // cache translation date for next translation
763    cacheState = tlbdata;
764    if (!cacheValid) {
765        cacheEntry[1] = NULL;
766        cacheEntry[0] = NULL;
767    }
768
769    if (cacheEntry[0] != e && cacheEntry[1] != e) {
770        cacheEntry[1] = cacheEntry[0];
771        cacheEntry[0] = e;
772        cacheAsi[1] = cacheAsi[0];
773        cacheAsi[0] = asi;
774        if (implicit)
775            cacheAsi[0] = (ASI)0;
776    }
777    cacheValid = true;
778    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
779                  vaddr & e->pte.size()-1);
780    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
781    return NoFault;
782    /** Normal flow ends here. */
783
784handleScratchRegAccess:
785    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
786        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
787        return new DataAccessException;
788    }
789    goto regAccessOk;
790
791handleQueueRegAccess:
792    if (!priv  && !hpriv) {
793        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
794        return new PrivilegedAction;
795    }
796    if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
797        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
798        return new DataAccessException;
799    }
800    goto regAccessOk;
801
802handleSparcErrorRegAccess:
803    if (!hpriv) {
804        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
805        if (priv)
806            return new DataAccessException;
807         else
808            return new PrivilegedAction;
809    }
810    goto regAccessOk;
811
812
813regAccessOk:
814handleMmuRegAccess:
815    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
816    req->setMmapedIpr(true);
817    req->setPaddr(req->getVaddr());
818    return NoFault;
819};
820
821Tick
822DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
823{
824    Addr va = pkt->getAddr();
825    ASI asi = (ASI)pkt->req->getAsi();
826    uint64_t temp;
827
828    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
829         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
830
831    switch (asi) {
832      case ASI_LSU_CONTROL_REG:
833        assert(va == 0);
834        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
835        break;
836      case ASI_MMU:
837        switch (va) {
838          case 0x8:
839            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
840            break;
841          case 0x10:
842            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
843            break;
844          default:
845            goto doMmuReadError;
846        }
847        break;
848      case ASI_QUEUE:
849        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
850                    (va >> 4) - 0x3c));
851        break;
852      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
853        assert(va == 0);
854        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
855        break;
856      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
857        assert(va == 0);
858        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
859        break;
860      case ASI_DMMU_CTXT_ZERO_CONFIG:
861        assert(va == 0);
862        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
863        break;
864      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
865        assert(va == 0);
866        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
867        break;
868      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
869        assert(va == 0);
870        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
871        break;
872      case ASI_IMMU_CTXT_ZERO_CONFIG:
873        assert(va == 0);
874        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
875        break;
876      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
877        assert(va == 0);
878        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
879        break;
880      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
881        assert(va == 0);
882        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
883        break;
884      case ASI_DMMU_CTXT_NONZERO_CONFIG:
885        assert(va == 0);
886        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
887        break;
888      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
889        assert(va == 0);
890        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
891        break;
892      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
893        assert(va == 0);
894        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
895        break;
896      case ASI_IMMU_CTXT_NONZERO_CONFIG:
897        assert(va == 0);
898        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
899        break;
900      case ASI_SPARC_ERROR_STATUS_REG:
901        pkt->set((uint64_t)0);
902        break;
903      case ASI_HYP_SCRATCHPAD:
904      case ASI_SCRATCHPAD:
905        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
906        break;
907      case ASI_IMMU:
908        switch (va) {
909          case 0x0:
910            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
911            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
912            break;
913          case 0x18:
914            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
915            break;
916          case 0x30:
917            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
918            break;
919          default:
920            goto doMmuReadError;
921        }
922        break;
923      case ASI_DMMU:
924        switch (va) {
925          case 0x0:
926            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
927            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
928            break;
929          case 0x18:
930            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
931            break;
932          case 0x20:
933            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
934            break;
935          case 0x30:
936            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
937            break;
938          case 0x80:
939            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
940            break;
941          default:
942                goto doMmuReadError;
943        }
944        break;
945      case ASI_DMMU_TSB_PS0_PTR_REG:
946        pkt->set(MakeTsbPtr(Ps0,
947            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
948            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
949            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
950            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
951            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
952        break;
953      case ASI_DMMU_TSB_PS1_PTR_REG:
954        pkt->set(MakeTsbPtr(Ps1,
955                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
956                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
957                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
958                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
959                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
960        break;
961      case ASI_IMMU_TSB_PS0_PTR_REG:
962          pkt->set(MakeTsbPtr(Ps0,
963                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
964                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
965                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
966                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
967                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
968        break;
969      case ASI_IMMU_TSB_PS1_PTR_REG:
970          pkt->set(MakeTsbPtr(Ps1,
971                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
972                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
973                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
974                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
975                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
976        break;
977
978      default:
979doMmuReadError:
980        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
981            (uint32_t)asi, va);
982    }
983    pkt->result = Packet::Success;
984    return tc->getCpuPtr()->cycles(1);
985}
986
987Tick
988DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
989{
990    uint64_t data = gtoh(pkt->get<uint64_t>());
991    Addr va = pkt->getAddr();
992    ASI asi = (ASI)pkt->req->getAsi();
993
994    Addr ta_insert;
995    Addr va_insert;
996    Addr ct_insert;
997    int part_insert;
998    int entry_insert = -1;
999    bool real_insert;
1000    bool ignore;
1001    int part_id;
1002    int ctx_id;
1003    PageTableEntry pte;
1004
1005    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1006         (uint32_t)asi, va, data);
1007
1008    switch (asi) {
1009      case ASI_LSU_CONTROL_REG:
1010        assert(va == 0);
1011        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1012        break;
1013      case ASI_MMU:
1014        switch (va) {
1015          case 0x8:
1016            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1017            break;
1018          case 0x10:
1019            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1020            break;
1021          default:
1022            goto doMmuWriteError;
1023        }
1024        break;
1025      case ASI_QUEUE:
1026        assert(mbits(data,13,6) == data);
1027        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1028                    (va >> 4) - 0x3c, data);
1029        break;
1030      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1031        assert(va == 0);
1032        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1033        break;
1034      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1035        assert(va == 0);
1036        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1037        break;
1038      case ASI_DMMU_CTXT_ZERO_CONFIG:
1039        assert(va == 0);
1040        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1041        break;
1042      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1043        assert(va == 0);
1044        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1045        break;
1046      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1047        assert(va == 0);
1048        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1049        break;
1050      case ASI_IMMU_CTXT_ZERO_CONFIG:
1051        assert(va == 0);
1052        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1053        break;
1054      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1055        assert(va == 0);
1056        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1057        break;
1058      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1059        assert(va == 0);
1060        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1061        break;
1062      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1063        assert(va == 0);
1064        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1065        break;
1066      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1067        assert(va == 0);
1068        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1069        break;
1070      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1071        assert(va == 0);
1072        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1073        break;
1074      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1075        assert(va == 0);
1076        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1077        break;
1078      case ASI_SPARC_ERROR_EN_REG:
1079      case ASI_SPARC_ERROR_STATUS_REG:
1080        warn("Ignoring write to SPARC ERROR regsiter\n");
1081        break;
1082      case ASI_HYP_SCRATCHPAD:
1083      case ASI_SCRATCHPAD:
1084        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1085        break;
1086      case ASI_IMMU:
1087        switch (va) {
1088          case 0x18:
1089            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1090            break;
1091          case 0x30:
1092            sext<59>(bits(data, 59,0));
1093            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1094            break;
1095          default:
1096            goto doMmuWriteError;
1097        }
1098        break;
1099      case ASI_ITLB_DATA_ACCESS_REG:
1100        entry_insert = bits(va, 8,3);
1101      case ASI_ITLB_DATA_IN_REG:
1102        assert(entry_insert != -1 || mbits(va,10,9) == va);
1103        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1104        va_insert = mbits(ta_insert, 63,13);
1105        ct_insert = mbits(ta_insert, 12,0);
1106        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1107        real_insert = bits(va, 9,9);
1108        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1109                PageTableEntry::sun4u);
1110        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1111                pte, entry_insert);
1112        break;
1113      case ASI_DTLB_DATA_ACCESS_REG:
1114        entry_insert = bits(va, 8,3);
1115      case ASI_DTLB_DATA_IN_REG:
1116        assert(entry_insert != -1 || mbits(va,10,9) == va);
1117        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1118        va_insert = mbits(ta_insert, 63,13);
1119        ct_insert = mbits(ta_insert, 12,0);
1120        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1121        real_insert = bits(va, 9,9);
1122        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1123                PageTableEntry::sun4u);
1124        insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1125        break;
1126      case ASI_IMMU_DEMAP:
1127        ignore = false;
1128        ctx_id = -1;
1129        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1130        switch (bits(va,5,4)) {
1131          case 0:
1132            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1133            break;
1134          case 1:
1135            ignore = true;
1136            break;
1137          case 3:
1138            ctx_id = 0;
1139            break;
1140          default:
1141            ignore = true;
1142        }
1143
1144        switch(bits(va,7,6)) {
1145          case 0: // demap page
1146            if (!ignore)
1147                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1148                        bits(va,9,9), ctx_id);
1149            break;
1150          case 1: //demap context
1151            if (!ignore)
1152                tc->getITBPtr()->demapContext(part_id, ctx_id);
1153            break;
1154          case 2:
1155            tc->getITBPtr()->demapAll(part_id);
1156            break;
1157          default:
1158            panic("Invalid type for IMMU demap\n");
1159        }
1160        break;
1161      case ASI_DMMU:
1162        switch (va) {
1163          case 0x18:
1164            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1165            break;
1166          case 0x30:
1167            sext<59>(bits(data, 59,0));
1168            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1169            break;
1170          case 0x80:
1171            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1172            break;
1173          default:
1174            goto doMmuWriteError;
1175        }
1176        break;
1177      case ASI_DMMU_DEMAP:
1178        ignore = false;
1179        ctx_id = -1;
1180        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1181        switch (bits(va,5,4)) {
1182          case 0:
1183            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1184            break;
1185          case 1:
1186            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1187            break;
1188          case 3:
1189            ctx_id = 0;
1190            break;
1191          default:
1192            ignore = true;
1193        }
1194
1195        switch(bits(va,7,6)) {
1196          case 0: // demap page
1197            if (!ignore)
1198                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1199            break;
1200          case 1: //demap context
1201            if (!ignore)
1202                demapContext(part_id, ctx_id);
1203            break;
1204          case 2:
1205            demapAll(part_id);
1206            break;
1207          default:
1208            panic("Invalid type for IMMU demap\n");
1209        }
1210        break;
1211      default:
1212doMmuWriteError:
1213        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1214            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1215    }
1216    pkt->result = Packet::Success;
1217    return tc->getCpuPtr()->cycles(1);
1218}
1219
1220void
1221DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1222{
1223    uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1224    ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1225                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
1226                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
1227                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
1228                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
1229    ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1230                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
1231                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
1232                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
1233                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
1234    ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1235                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
1236                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1237                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
1238                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
1239    ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1240                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
1241                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1242                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
1243                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
1244}
1245
1246
1247
1248
1249
1250uint64_t
1251DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1252        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1253{
1254    uint64_t tsb;
1255    uint64_t config;
1256
1257    if (bits(tag_access, 12,0) == 0) {
1258        tsb = c0_tsb;
1259        config = c0_config;
1260    } else {
1261        tsb = cX_tsb;
1262        config = cX_config;
1263    }
1264
1265    uint64_t ptr = mbits(tsb,63,13);
1266    bool split = bits(tsb,12,12);
1267    int tsb_size = bits(tsb,3,0);
1268    int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1269
1270    if (ps == Ps1  && split)
1271        ptr |= ULL(1) << (13 + tsb_size);
1272    ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1273
1274    return ptr;
1275}
1276
1277
1278void
1279TLB::serialize(std::ostream &os)
1280{
1281    SERIALIZE_SCALAR(size);
1282    SERIALIZE_SCALAR(usedEntries);
1283    SERIALIZE_SCALAR(lastReplaced);
1284
1285    // convert the pointer based free list into an index based one
1286    int *free_list = (int*)malloc(sizeof(int) * size);
1287    int cntr = 0;
1288    std::list<TlbEntry*>::iterator i;
1289    i = freeList.begin();
1290    while (i != freeList.end()) {
1291        free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1292        i++;
1293    }
1294    SERIALIZE_SCALAR(cntr);
1295    SERIALIZE_ARRAY(free_list,  cntr);
1296
1297    for (int x = 0; x < size; x++) {
1298        nameOut(os, csprintf("%s.PTE%d", name(), x));
1299        tlb[x].serialize(os);
1300    }
1301}
1302
1303void
1304TLB::unserialize(Checkpoint *cp, const std::string &section)
1305{
1306    int oldSize;
1307
1308    paramIn(cp, section, "size", oldSize);
1309    if (oldSize != size)
1310        panic("Don't support unserializing different sized TLBs\n");
1311    UNSERIALIZE_SCALAR(usedEntries);
1312    UNSERIALIZE_SCALAR(lastReplaced);
1313
1314    int cntr;
1315    UNSERIALIZE_SCALAR(cntr);
1316
1317    int *free_list = (int*)malloc(sizeof(int) * cntr);
1318    freeList.clear();
1319    UNSERIALIZE_ARRAY(free_list,  cntr);
1320    for (int x = 0; x < cntr; x++)
1321        freeList.push_back(&tlb[free_list[x]]);
1322
1323    lookupTable.clear();
1324    for (int x = 0; x < size; x++) {
1325        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1326        if (tlb[x].valid)
1327            lookupTable.insert(tlb[x].range, &tlb[x]);
1328
1329    }
1330}
1331
1332
1333DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1334
1335BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1336
1337    Param<int> size;
1338
1339END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1340
1341BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1342
1343    INIT_PARAM_DFLT(size, "TLB size", 48)
1344
1345END_INIT_SIM_OBJECT_PARAMS(ITB)
1346
1347
1348CREATE_SIM_OBJECT(ITB)
1349{
1350    return new ITB(getInstanceName(), size);
1351}
1352
1353REGISTER_SIM_OBJECT("SparcITB", ITB)
1354
1355BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1356
1357    Param<int> size;
1358
1359END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1360
1361BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1362
1363    INIT_PARAM_DFLT(size, "TLB size", 64)
1364
1365END_INIT_SIM_OBJECT_PARAMS(DTB)
1366
1367
1368CREATE_SIM_OBJECT(DTB)
1369{
1370    return new DTB(getInstanceName(), size);
1371}
1372
1373REGISTER_SIM_OBJECT("SparcDTB", DTB)
1374}
1375