tlb.cc revision 12620
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include "arch/sparc/tlb.hh" 32 33#include <cstring> 34 35#include "arch/sparc/asi.hh" 36#include "arch/sparc/faults.hh" 37#include "arch/sparc/registers.hh" 38#include "base/bitfield.hh" 39#include "base/compiler.hh" 40#include "base/trace.hh" 41#include "cpu/base.hh" 42#include "cpu/thread_context.hh" 43#include "debug/IPR.hh" 44#include "debug/TLB.hh" 45#include "mem/packet_access.hh" 46#include "mem/request.hh" 47#include "sim/full_system.hh" 48#include "sim/system.hh" 49 50/* @todo remove some of the magic constants. -- ali 51 * */ 52namespace SparcISA { 53 54TLB::TLB(const Params *p) 55 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 56 cacheState(0), cacheValid(false) 57{ 58 // To make this work you'll have to change the hypervisor and OS 59 if (size > 64) 60 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 61 62 tlb = new TlbEntry[size]; 63 std::memset(tlb, 0, sizeof(TlbEntry) * size); 64 65 for (int x = 0; x < size; x++) 66 freeList.push_back(&tlb[x]); 67 68 c0_tsb_ps0 = 0; 69 c0_tsb_ps1 = 0; 70 c0_config = 0; 71 cx_tsb_ps0 = 0; 72 cx_tsb_ps1 = 0; 73 cx_config = 0; 74 sfsr = 0; 75 tag_access = 0; 76 sfar = 0; 77 cacheEntry[0] = NULL; 78 cacheEntry[1] = NULL; 79} 80 81void 82TLB::clearUsedBits() 83{ 84 MapIter i; 85 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 86 TlbEntry *t = i->second; 87 if (!t->pte.locked()) { 88 t->used = false; 89 usedEntries--; 90 } 91 } 92} 93 94 95void 96TLB::insert(Addr va, int partition_id, int context_id, bool real, 97 const PageTableEntry& PTE, int entry) 98{ 99 MapIter i; 100 TlbEntry *new_entry = NULL; 101// TlbRange tr; 102 int x; 103 104 cacheValid = false; 105 va &= ~(PTE.size()-1); 106 /* tr.va = va; 107 tr.size = PTE.size() - 1; 108 tr.contextId = context_id; 109 tr.partitionId = partition_id; 110 tr.real = real; 111*/ 112 113 DPRINTF(TLB, 114 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 115 va, PTE.paddr(), partition_id, context_id, (int)real, entry); 116 117 // Demap any entry that conflicts 118 for (x = 0; x < size; x++) { 119 if (tlb[x].range.real == real && 120 tlb[x].range.partitionId == partition_id && 121 tlb[x].range.va < va + PTE.size() - 1 && 122 tlb[x].range.va + tlb[x].range.size >= va && 123 (real || tlb[x].range.contextId == context_id )) 124 { 125 if (tlb[x].valid) { 126 freeList.push_front(&tlb[x]); 127 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 128 129 tlb[x].valid = false; 130 if (tlb[x].used) { 131 tlb[x].used = false; 132 usedEntries--; 133 } 134 lookupTable.erase(tlb[x].range); 135 } 136 } 137 } 138 139 if (entry != -1) { 140 assert(entry < size && entry >= 0); 141 new_entry = &tlb[entry]; 142 } else { 143 if (!freeList.empty()) { 144 new_entry = freeList.front(); 145 } else { 146 x = lastReplaced; 147 do { 148 ++x; 149 if (x == size) 150 x = 0; 151 if (x == lastReplaced) 152 goto insertAllLocked; 153 } while (tlb[x].pte.locked()); 154 lastReplaced = x; 155 new_entry = &tlb[x]; 156 } 157 } 158 159insertAllLocked: 160 // Update the last ently if their all locked 161 if (!new_entry) { 162 new_entry = &tlb[size-1]; 163 } 164 165 freeList.remove(new_entry); 166 if (new_entry->valid && new_entry->used) 167 usedEntries--; 168 if (new_entry->valid) 169 lookupTable.erase(new_entry->range); 170 171 172 assert(PTE.valid()); 173 new_entry->range.va = va; 174 new_entry->range.size = PTE.size() - 1; 175 new_entry->range.partitionId = partition_id; 176 new_entry->range.contextId = context_id; 177 new_entry->range.real = real; 178 new_entry->pte = PTE; 179 new_entry->used = true;; 180 new_entry->valid = true; 181 usedEntries++; 182 183 i = lookupTable.insert(new_entry->range, new_entry); 184 assert(i != lookupTable.end()); 185 186 // If all entries have their used bit set, clear it on them all, 187 // but the one we just inserted 188 if (usedEntries == size) { 189 clearUsedBits(); 190 new_entry->used = true; 191 usedEntries++; 192 } 193} 194 195 196TlbEntry* 197TLB::lookup(Addr va, int partition_id, bool real, int context_id, 198 bool update_used) 199{ 200 MapIter i; 201 TlbRange tr; 202 TlbEntry *t; 203 204 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 205 va, partition_id, context_id, real); 206 // Assemble full address structure 207 tr.va = va; 208 tr.size = 1; 209 tr.contextId = context_id; 210 tr.partitionId = partition_id; 211 tr.real = real; 212 213 // Try to find the entry 214 i = lookupTable.find(tr); 215 if (i == lookupTable.end()) { 216 DPRINTF(TLB, "TLB: No valid entry found\n"); 217 return NULL; 218 } 219 220 // Mark the entries used bit and clear other used bits in needed 221 t = i->second; 222 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 223 t->pte.size()); 224 225 // Update the used bits only if this is a real access (not a fake 226 // one from virttophys() 227 if (!t->used && update_used) { 228 t->used = true; 229 usedEntries++; 230 if (usedEntries == size) { 231 clearUsedBits(); 232 t->used = true; 233 usedEntries++; 234 } 235 } 236 237 return t; 238} 239 240void 241TLB::dumpAll() 242{ 243 MapIter i; 244 for (int x = 0; x < size; x++) { 245 if (tlb[x].valid) { 246 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 247 x, tlb[x].range.partitionId, tlb[x].range.contextId, 248 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 249 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 250 } 251 } 252} 253 254void 255TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 256{ 257 TlbRange tr; 258 MapIter i; 259 260 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 261 va, partition_id, context_id, real); 262 263 cacheValid = false; 264 265 // Assemble full address structure 266 tr.va = va; 267 tr.size = 1; 268 tr.contextId = context_id; 269 tr.partitionId = partition_id; 270 tr.real = real; 271 272 // Demap any entry that conflicts 273 i = lookupTable.find(tr); 274 if (i != lookupTable.end()) { 275 DPRINTF(IPR, "TLB: Demapped page\n"); 276 i->second->valid = false; 277 if (i->second->used) { 278 i->second->used = false; 279 usedEntries--; 280 } 281 freeList.push_front(i->second); 282 lookupTable.erase(i); 283 } 284} 285 286void 287TLB::demapContext(int partition_id, int context_id) 288{ 289 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 290 partition_id, context_id); 291 cacheValid = false; 292 for (int x = 0; x < size; x++) { 293 if (tlb[x].range.contextId == context_id && 294 tlb[x].range.partitionId == partition_id) { 295 if (tlb[x].valid) { 296 freeList.push_front(&tlb[x]); 297 } 298 tlb[x].valid = false; 299 if (tlb[x].used) { 300 tlb[x].used = false; 301 usedEntries--; 302 } 303 lookupTable.erase(tlb[x].range); 304 } 305 } 306} 307 308void 309TLB::demapAll(int partition_id) 310{ 311 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 312 cacheValid = false; 313 for (int x = 0; x < size; x++) { 314 if (tlb[x].valid && !tlb[x].pte.locked() && 315 tlb[x].range.partitionId == partition_id) { 316 freeList.push_front(&tlb[x]); 317 tlb[x].valid = false; 318 if (tlb[x].used) { 319 tlb[x].used = false; 320 usedEntries--; 321 } 322 lookupTable.erase(tlb[x].range); 323 } 324 } 325} 326 327void 328TLB::flushAll() 329{ 330 cacheValid = false; 331 lookupTable.clear(); 332 333 for (int x = 0; x < size; x++) { 334 if (tlb[x].valid) 335 freeList.push_back(&tlb[x]); 336 tlb[x].valid = false; 337 tlb[x].used = false; 338 } 339 usedEntries = 0; 340} 341 342uint64_t 343TLB::TteRead(int entry) 344{ 345 if (entry >= size) 346 panic("entry: %d\n", entry); 347 348 assert(entry < size); 349 if (tlb[entry].valid) 350 return tlb[entry].pte(); 351 else 352 return (uint64_t)-1ll; 353} 354 355uint64_t 356TLB::TagRead(int entry) 357{ 358 assert(entry < size); 359 uint64_t tag; 360 if (!tlb[entry].valid) 361 return (uint64_t)-1ll; 362 363 tag = tlb[entry].range.contextId; 364 tag |= tlb[entry].range.va; 365 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 366 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 367 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 368 return tag; 369} 370 371bool 372TLB::validVirtualAddress(Addr va, bool am) 373{ 374 if (am) 375 return true; 376 if (va >= StartVAddrHole && va <= EndVAddrHole) 377 return false; 378 return true; 379} 380 381void 382TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 383{ 384 if (sfsr & 0x1) 385 sfsr = 0x3; 386 else 387 sfsr = 1; 388 389 if (write) 390 sfsr |= 1 << 2; 391 sfsr |= ct << 4; 392 if (se) 393 sfsr |= 1 << 6; 394 sfsr |= ft << 7; 395 sfsr |= asi << 16; 396} 397 398void 399TLB::writeTagAccess(Addr va, int context) 400{ 401 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 402 va, context, mbits(va, 63,13) | mbits(context,12,0)); 403 404 tag_access = mbits(va, 63,13) | mbits(context,12,0); 405} 406 407void 408TLB::writeSfsr(Addr a, bool write, ContextType ct, 409 bool se, FaultTypes ft, int asi) 410{ 411 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 412 a, (int)write, ct, ft, asi); 413 TLB::writeSfsr(write, ct, se, ft, asi); 414 sfar = a; 415} 416 417Fault 418TLB::translateInst(RequestPtr req, ThreadContext *tc) 419{ 420 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 421 422 Addr vaddr = req->getVaddr(); 423 TlbEntry *e; 424 425 assert(req->getArchFlags() == ASI_IMPLICIT); 426 427 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 428 vaddr, req->getSize()); 429 430 // Be fast if we can! 431 if (cacheValid && cacheState == tlbdata) { 432 if (cacheEntry[0]) { 433 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 434 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 435 req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 436 return NoFault; 437 } 438 } else { 439 req->setPaddr(vaddr & PAddrImplMask); 440 return NoFault; 441 } 442 } 443 444 bool hpriv = bits(tlbdata,0,0); 445 bool red = bits(tlbdata,1,1); 446 bool priv = bits(tlbdata,2,2); 447 bool addr_mask = bits(tlbdata,3,3); 448 bool lsu_im = bits(tlbdata,4,4); 449 450 int part_id = bits(tlbdata,15,8); 451 int tl = bits(tlbdata,18,16); 452 int pri_context = bits(tlbdata,47,32); 453 int context; 454 ContextType ct; 455 int asi; 456 bool real = false; 457 458 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 459 priv, hpriv, red, lsu_im, part_id); 460 461 if (tl > 0) { 462 asi = ASI_N; 463 ct = Nucleus; 464 context = 0; 465 } else { 466 asi = ASI_P; 467 ct = Primary; 468 context = pri_context; 469 } 470 471 if ( hpriv || red ) { 472 cacheValid = true; 473 cacheState = tlbdata; 474 cacheEntry[0] = NULL; 475 req->setPaddr(vaddr & PAddrImplMask); 476 return NoFault; 477 } 478 479 // If the access is unaligned trap 480 if (vaddr & 0x3) { 481 writeSfsr(false, ct, false, OtherFault, asi); 482 return std::make_shared<MemAddressNotAligned>(); 483 } 484 485 if (addr_mask) 486 vaddr = vaddr & VAddrAMask; 487 488 if (!validVirtualAddress(vaddr, addr_mask)) { 489 writeSfsr(false, ct, false, VaOutOfRange, asi); 490 return std::make_shared<InstructionAccessException>(); 491 } 492 493 if (!lsu_im) { 494 e = lookup(vaddr, part_id, true); 495 real = true; 496 context = 0; 497 } else { 498 e = lookup(vaddr, part_id, false, context); 499 } 500 501 if (e == NULL || !e->valid) { 502 writeTagAccess(vaddr, context); 503 if (real) { 504 return std::make_shared<InstructionRealTranslationMiss>(); 505 } else { 506 if (FullSystem) 507 return std::make_shared<FastInstructionAccessMMUMiss>(); 508 else 509 return std::make_shared<FastInstructionAccessMMUMiss>( 510 req->getVaddr()); 511 } 512 } 513 514 // were not priviledged accesing priv page 515 if (!priv && e->pte.priv()) { 516 writeTagAccess(vaddr, context); 517 writeSfsr(false, ct, false, PrivViolation, asi); 518 return std::make_shared<InstructionAccessException>(); 519 } 520 521 // cache translation date for next translation 522 cacheValid = true; 523 cacheState = tlbdata; 524 cacheEntry[0] = e; 525 526 req->setPaddr(e->pte.translate(vaddr)); 527 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 528 return NoFault; 529} 530 531Fault 532TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 533{ 534 /* 535 * @todo this could really use some profiling and fixing to make 536 * it faster! 537 */ 538 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 539 Addr vaddr = req->getVaddr(); 540 Addr size = req->getSize(); 541 ASI asi; 542 asi = (ASI)req->getArchFlags(); 543 bool implicit = false; 544 bool hpriv = bits(tlbdata,0,0); 545 bool unaligned = vaddr & (size - 1); 546 547 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 548 vaddr, size, asi); 549 550 if (lookupTable.size() != 64 - freeList.size()) 551 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 552 freeList.size()); 553 if (asi == ASI_IMPLICIT) 554 implicit = true; 555 556 // Only use the fast path here if there doesn't need to be an unaligned 557 // trap later 558 if (!unaligned) { 559 if (hpriv && implicit) { 560 req->setPaddr(vaddr & PAddrImplMask); 561 return NoFault; 562 } 563 564 // Be fast if we can! 565 if (cacheValid && cacheState == tlbdata) { 566 567 568 569 if (cacheEntry[0]) { 570 TlbEntry *ce = cacheEntry[0]; 571 Addr ce_va = ce->range.va; 572 if (cacheAsi[0] == asi && 573 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 574 (!write || ce->pte.writable())) { 575 req->setPaddr(ce->pte.translate(vaddr)); 576 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 577 req->setFlags( 578 Request::UNCACHEABLE | Request::STRICT_ORDER); 579 } 580 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 581 return NoFault; 582 } // if matched 583 } // if cache entry valid 584 if (cacheEntry[1]) { 585 TlbEntry *ce = cacheEntry[1]; 586 Addr ce_va = ce->range.va; 587 if (cacheAsi[1] == asi && 588 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 589 (!write || ce->pte.writable())) { 590 req->setPaddr(ce->pte.translate(vaddr)); 591 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 592 req->setFlags( 593 Request::UNCACHEABLE | Request::STRICT_ORDER); 594 } 595 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 596 return NoFault; 597 } // if matched 598 } // if cache entry valid 599 } 600 } 601 602 bool red = bits(tlbdata,1,1); 603 bool priv = bits(tlbdata,2,2); 604 bool addr_mask = bits(tlbdata,3,3); 605 bool lsu_dm = bits(tlbdata,5,5); 606 607 int part_id = bits(tlbdata,15,8); 608 int tl = bits(tlbdata,18,16); 609 int pri_context = bits(tlbdata,47,32); 610 int sec_context = bits(tlbdata,63,48); 611 612 bool real = false; 613 ContextType ct = Primary; 614 int context = 0; 615 616 TlbEntry *e; 617 618 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 619 priv, hpriv, red, lsu_dm, part_id); 620 621 if (implicit) { 622 if (tl > 0) { 623 asi = ASI_N; 624 ct = Nucleus; 625 context = 0; 626 } else { 627 asi = ASI_P; 628 ct = Primary; 629 context = pri_context; 630 } 631 } else { 632 // We need to check for priv level/asi priv 633 if (!priv && !hpriv && !asiIsUnPriv(asi)) { 634 // It appears that context should be Nucleus in these cases? 635 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 636 return std::make_shared<PrivilegedAction>(); 637 } 638 639 if (!hpriv && asiIsHPriv(asi)) { 640 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 641 return std::make_shared<DataAccessException>(); 642 } 643 644 if (asiIsPrimary(asi)) { 645 context = pri_context; 646 ct = Primary; 647 } else if (asiIsSecondary(asi)) { 648 context = sec_context; 649 ct = Secondary; 650 } else if (asiIsNucleus(asi)) { 651 ct = Nucleus; 652 context = 0; 653 } else { // ???? 654 ct = Primary; 655 context = pri_context; 656 } 657 } 658 659 if (!implicit && asi != ASI_P && asi != ASI_S) { 660 if (asiIsLittle(asi)) 661 panic("Little Endian ASIs not supported\n"); 662 663 //XXX It's unclear from looking at the documentation how a no fault 664 // load differs from a regular one, other than what happens concerning 665 // nfo and e bits in the TTE 666// if (asiIsNoFault(asi)) 667// panic("No Fault ASIs not supported\n"); 668 669 if (asiIsPartialStore(asi)) 670 panic("Partial Store ASIs not supported\n"); 671 672 if (asiIsCmt(asi)) 673 panic("Cmt ASI registers not implmented\n"); 674 675 if (asiIsInterrupt(asi)) 676 goto handleIntRegAccess; 677 if (asiIsMmu(asi)) 678 goto handleMmuRegAccess; 679 if (asiIsScratchPad(asi)) 680 goto handleScratchRegAccess; 681 if (asiIsQueue(asi)) 682 goto handleQueueRegAccess; 683 if (asiIsSparcError(asi)) 684 goto handleSparcErrorRegAccess; 685 686 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 687 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 688 panic("Accessing ASI %#X. Should we?\n", asi); 689 } 690 691 // If the asi is unaligned trap 692 if (unaligned) { 693 writeSfsr(vaddr, false, ct, false, OtherFault, asi); 694 return std::make_shared<MemAddressNotAligned>(); 695 } 696 697 if (addr_mask) 698 vaddr = vaddr & VAddrAMask; 699 700 if (!validVirtualAddress(vaddr, addr_mask)) { 701 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 702 return std::make_shared<DataAccessException>(); 703 } 704 705 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 706 real = true; 707 context = 0; 708 } 709 710 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 711 req->setPaddr(vaddr & PAddrImplMask); 712 return NoFault; 713 } 714 715 e = lookup(vaddr, part_id, real, context); 716 717 if (e == NULL || !e->valid) { 718 writeTagAccess(vaddr, context); 719 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 720 if (real) { 721 return std::make_shared<DataRealTranslationMiss>(); 722 } else { 723 if (FullSystem) 724 return std::make_shared<FastDataAccessMMUMiss>(); 725 else 726 return std::make_shared<FastDataAccessMMUMiss>( 727 req->getVaddr()); 728 } 729 730 } 731 732 if (!priv && e->pte.priv()) { 733 writeTagAccess(vaddr, context); 734 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 735 return std::make_shared<DataAccessException>(); 736 } 737 738 if (write && !e->pte.writable()) { 739 writeTagAccess(vaddr, context); 740 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 741 return std::make_shared<FastDataAccessProtection>(); 742 } 743 744 if (e->pte.nofault() && !asiIsNoFault(asi)) { 745 writeTagAccess(vaddr, context); 746 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 747 return std::make_shared<DataAccessException>(); 748 } 749 750 if (e->pte.sideffect() && asiIsNoFault(asi)) { 751 writeTagAccess(vaddr, context); 752 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 753 return std::make_shared<DataAccessException>(); 754 } 755 756 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 757 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 758 759 // cache translation date for next translation 760 cacheState = tlbdata; 761 if (!cacheValid) { 762 cacheEntry[1] = NULL; 763 cacheEntry[0] = NULL; 764 } 765 766 if (cacheEntry[0] != e && cacheEntry[1] != e) { 767 cacheEntry[1] = cacheEntry[0]; 768 cacheEntry[0] = e; 769 cacheAsi[1] = cacheAsi[0]; 770 cacheAsi[0] = asi; 771 if (implicit) 772 cacheAsi[0] = (ASI)0; 773 } 774 cacheValid = true; 775 req->setPaddr(e->pte.translate(vaddr)); 776 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 777 return NoFault; 778 779 /** Normal flow ends here. */ 780handleIntRegAccess: 781 if (!hpriv) { 782 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 783 if (priv) 784 return std::make_shared<DataAccessException>(); 785 else 786 return std::make_shared<PrivilegedAction>(); 787 } 788 789 if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 790 (asi == ASI_SWVR_UDB_INTR_R && write)) { 791 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 792 return std::make_shared<DataAccessException>(); 793 } 794 795 goto regAccessOk; 796 797 798handleScratchRegAccess: 799 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 800 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 801 return std::make_shared<DataAccessException>(); 802 } 803 goto regAccessOk; 804 805handleQueueRegAccess: 806 if (!priv && !hpriv) { 807 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 808 return std::make_shared<PrivilegedAction>(); 809 } 810 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 811 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 812 return std::make_shared<DataAccessException>(); 813 } 814 goto regAccessOk; 815 816handleSparcErrorRegAccess: 817 if (!hpriv) { 818 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 819 if (priv) 820 return std::make_shared<DataAccessException>(); 821 else 822 return std::make_shared<PrivilegedAction>(); 823 } 824 goto regAccessOk; 825 826 827regAccessOk: 828handleMmuRegAccess: 829 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 830 req->setFlags(Request::MMAPPED_IPR); 831 req->setPaddr(req->getVaddr()); 832 return NoFault; 833}; 834 835Fault 836TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 837{ 838 if (mode == Execute) 839 return translateInst(req, tc); 840 else 841 return translateData(req, tc, mode == Write); 842} 843 844void 845TLB::translateTiming(RequestPtr req, ThreadContext *tc, 846 Translation *translation, Mode mode) 847{ 848 assert(translation); 849 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 850} 851 852Fault 853TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 854{ 855 return NoFault; 856} 857 858Cycles 859TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 860{ 861 Addr va = pkt->getAddr(); 862 ASI asi = (ASI)pkt->req->getArchFlags(); 863 uint64_t temp; 864 865 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 866 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); 867 868 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 869 870 switch (asi) { 871 case ASI_LSU_CONTROL_REG: 872 assert(va == 0); 873 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 874 break; 875 case ASI_MMU: 876 switch (va) { 877 case 0x8: 878 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 879 break; 880 case 0x10: 881 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 882 break; 883 default: 884 goto doMmuReadError; 885 } 886 break; 887 case ASI_QUEUE: 888 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 889 (va >> 4) - 0x3c)); 890 break; 891 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 892 assert(va == 0); 893 pkt->set(c0_tsb_ps0); 894 break; 895 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 896 assert(va == 0); 897 pkt->set(c0_tsb_ps1); 898 break; 899 case ASI_DMMU_CTXT_ZERO_CONFIG: 900 assert(va == 0); 901 pkt->set(c0_config); 902 break; 903 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 904 assert(va == 0); 905 pkt->set(itb->c0_tsb_ps0); 906 break; 907 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 908 assert(va == 0); 909 pkt->set(itb->c0_tsb_ps1); 910 break; 911 case ASI_IMMU_CTXT_ZERO_CONFIG: 912 assert(va == 0); 913 pkt->set(itb->c0_config); 914 break; 915 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 916 assert(va == 0); 917 pkt->set(cx_tsb_ps0); 918 break; 919 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 920 assert(va == 0); 921 pkt->set(cx_tsb_ps1); 922 break; 923 case ASI_DMMU_CTXT_NONZERO_CONFIG: 924 assert(va == 0); 925 pkt->set(cx_config); 926 break; 927 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 928 assert(va == 0); 929 pkt->set(itb->cx_tsb_ps0); 930 break; 931 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 932 assert(va == 0); 933 pkt->set(itb->cx_tsb_ps1); 934 break; 935 case ASI_IMMU_CTXT_NONZERO_CONFIG: 936 assert(va == 0); 937 pkt->set(itb->cx_config); 938 break; 939 case ASI_SPARC_ERROR_STATUS_REG: 940 pkt->set((uint64_t)0); 941 break; 942 case ASI_HYP_SCRATCHPAD: 943 case ASI_SCRATCHPAD: 944 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 945 break; 946 case ASI_IMMU: 947 switch (va) { 948 case 0x0: 949 temp = itb->tag_access; 950 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 951 break; 952 case 0x18: 953 pkt->set(itb->sfsr); 954 break; 955 case 0x30: 956 pkt->set(itb->tag_access); 957 break; 958 default: 959 goto doMmuReadError; 960 } 961 break; 962 case ASI_DMMU: 963 switch (va) { 964 case 0x0: 965 temp = tag_access; 966 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 967 break; 968 case 0x18: 969 pkt->set(sfsr); 970 break; 971 case 0x20: 972 pkt->set(sfar); 973 break; 974 case 0x30: 975 pkt->set(tag_access); 976 break; 977 case 0x80: 978 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 979 break; 980 default: 981 goto doMmuReadError; 982 } 983 break; 984 case ASI_DMMU_TSB_PS0_PTR_REG: 985 pkt->set(MakeTsbPtr(Ps0, 986 tag_access, 987 c0_tsb_ps0, 988 c0_config, 989 cx_tsb_ps0, 990 cx_config)); 991 break; 992 case ASI_DMMU_TSB_PS1_PTR_REG: 993 pkt->set(MakeTsbPtr(Ps1, 994 tag_access, 995 c0_tsb_ps1, 996 c0_config, 997 cx_tsb_ps1, 998 cx_config)); 999 break; 1000 case ASI_IMMU_TSB_PS0_PTR_REG: 1001 pkt->set(MakeTsbPtr(Ps0, 1002 itb->tag_access, 1003 itb->c0_tsb_ps0, 1004 itb->c0_config, 1005 itb->cx_tsb_ps0, 1006 itb->cx_config)); 1007 break; 1008 case ASI_IMMU_TSB_PS1_PTR_REG: 1009 pkt->set(MakeTsbPtr(Ps1, 1010 itb->tag_access, 1011 itb->c0_tsb_ps1, 1012 itb->c0_config, 1013 itb->cx_tsb_ps1, 1014 itb->cx_config)); 1015 break; 1016 case ASI_SWVR_INTR_RECEIVE: 1017 { 1018 SparcISA::Interrupts * interrupts = 1019 dynamic_cast<SparcISA::Interrupts *>( 1020 tc->getCpuPtr()->getInterruptController(0)); 1021 pkt->set(interrupts->get_vec(IT_INT_VEC)); 1022 } 1023 break; 1024 case ASI_SWVR_UDB_INTR_R: 1025 { 1026 SparcISA::Interrupts * interrupts = 1027 dynamic_cast<SparcISA::Interrupts *>( 1028 tc->getCpuPtr()->getInterruptController(0)); 1029 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 1030 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp); 1031 pkt->set(temp); 1032 } 1033 break; 1034 default: 1035doMmuReadError: 1036 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 1037 (uint32_t)asi, va); 1038 } 1039 pkt->makeAtomicResponse(); 1040 return Cycles(1); 1041} 1042 1043Cycles 1044TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1045{ 1046 uint64_t data = pkt->get<uint64_t>(); 1047 Addr va = pkt->getAddr(); 1048 ASI asi = (ASI)pkt->req->getArchFlags(); 1049 1050 Addr ta_insert; 1051 Addr va_insert; 1052 Addr ct_insert; 1053 int part_insert; 1054 int entry_insert = -1; 1055 bool real_insert; 1056 bool ignore; 1057 int part_id; 1058 int ctx_id; 1059 PageTableEntry pte; 1060 1061 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1062 (uint32_t)asi, va, data); 1063 1064 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 1065 1066 switch (asi) { 1067 case ASI_LSU_CONTROL_REG: 1068 assert(va == 0); 1069 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 1070 break; 1071 case ASI_MMU: 1072 switch (va) { 1073 case 0x8: 1074 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 1075 break; 1076 case 0x10: 1077 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 1078 break; 1079 default: 1080 goto doMmuWriteError; 1081 } 1082 break; 1083 case ASI_QUEUE: 1084 assert(mbits(data,13,6) == data); 1085 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 1086 (va >> 4) - 0x3c, data); 1087 break; 1088 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1089 assert(va == 0); 1090 c0_tsb_ps0 = data; 1091 break; 1092 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1093 assert(va == 0); 1094 c0_tsb_ps1 = data; 1095 break; 1096 case ASI_DMMU_CTXT_ZERO_CONFIG: 1097 assert(va == 0); 1098 c0_config = data; 1099 break; 1100 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1101 assert(va == 0); 1102 itb->c0_tsb_ps0 = data; 1103 break; 1104 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1105 assert(va == 0); 1106 itb->c0_tsb_ps1 = data; 1107 break; 1108 case ASI_IMMU_CTXT_ZERO_CONFIG: 1109 assert(va == 0); 1110 itb->c0_config = data; 1111 break; 1112 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1113 assert(va == 0); 1114 cx_tsb_ps0 = data; 1115 break; 1116 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1117 assert(va == 0); 1118 cx_tsb_ps1 = data; 1119 break; 1120 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1121 assert(va == 0); 1122 cx_config = data; 1123 break; 1124 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1125 assert(va == 0); 1126 itb->cx_tsb_ps0 = data; 1127 break; 1128 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1129 assert(va == 0); 1130 itb->cx_tsb_ps1 = data; 1131 break; 1132 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1133 assert(va == 0); 1134 itb->cx_config = data; 1135 break; 1136 case ASI_SPARC_ERROR_EN_REG: 1137 case ASI_SPARC_ERROR_STATUS_REG: 1138 inform("Ignoring write to SPARC ERROR regsiter\n"); 1139 break; 1140 case ASI_HYP_SCRATCHPAD: 1141 case ASI_SCRATCHPAD: 1142 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1143 break; 1144 case ASI_IMMU: 1145 switch (va) { 1146 case 0x18: 1147 itb->sfsr = data; 1148 break; 1149 case 0x30: 1150 sext<59>(bits(data, 59,0)); 1151 itb->tag_access = data; 1152 break; 1153 default: 1154 goto doMmuWriteError; 1155 } 1156 break; 1157 case ASI_ITLB_DATA_ACCESS_REG: 1158 entry_insert = bits(va, 8,3); 1159 M5_FALLTHROUGH; 1160 case ASI_ITLB_DATA_IN_REG: 1161 assert(entry_insert != -1 || mbits(va,10,9) == va); 1162 ta_insert = itb->tag_access; 1163 va_insert = mbits(ta_insert, 63,13); 1164 ct_insert = mbits(ta_insert, 12,0); 1165 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1166 real_insert = bits(va, 9,9); 1167 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1168 PageTableEntry::sun4u); 1169 itb->insert(va_insert, part_insert, ct_insert, real_insert, 1170 pte, entry_insert); 1171 break; 1172 case ASI_DTLB_DATA_ACCESS_REG: 1173 entry_insert = bits(va, 8,3); 1174 M5_FALLTHROUGH; 1175 case ASI_DTLB_DATA_IN_REG: 1176 assert(entry_insert != -1 || mbits(va,10,9) == va); 1177 ta_insert = tag_access; 1178 va_insert = mbits(ta_insert, 63,13); 1179 ct_insert = mbits(ta_insert, 12,0); 1180 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1181 real_insert = bits(va, 9,9); 1182 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1183 PageTableEntry::sun4u); 1184 insert(va_insert, part_insert, ct_insert, real_insert, pte, 1185 entry_insert); 1186 break; 1187 case ASI_IMMU_DEMAP: 1188 ignore = false; 1189 ctx_id = -1; 1190 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1191 switch (bits(va,5,4)) { 1192 case 0: 1193 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1194 break; 1195 case 1: 1196 ignore = true; 1197 break; 1198 case 3: 1199 ctx_id = 0; 1200 break; 1201 default: 1202 ignore = true; 1203 } 1204 1205 switch (bits(va,7,6)) { 1206 case 0: // demap page 1207 if (!ignore) 1208 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1209 break; 1210 case 1: // demap context 1211 if (!ignore) 1212 itb->demapContext(part_id, ctx_id); 1213 break; 1214 case 2: 1215 itb->demapAll(part_id); 1216 break; 1217 default: 1218 panic("Invalid type for IMMU demap\n"); 1219 } 1220 break; 1221 case ASI_DMMU: 1222 switch (va) { 1223 case 0x18: 1224 sfsr = data; 1225 break; 1226 case 0x30: 1227 sext<59>(bits(data, 59,0)); 1228 tag_access = data; 1229 break; 1230 case 0x80: 1231 tc->setMiscReg(MISCREG_MMU_PART_ID, data); 1232 break; 1233 default: 1234 goto doMmuWriteError; 1235 } 1236 break; 1237 case ASI_DMMU_DEMAP: 1238 ignore = false; 1239 ctx_id = -1; 1240 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 1241 switch (bits(va,5,4)) { 1242 case 0: 1243 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 1244 break; 1245 case 1: 1246 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 1247 break; 1248 case 3: 1249 ctx_id = 0; 1250 break; 1251 default: 1252 ignore = true; 1253 } 1254 1255 switch (bits(va,7,6)) { 1256 case 0: // demap page 1257 if (!ignore) 1258 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1259 break; 1260 case 1: // demap context 1261 if (!ignore) 1262 demapContext(part_id, ctx_id); 1263 break; 1264 case 2: 1265 demapAll(part_id); 1266 break; 1267 default: 1268 panic("Invalid type for IMMU demap\n"); 1269 } 1270 break; 1271 case ASI_SWVR_INTR_RECEIVE: 1272 { 1273 int msb; 1274 // clear all the interrupts that aren't set in the write 1275 SparcISA::Interrupts * interrupts = 1276 dynamic_cast<SparcISA::Interrupts *>( 1277 tc->getCpuPtr()->getInterruptController(0)); 1278 while (interrupts->get_vec(IT_INT_VEC) & data) { 1279 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 1280 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb); 1281 } 1282 } 1283 break; 1284 case ASI_SWVR_UDB_INTR_W: 1285 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 1286 postInterrupt(0, bits(data, 5, 0), 0); 1287 break; 1288 default: 1289doMmuWriteError: 1290 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1291 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data); 1292 } 1293 pkt->makeAtomicResponse(); 1294 return Cycles(1); 1295} 1296 1297void 1298TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1299{ 1300 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 1301 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 1302 ptrs[0] = MakeTsbPtr(Ps0, tag_access, 1303 c0_tsb_ps0, 1304 c0_config, 1305 cx_tsb_ps0, 1306 cx_config); 1307 ptrs[1] = MakeTsbPtr(Ps1, tag_access, 1308 c0_tsb_ps1, 1309 c0_config, 1310 cx_tsb_ps1, 1311 cx_config); 1312 ptrs[2] = MakeTsbPtr(Ps0, tag_access, 1313 itb->c0_tsb_ps0, 1314 itb->c0_config, 1315 itb->cx_tsb_ps0, 1316 itb->cx_config); 1317 ptrs[3] = MakeTsbPtr(Ps1, tag_access, 1318 itb->c0_tsb_ps1, 1319 itb->c0_config, 1320 itb->cx_tsb_ps1, 1321 itb->cx_config); 1322} 1323 1324uint64_t 1325TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 1326 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 1327{ 1328 uint64_t tsb; 1329 uint64_t config; 1330 1331 if (bits(tag_access, 12,0) == 0) { 1332 tsb = c0_tsb; 1333 config = c0_config; 1334 } else { 1335 tsb = cX_tsb; 1336 config = cX_config; 1337 } 1338 1339 uint64_t ptr = mbits(tsb,63,13); 1340 bool split = bits(tsb,12,12); 1341 int tsb_size = bits(tsb,3,0); 1342 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 1343 1344 if (ps == Ps1 && split) 1345 ptr |= ULL(1) << (13 + tsb_size); 1346 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 1347 1348 return ptr; 1349} 1350 1351void 1352TLB::serialize(CheckpointOut &cp) const 1353{ 1354 SERIALIZE_SCALAR(size); 1355 SERIALIZE_SCALAR(usedEntries); 1356 SERIALIZE_SCALAR(lastReplaced); 1357 1358 // convert the pointer based free list into an index based one 1359 std::vector<int> free_list; 1360 for (const TlbEntry *entry : freeList) 1361 free_list.push_back(entry - tlb); 1362 1363 SERIALIZE_CONTAINER(free_list); 1364 1365 SERIALIZE_SCALAR(c0_tsb_ps0); 1366 SERIALIZE_SCALAR(c0_tsb_ps1); 1367 SERIALIZE_SCALAR(c0_config); 1368 SERIALIZE_SCALAR(cx_tsb_ps0); 1369 SERIALIZE_SCALAR(cx_tsb_ps1); 1370 SERIALIZE_SCALAR(cx_config); 1371 SERIALIZE_SCALAR(sfsr); 1372 SERIALIZE_SCALAR(tag_access); 1373 SERIALIZE_SCALAR(sfar); 1374 1375 for (int x = 0; x < size; x++) { 1376 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 1377 tlb[x].serialize(cp); 1378 } 1379} 1380 1381void 1382TLB::unserialize(CheckpointIn &cp) 1383{ 1384 int oldSize; 1385 1386 paramIn(cp, "size", oldSize); 1387 if (oldSize != size) 1388 panic("Don't support unserializing different sized TLBs\n"); 1389 UNSERIALIZE_SCALAR(usedEntries); 1390 UNSERIALIZE_SCALAR(lastReplaced); 1391 1392 std::vector<int> free_list; 1393 UNSERIALIZE_CONTAINER(free_list); 1394 freeList.clear(); 1395 for (int idx : free_list) 1396 freeList.push_back(&tlb[idx]); 1397 1398 UNSERIALIZE_SCALAR(c0_tsb_ps0); 1399 UNSERIALIZE_SCALAR(c0_tsb_ps1); 1400 UNSERIALIZE_SCALAR(c0_config); 1401 UNSERIALIZE_SCALAR(cx_tsb_ps0); 1402 UNSERIALIZE_SCALAR(cx_tsb_ps1); 1403 UNSERIALIZE_SCALAR(cx_config); 1404 UNSERIALIZE_SCALAR(sfsr); 1405 UNSERIALIZE_SCALAR(tag_access); 1406 1407 lookupTable.clear(); 1408 for (int x = 0; x < size; x++) { 1409 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 1410 tlb[x].unserialize(cp); 1411 if (tlb[x].valid) 1412 lookupTable.insert(tlb[x].range, &tlb[x]); 1413 1414 } 1415 UNSERIALIZE_SCALAR(sfar); 1416} 1417 1418} // namespace SparcISA 1419 1420SparcISA::TLB * 1421SparcTLBParams::create() 1422{ 1423 return new SparcISA::TLB(this); 1424} 1425