tlb.cc revision 10474:799c8ee4ecba 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/IPR.hh"
42#include "debug/TLB.hh"
43#include "mem/packet_access.hh"
44#include "mem/request.hh"
45#include "sim/full_system.hh"
46#include "sim/system.hh"
47
48/* @todo remove some of the magic constants.  -- ali
49 * */
50namespace SparcISA {
51
52TLB::TLB(const Params *p)
53    : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
54      cacheState(0), cacheValid(false)
55{
56    // To make this work you'll have to change the hypervisor and OS
57    if (size > 64)
58        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
59
60    tlb = new TlbEntry[size];
61    std::memset(tlb, 0, sizeof(TlbEntry) * size);
62
63    for (int x = 0; x < size; x++)
64        freeList.push_back(&tlb[x]);
65
66    c0_tsb_ps0 = 0;
67    c0_tsb_ps1 = 0;
68    c0_config = 0;
69    cx_tsb_ps0 = 0;
70    cx_tsb_ps1 = 0;
71    cx_config = 0;
72    sfsr = 0;
73    tag_access = 0;
74    sfar = 0;
75    cacheEntry[0] = NULL;
76    cacheEntry[1] = NULL;
77}
78
79void
80TLB::clearUsedBits()
81{
82    MapIter i;
83    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
84        TlbEntry *t = i->second;
85        if (!t->pte.locked()) {
86            t->used = false;
87            usedEntries--;
88        }
89    }
90}
91
92
93void
94TLB::insert(Addr va, int partition_id, int context_id, bool real,
95        const PageTableEntry& PTE, int entry)
96{
97    MapIter i;
98    TlbEntry *new_entry = NULL;
99//    TlbRange tr;
100    int x;
101
102    cacheValid = false;
103    va &= ~(PTE.size()-1);
104 /*   tr.va = va;
105    tr.size = PTE.size() - 1;
106    tr.contextId = context_id;
107    tr.partitionId = partition_id;
108    tr.real = real;
109*/
110
111    DPRINTF(TLB,
112        "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
113        va, PTE.paddr(), partition_id, context_id, (int)real, entry);
114
115    // Demap any entry that conflicts
116    for (x = 0; x < size; x++) {
117        if (tlb[x].range.real == real &&
118            tlb[x].range.partitionId == partition_id &&
119            tlb[x].range.va < va + PTE.size() - 1 &&
120            tlb[x].range.va + tlb[x].range.size >= va &&
121            (real || tlb[x].range.contextId == context_id ))
122        {
123            if (tlb[x].valid) {
124                freeList.push_front(&tlb[x]);
125                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
126
127                tlb[x].valid = false;
128                if (tlb[x].used) {
129                    tlb[x].used = false;
130                    usedEntries--;
131                }
132                lookupTable.erase(tlb[x].range);
133            }
134        }
135    }
136
137    if (entry != -1) {
138        assert(entry < size && entry >= 0);
139        new_entry = &tlb[entry];
140    } else {
141        if (!freeList.empty()) {
142            new_entry = freeList.front();
143        } else {
144            x = lastReplaced;
145            do {
146                ++x;
147                if (x == size)
148                    x = 0;
149                if (x == lastReplaced)
150                    goto insertAllLocked;
151            } while (tlb[x].pte.locked());
152            lastReplaced = x;
153            new_entry = &tlb[x];
154        }
155    }
156
157insertAllLocked:
158    // Update the last ently if their all locked
159    if (!new_entry) {
160        new_entry = &tlb[size-1];
161    }
162
163    freeList.remove(new_entry);
164    if (new_entry->valid && new_entry->used)
165        usedEntries--;
166    if (new_entry->valid)
167        lookupTable.erase(new_entry->range);
168
169
170    assert(PTE.valid());
171    new_entry->range.va = va;
172    new_entry->range.size = PTE.size() - 1;
173    new_entry->range.partitionId = partition_id;
174    new_entry->range.contextId = context_id;
175    new_entry->range.real = real;
176    new_entry->pte = PTE;
177    new_entry->used = true;;
178    new_entry->valid = true;
179    usedEntries++;
180
181    i = lookupTable.insert(new_entry->range, new_entry);
182    assert(i != lookupTable.end());
183
184    // If all entries have their used bit set, clear it on them all,
185    // but the one we just inserted
186    if (usedEntries == size) {
187        clearUsedBits();
188        new_entry->used = true;
189        usedEntries++;
190    }
191}
192
193
194TlbEntry*
195TLB::lookup(Addr va, int partition_id, bool real, int context_id,
196            bool update_used)
197{
198    MapIter i;
199    TlbRange tr;
200    TlbEntry *t;
201
202    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
203            va, partition_id, context_id, real);
204    // Assemble full address structure
205    tr.va = va;
206    tr.size = 1;
207    tr.contextId = context_id;
208    tr.partitionId = partition_id;
209    tr.real = real;
210
211    // Try to find the entry
212    i = lookupTable.find(tr);
213    if (i == lookupTable.end()) {
214        DPRINTF(TLB, "TLB: No valid entry found\n");
215        return NULL;
216    }
217
218    // Mark the entries used bit and clear other used bits in needed
219    t = i->second;
220    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
221            t->pte.size());
222
223    // Update the used bits only if this is a real access (not a fake
224    // one from virttophys()
225    if (!t->used && update_used) {
226        t->used = true;
227        usedEntries++;
228        if (usedEntries == size) {
229            clearUsedBits();
230            t->used = true;
231            usedEntries++;
232        }
233    }
234
235    return t;
236}
237
238void
239TLB::dumpAll()
240{
241    MapIter i;
242    for (int x = 0; x < size; x++) {
243        if (tlb[x].valid) {
244           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
245                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
246                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
247                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
248        }
249    }
250}
251
252void
253TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
254{
255    TlbRange tr;
256    MapIter i;
257
258    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
259            va, partition_id, context_id, real);
260
261    cacheValid = false;
262
263    // Assemble full address structure
264    tr.va = va;
265    tr.size = 1;
266    tr.contextId = context_id;
267    tr.partitionId = partition_id;
268    tr.real = real;
269
270    // Demap any entry that conflicts
271    i = lookupTable.find(tr);
272    if (i != lookupTable.end()) {
273        DPRINTF(IPR, "TLB: Demapped page\n");
274        i->second->valid = false;
275        if (i->second->used) {
276            i->second->used = false;
277            usedEntries--;
278        }
279        freeList.push_front(i->second);
280        lookupTable.erase(i);
281    }
282}
283
284void
285TLB::demapContext(int partition_id, int context_id)
286{
287    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
288            partition_id, context_id);
289    cacheValid = false;
290    for (int x = 0; x < size; x++) {
291        if (tlb[x].range.contextId == context_id &&
292            tlb[x].range.partitionId == partition_id) {
293            if (tlb[x].valid) {
294                freeList.push_front(&tlb[x]);
295            }
296            tlb[x].valid = false;
297            if (tlb[x].used) {
298                tlb[x].used = false;
299                usedEntries--;
300            }
301            lookupTable.erase(tlb[x].range);
302        }
303    }
304}
305
306void
307TLB::demapAll(int partition_id)
308{
309    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
310    cacheValid = false;
311    for (int x = 0; x < size; x++) {
312        if (tlb[x].valid && !tlb[x].pte.locked() &&
313                tlb[x].range.partitionId == partition_id) {
314            freeList.push_front(&tlb[x]);
315            tlb[x].valid = false;
316            if (tlb[x].used) {
317                tlb[x].used = false;
318                usedEntries--;
319            }
320            lookupTable.erase(tlb[x].range);
321        }
322    }
323}
324
325void
326TLB::flushAll()
327{
328    cacheValid = false;
329    lookupTable.clear();
330
331    for (int x = 0; x < size; x++) {
332        if (tlb[x].valid)
333            freeList.push_back(&tlb[x]);
334        tlb[x].valid = false;
335        tlb[x].used = false;
336    }
337    usedEntries = 0;
338}
339
340uint64_t
341TLB::TteRead(int entry)
342{
343    if (entry >= size)
344        panic("entry: %d\n", entry);
345
346    assert(entry < size);
347    if (tlb[entry].valid)
348        return tlb[entry].pte();
349    else
350        return (uint64_t)-1ll;
351}
352
353uint64_t
354TLB::TagRead(int entry)
355{
356    assert(entry < size);
357    uint64_t tag;
358    if (!tlb[entry].valid)
359        return (uint64_t)-1ll;
360
361    tag = tlb[entry].range.contextId;
362    tag |= tlb[entry].range.va;
363    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
364    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
365    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
366    return tag;
367}
368
369bool
370TLB::validVirtualAddress(Addr va, bool am)
371{
372    if (am)
373        return true;
374    if (va >= StartVAddrHole && va <= EndVAddrHole)
375        return false;
376    return true;
377}
378
379void
380TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
381{
382    if (sfsr & 0x1)
383        sfsr = 0x3;
384    else
385        sfsr = 1;
386
387    if (write)
388        sfsr |= 1 << 2;
389    sfsr |= ct << 4;
390    if (se)
391        sfsr |= 1 << 6;
392    sfsr |= ft << 7;
393    sfsr |= asi << 16;
394}
395
396void
397TLB::writeTagAccess(Addr va, int context)
398{
399    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
400            va, context, mbits(va, 63,13) | mbits(context,12,0));
401
402    tag_access = mbits(va, 63,13) | mbits(context,12,0);
403}
404
405void
406TLB::writeSfsr(Addr a, bool write, ContextType ct,
407        bool se, FaultTypes ft, int asi)
408{
409    DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
410            a, (int)write, ct, ft, asi);
411    TLB::writeSfsr(write, ct, se, ft, asi);
412    sfar = a;
413}
414
415Fault
416TLB::translateInst(RequestPtr req, ThreadContext *tc)
417{
418    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
419
420    Addr vaddr = req->getVaddr();
421    TlbEntry *e;
422
423    assert(req->getArchFlags() == ASI_IMPLICIT);
424
425    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
426            vaddr, req->getSize());
427
428    // Be fast if we can!
429    if (cacheValid && cacheState == tlbdata) {
430        if (cacheEntry[0]) {
431            if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
432                cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
433                req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
434                return NoFault;
435            }
436        } else {
437            req->setPaddr(vaddr & PAddrImplMask);
438            return NoFault;
439        }
440    }
441
442    bool hpriv = bits(tlbdata,0,0);
443    bool red = bits(tlbdata,1,1);
444    bool priv = bits(tlbdata,2,2);
445    bool addr_mask = bits(tlbdata,3,3);
446    bool lsu_im = bits(tlbdata,4,4);
447
448    int part_id = bits(tlbdata,15,8);
449    int tl = bits(tlbdata,18,16);
450    int pri_context = bits(tlbdata,47,32);
451    int context;
452    ContextType ct;
453    int asi;
454    bool real = false;
455
456    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
457           priv, hpriv, red, lsu_im, part_id);
458
459    if (tl > 0) {
460        asi = ASI_N;
461        ct = Nucleus;
462        context = 0;
463    } else {
464        asi = ASI_P;
465        ct = Primary;
466        context = pri_context;
467    }
468
469    if ( hpriv || red ) {
470        cacheValid = true;
471        cacheState = tlbdata;
472        cacheEntry[0] = NULL;
473        req->setPaddr(vaddr & PAddrImplMask);
474        return NoFault;
475    }
476
477    // If the access is unaligned trap
478    if (vaddr & 0x3) {
479        writeSfsr(false, ct, false, OtherFault, asi);
480        return std::make_shared<MemAddressNotAligned>();
481    }
482
483    if (addr_mask)
484        vaddr = vaddr & VAddrAMask;
485
486    if (!validVirtualAddress(vaddr, addr_mask)) {
487        writeSfsr(false, ct, false, VaOutOfRange, asi);
488        return std::make_shared<InstructionAccessException>();
489    }
490
491    if (!lsu_im) {
492        e = lookup(vaddr, part_id, true);
493        real = true;
494        context = 0;
495    } else {
496        e = lookup(vaddr, part_id, false, context);
497    }
498
499    if (e == NULL || !e->valid) {
500        writeTagAccess(vaddr, context);
501        if (real) {
502            return std::make_shared<InstructionRealTranslationMiss>();
503        } else {
504            if (FullSystem)
505                return std::make_shared<FastInstructionAccessMMUMiss>();
506            else
507                return std::make_shared<FastInstructionAccessMMUMiss>(
508                    req->getVaddr());
509        }
510    }
511
512    // were not priviledged accesing priv page
513    if (!priv && e->pte.priv()) {
514        writeTagAccess(vaddr, context);
515        writeSfsr(false, ct, false, PrivViolation, asi);
516        return std::make_shared<InstructionAccessException>();
517    }
518
519    // cache translation date for next translation
520    cacheValid = true;
521    cacheState = tlbdata;
522    cacheEntry[0] = e;
523
524    req->setPaddr(e->pte.translate(vaddr));
525    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
526    return NoFault;
527}
528
529Fault
530TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
531{
532    /*
533     * @todo this could really use some profiling and fixing to make
534     * it faster!
535     */
536    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
537    Addr vaddr = req->getVaddr();
538    Addr size = req->getSize();
539    ASI asi;
540    asi = (ASI)req->getArchFlags();
541    bool implicit = false;
542    bool hpriv = bits(tlbdata,0,0);
543    bool unaligned = vaddr & (size - 1);
544
545    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
546            vaddr, size, asi);
547
548    if (lookupTable.size() != 64 - freeList.size())
549       panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
550               freeList.size());
551    if (asi == ASI_IMPLICIT)
552        implicit = true;
553
554    // Only use the fast path here if there doesn't need to be an unaligned
555    // trap later
556    if (!unaligned) {
557        if (hpriv && implicit) {
558            req->setPaddr(vaddr & PAddrImplMask);
559            return NoFault;
560        }
561
562        // Be fast if we can!
563        if (cacheValid &&  cacheState == tlbdata) {
564
565
566
567            if (cacheEntry[0]) {
568                TlbEntry *ce = cacheEntry[0];
569                Addr ce_va = ce->range.va;
570                if (cacheAsi[0] == asi &&
571                    ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
572                    (!write || ce->pte.writable())) {
573                    req->setPaddr(ce->pte.translate(vaddr));
574                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
575                        req->setFlags(Request::UNCACHEABLE);
576                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
577                    return NoFault;
578                } // if matched
579            } // if cache entry valid
580            if (cacheEntry[1]) {
581                TlbEntry *ce = cacheEntry[1];
582                Addr ce_va = ce->range.va;
583                if (cacheAsi[1] == asi &&
584                    ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
585                    (!write || ce->pte.writable())) {
586                    req->setPaddr(ce->pte.translate(vaddr));
587                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
588                        req->setFlags(Request::UNCACHEABLE);
589                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
590                    return NoFault;
591                } // if matched
592            } // if cache entry valid
593        }
594    }
595
596    bool red = bits(tlbdata,1,1);
597    bool priv = bits(tlbdata,2,2);
598    bool addr_mask = bits(tlbdata,3,3);
599    bool lsu_dm = bits(tlbdata,5,5);
600
601    int part_id = bits(tlbdata,15,8);
602    int tl = bits(tlbdata,18,16);
603    int pri_context = bits(tlbdata,47,32);
604    int sec_context = bits(tlbdata,63,48);
605
606    bool real = false;
607    ContextType ct = Primary;
608    int context = 0;
609
610    TlbEntry *e;
611
612    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
613            priv, hpriv, red, lsu_dm, part_id);
614
615    if (implicit) {
616        if (tl > 0) {
617            asi = ASI_N;
618            ct = Nucleus;
619            context = 0;
620        } else {
621            asi = ASI_P;
622            ct = Primary;
623            context = pri_context;
624        }
625    } else {
626        // We need to check for priv level/asi priv
627        if (!priv && !hpriv && !asiIsUnPriv(asi)) {
628            // It appears that context should be Nucleus in these cases?
629            writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
630            return std::make_shared<PrivilegedAction>();
631        }
632
633        if (!hpriv && asiIsHPriv(asi)) {
634            writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
635            return std::make_shared<DataAccessException>();
636        }
637
638        if (asiIsPrimary(asi)) {
639            context = pri_context;
640            ct = Primary;
641        } else if (asiIsSecondary(asi)) {
642            context = sec_context;
643            ct = Secondary;
644        } else if (asiIsNucleus(asi)) {
645            ct = Nucleus;
646            context = 0;
647        } else {  // ????
648            ct = Primary;
649            context = pri_context;
650        }
651    }
652
653    if (!implicit && asi != ASI_P && asi != ASI_S) {
654        if (asiIsLittle(asi))
655            panic("Little Endian ASIs not supported\n");
656
657        //XXX It's unclear from looking at the documentation how a no fault
658        // load differs from a regular one, other than what happens concerning
659        // nfo and e bits in the TTE
660//        if (asiIsNoFault(asi))
661//            panic("No Fault ASIs not supported\n");
662
663        if (asiIsPartialStore(asi))
664            panic("Partial Store ASIs not supported\n");
665
666        if (asiIsCmt(asi))
667            panic("Cmt ASI registers not implmented\n");
668
669        if (asiIsInterrupt(asi))
670            goto handleIntRegAccess;
671        if (asiIsMmu(asi))
672            goto handleMmuRegAccess;
673        if (asiIsScratchPad(asi))
674            goto handleScratchRegAccess;
675        if (asiIsQueue(asi))
676            goto handleQueueRegAccess;
677        if (asiIsSparcError(asi))
678            goto handleSparcErrorRegAccess;
679
680        if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
681                !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
682            panic("Accessing ASI %#X. Should we?\n", asi);
683    }
684
685    // If the asi is unaligned trap
686    if (unaligned) {
687        writeSfsr(vaddr, false, ct, false, OtherFault, asi);
688        return std::make_shared<MemAddressNotAligned>();
689    }
690
691    if (addr_mask)
692        vaddr = vaddr & VAddrAMask;
693
694    if (!validVirtualAddress(vaddr, addr_mask)) {
695        writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
696        return std::make_shared<DataAccessException>();
697    }
698
699    if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
700        real = true;
701        context = 0;
702    }
703
704    if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
705        req->setPaddr(vaddr & PAddrImplMask);
706        return NoFault;
707    }
708
709    e = lookup(vaddr, part_id, real, context);
710
711    if (e == NULL || !e->valid) {
712        writeTagAccess(vaddr, context);
713        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
714        if (real) {
715            return std::make_shared<DataRealTranslationMiss>();
716        } else {
717            if (FullSystem)
718                return std::make_shared<FastDataAccessMMUMiss>();
719            else
720                return std::make_shared<FastDataAccessMMUMiss>(
721                    req->getVaddr());
722        }
723
724    }
725
726    if (!priv && e->pte.priv()) {
727        writeTagAccess(vaddr, context);
728        writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
729        return std::make_shared<DataAccessException>();
730    }
731
732    if (write && !e->pte.writable()) {
733        writeTagAccess(vaddr, context);
734        writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
735        return std::make_shared<FastDataAccessProtection>();
736    }
737
738    if (e->pte.nofault() && !asiIsNoFault(asi)) {
739        writeTagAccess(vaddr, context);
740        writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
741        return std::make_shared<DataAccessException>();
742    }
743
744    if (e->pte.sideffect() && asiIsNoFault(asi)) {
745        writeTagAccess(vaddr, context);
746        writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
747        return std::make_shared<DataAccessException>();
748    }
749
750    if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
751        req->setFlags(Request::UNCACHEABLE);
752
753    // cache translation date for next translation
754    cacheState = tlbdata;
755    if (!cacheValid) {
756        cacheEntry[1] = NULL;
757        cacheEntry[0] = NULL;
758    }
759
760    if (cacheEntry[0] != e && cacheEntry[1] != e) {
761        cacheEntry[1] = cacheEntry[0];
762        cacheEntry[0] = e;
763        cacheAsi[1] = cacheAsi[0];
764        cacheAsi[0] = asi;
765        if (implicit)
766            cacheAsi[0] = (ASI)0;
767    }
768    cacheValid = true;
769    req->setPaddr(e->pte.translate(vaddr));
770    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
771    return NoFault;
772
773    /** Normal flow ends here. */
774handleIntRegAccess:
775    if (!hpriv) {
776        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
777        if (priv)
778            return std::make_shared<DataAccessException>();
779         else
780             return std::make_shared<PrivilegedAction>();
781    }
782
783    if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
784        (asi == ASI_SWVR_UDB_INTR_R && write)) {
785        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
786        return std::make_shared<DataAccessException>();
787    }
788
789    goto regAccessOk;
790
791
792handleScratchRegAccess:
793    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
794        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
795        return std::make_shared<DataAccessException>();
796    }
797    goto regAccessOk;
798
799handleQueueRegAccess:
800    if (!priv  && !hpriv) {
801        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
802        return std::make_shared<PrivilegedAction>();
803    }
804    if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
805        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
806        return std::make_shared<DataAccessException>();
807    }
808    goto regAccessOk;
809
810handleSparcErrorRegAccess:
811    if (!hpriv) {
812        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
813        if (priv)
814            return std::make_shared<DataAccessException>();
815         else
816             return std::make_shared<PrivilegedAction>();
817    }
818    goto regAccessOk;
819
820
821regAccessOk:
822handleMmuRegAccess:
823    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
824    req->setFlags(Request::MMAPPED_IPR);
825    req->setPaddr(req->getVaddr());
826    return NoFault;
827};
828
829Fault
830TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
831{
832    if (mode == Execute)
833        return translateInst(req, tc);
834    else
835        return translateData(req, tc, mode == Write);
836}
837
838void
839TLB::translateTiming(RequestPtr req, ThreadContext *tc,
840        Translation *translation, Mode mode)
841{
842    assert(translation);
843    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
844}
845
846Fault
847TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
848{
849    panic("Not implemented\n");
850    return NoFault;
851}
852
853Fault
854TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
855{
856    return NoFault;
857}
858
859Cycles
860TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
861{
862    Addr va = pkt->getAddr();
863    ASI asi = (ASI)pkt->req->getArchFlags();
864    uint64_t temp;
865
866    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
867         (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
868
869    TLB *itb = tc->getITBPtr();
870
871    switch (asi) {
872      case ASI_LSU_CONTROL_REG:
873        assert(va == 0);
874        pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
875        break;
876      case ASI_MMU:
877        switch (va) {
878          case 0x8:
879            pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
880            break;
881          case 0x10:
882            pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
883            break;
884          default:
885            goto doMmuReadError;
886        }
887        break;
888      case ASI_QUEUE:
889        pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
890                    (va >> 4) - 0x3c));
891        break;
892      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
893        assert(va == 0);
894        pkt->set(c0_tsb_ps0);
895        break;
896      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
897        assert(va == 0);
898        pkt->set(c0_tsb_ps1);
899        break;
900      case ASI_DMMU_CTXT_ZERO_CONFIG:
901        assert(va == 0);
902        pkt->set(c0_config);
903        break;
904      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
905        assert(va == 0);
906        pkt->set(itb->c0_tsb_ps0);
907        break;
908      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
909        assert(va == 0);
910        pkt->set(itb->c0_tsb_ps1);
911        break;
912      case ASI_IMMU_CTXT_ZERO_CONFIG:
913        assert(va == 0);
914        pkt->set(itb->c0_config);
915        break;
916      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
917        assert(va == 0);
918        pkt->set(cx_tsb_ps0);
919        break;
920      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
921        assert(va == 0);
922        pkt->set(cx_tsb_ps1);
923        break;
924      case ASI_DMMU_CTXT_NONZERO_CONFIG:
925        assert(va == 0);
926        pkt->set(cx_config);
927        break;
928      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
929        assert(va == 0);
930        pkt->set(itb->cx_tsb_ps0);
931        break;
932      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
933        assert(va == 0);
934        pkt->set(itb->cx_tsb_ps1);
935        break;
936      case ASI_IMMU_CTXT_NONZERO_CONFIG:
937        assert(va == 0);
938        pkt->set(itb->cx_config);
939        break;
940      case ASI_SPARC_ERROR_STATUS_REG:
941        pkt->set((uint64_t)0);
942        break;
943      case ASI_HYP_SCRATCHPAD:
944      case ASI_SCRATCHPAD:
945        pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
946        break;
947      case ASI_IMMU:
948        switch (va) {
949          case 0x0:
950            temp = itb->tag_access;
951            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
952            break;
953          case 0x18:
954            pkt->set(itb->sfsr);
955            break;
956          case 0x30:
957            pkt->set(itb->tag_access);
958            break;
959          default:
960            goto doMmuReadError;
961        }
962        break;
963      case ASI_DMMU:
964        switch (va) {
965          case 0x0:
966            temp = tag_access;
967            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
968            break;
969          case 0x18:
970            pkt->set(sfsr);
971            break;
972          case 0x20:
973            pkt->set(sfar);
974            break;
975          case 0x30:
976            pkt->set(tag_access);
977            break;
978          case 0x80:
979            pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
980            break;
981          default:
982                goto doMmuReadError;
983        }
984        break;
985      case ASI_DMMU_TSB_PS0_PTR_REG:
986        pkt->set(MakeTsbPtr(Ps0,
987            tag_access,
988            c0_tsb_ps0,
989            c0_config,
990            cx_tsb_ps0,
991            cx_config));
992        break;
993      case ASI_DMMU_TSB_PS1_PTR_REG:
994        pkt->set(MakeTsbPtr(Ps1,
995                tag_access,
996                c0_tsb_ps1,
997                c0_config,
998                cx_tsb_ps1,
999                cx_config));
1000        break;
1001      case ASI_IMMU_TSB_PS0_PTR_REG:
1002          pkt->set(MakeTsbPtr(Ps0,
1003                itb->tag_access,
1004                itb->c0_tsb_ps0,
1005                itb->c0_config,
1006                itb->cx_tsb_ps0,
1007                itb->cx_config));
1008        break;
1009      case ASI_IMMU_TSB_PS1_PTR_REG:
1010          pkt->set(MakeTsbPtr(Ps1,
1011                itb->tag_access,
1012                itb->c0_tsb_ps1,
1013                itb->c0_config,
1014                itb->cx_tsb_ps1,
1015                itb->cx_config));
1016        break;
1017      case ASI_SWVR_INTR_RECEIVE:
1018        {
1019            SparcISA::Interrupts * interrupts =
1020                dynamic_cast<SparcISA::Interrupts *>(
1021                        tc->getCpuPtr()->getInterruptController());
1022            pkt->set(interrupts->get_vec(IT_INT_VEC));
1023        }
1024        break;
1025      case ASI_SWVR_UDB_INTR_R:
1026        {
1027            SparcISA::Interrupts * interrupts =
1028                dynamic_cast<SparcISA::Interrupts *>(
1029                        tc->getCpuPtr()->getInterruptController());
1030            temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1031            tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
1032            pkt->set(temp);
1033        }
1034        break;
1035      default:
1036doMmuReadError:
1037        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1038            (uint32_t)asi, va);
1039    }
1040    pkt->makeAtomicResponse();
1041    return Cycles(1);
1042}
1043
1044Cycles
1045TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1046{
1047    uint64_t data = pkt->get<uint64_t>();
1048    Addr va = pkt->getAddr();
1049    ASI asi = (ASI)pkt->req->getArchFlags();
1050
1051    Addr ta_insert;
1052    Addr va_insert;
1053    Addr ct_insert;
1054    int part_insert;
1055    int entry_insert = -1;
1056    bool real_insert;
1057    bool ignore;
1058    int part_id;
1059    int ctx_id;
1060    PageTableEntry pte;
1061
1062    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1063         (uint32_t)asi, va, data);
1064
1065    TLB *itb = tc->getITBPtr();
1066
1067    switch (asi) {
1068      case ASI_LSU_CONTROL_REG:
1069        assert(va == 0);
1070        tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1071        break;
1072      case ASI_MMU:
1073        switch (va) {
1074          case 0x8:
1075            tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1076            break;
1077          case 0x10:
1078            tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1079            break;
1080          default:
1081            goto doMmuWriteError;
1082        }
1083        break;
1084      case ASI_QUEUE:
1085        assert(mbits(data,13,6) == data);
1086        tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1087                    (va >> 4) - 0x3c, data);
1088        break;
1089      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1090        assert(va == 0);
1091        c0_tsb_ps0 = data;
1092        break;
1093      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1094        assert(va == 0);
1095        c0_tsb_ps1 = data;
1096        break;
1097      case ASI_DMMU_CTXT_ZERO_CONFIG:
1098        assert(va == 0);
1099        c0_config = data;
1100        break;
1101      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1102        assert(va == 0);
1103        itb->c0_tsb_ps0 = data;
1104        break;
1105      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1106        assert(va == 0);
1107        itb->c0_tsb_ps1 = data;
1108        break;
1109      case ASI_IMMU_CTXT_ZERO_CONFIG:
1110        assert(va == 0);
1111        itb->c0_config = data;
1112        break;
1113      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1114        assert(va == 0);
1115        cx_tsb_ps0 = data;
1116        break;
1117      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1118        assert(va == 0);
1119        cx_tsb_ps1 = data;
1120        break;
1121      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1122        assert(va == 0);
1123        cx_config = data;
1124        break;
1125      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1126        assert(va == 0);
1127        itb->cx_tsb_ps0 = data;
1128        break;
1129      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1130        assert(va == 0);
1131        itb->cx_tsb_ps1 = data;
1132        break;
1133      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1134        assert(va == 0);
1135        itb->cx_config = data;
1136        break;
1137      case ASI_SPARC_ERROR_EN_REG:
1138      case ASI_SPARC_ERROR_STATUS_REG:
1139        inform("Ignoring write to SPARC ERROR regsiter\n");
1140        break;
1141      case ASI_HYP_SCRATCHPAD:
1142      case ASI_SCRATCHPAD:
1143        tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1144        break;
1145      case ASI_IMMU:
1146        switch (va) {
1147          case 0x18:
1148            itb->sfsr = data;
1149            break;
1150          case 0x30:
1151            sext<59>(bits(data, 59,0));
1152            itb->tag_access = data;
1153            break;
1154          default:
1155            goto doMmuWriteError;
1156        }
1157        break;
1158      case ASI_ITLB_DATA_ACCESS_REG:
1159        entry_insert = bits(va, 8,3);
1160      case ASI_ITLB_DATA_IN_REG:
1161        assert(entry_insert != -1 || mbits(va,10,9) == va);
1162        ta_insert = itb->tag_access;
1163        va_insert = mbits(ta_insert, 63,13);
1164        ct_insert = mbits(ta_insert, 12,0);
1165        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1166        real_insert = bits(va, 9,9);
1167        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1168                PageTableEntry::sun4u);
1169        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1170                pte, entry_insert);
1171        break;
1172      case ASI_DTLB_DATA_ACCESS_REG:
1173        entry_insert = bits(va, 8,3);
1174      case ASI_DTLB_DATA_IN_REG:
1175        assert(entry_insert != -1 || mbits(va,10,9) == va);
1176        ta_insert = tag_access;
1177        va_insert = mbits(ta_insert, 63,13);
1178        ct_insert = mbits(ta_insert, 12,0);
1179        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1180        real_insert = bits(va, 9,9);
1181        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1182                PageTableEntry::sun4u);
1183        insert(va_insert, part_insert, ct_insert, real_insert, pte,
1184               entry_insert);
1185        break;
1186      case ASI_IMMU_DEMAP:
1187        ignore = false;
1188        ctx_id = -1;
1189        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1190        switch (bits(va,5,4)) {
1191          case 0:
1192            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1193            break;
1194          case 1:
1195            ignore = true;
1196            break;
1197          case 3:
1198            ctx_id = 0;
1199            break;
1200          default:
1201            ignore = true;
1202        }
1203
1204        switch (bits(va,7,6)) {
1205          case 0: // demap page
1206            if (!ignore)
1207                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1208                        bits(va,9,9), ctx_id);
1209            break;
1210          case 1: // demap context
1211            if (!ignore)
1212                tc->getITBPtr()->demapContext(part_id, ctx_id);
1213            break;
1214          case 2:
1215            tc->getITBPtr()->demapAll(part_id);
1216            break;
1217          default:
1218            panic("Invalid type for IMMU demap\n");
1219        }
1220        break;
1221      case ASI_DMMU:
1222        switch (va) {
1223          case 0x18:
1224            sfsr = data;
1225            break;
1226          case 0x30:
1227            sext<59>(bits(data, 59,0));
1228            tag_access = data;
1229            break;
1230          case 0x80:
1231            tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1232            break;
1233          default:
1234            goto doMmuWriteError;
1235        }
1236        break;
1237      case ASI_DMMU_DEMAP:
1238        ignore = false;
1239        ctx_id = -1;
1240        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1241        switch (bits(va,5,4)) {
1242          case 0:
1243            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1244            break;
1245          case 1:
1246            ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1247            break;
1248          case 3:
1249            ctx_id = 0;
1250            break;
1251          default:
1252            ignore = true;
1253        }
1254
1255        switch (bits(va,7,6)) {
1256          case 0: // demap page
1257            if (!ignore)
1258                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1259            break;
1260          case 1: // demap context
1261            if (!ignore)
1262                demapContext(part_id, ctx_id);
1263            break;
1264          case 2:
1265            demapAll(part_id);
1266            break;
1267          default:
1268            panic("Invalid type for IMMU demap\n");
1269        }
1270        break;
1271       case ASI_SWVR_INTR_RECEIVE:
1272        {
1273            int msb;
1274            // clear all the interrupts that aren't set in the write
1275            SparcISA::Interrupts * interrupts =
1276                dynamic_cast<SparcISA::Interrupts *>(
1277                        tc->getCpuPtr()->getInterruptController());
1278            while (interrupts->get_vec(IT_INT_VEC) & data) {
1279                msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1280                tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
1281            }
1282        }
1283        break;
1284      case ASI_SWVR_UDB_INTR_W:
1285            tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1286            postInterrupt(bits(data, 5, 0), 0);
1287        break;
1288      default:
1289doMmuWriteError:
1290        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1291            (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1292    }
1293    pkt->makeAtomicResponse();
1294    return Cycles(1);
1295}
1296
1297void
1298TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1299{
1300    uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1301    TLB * itb = tc->getITBPtr();
1302    ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1303                c0_tsb_ps0,
1304                c0_config,
1305                cx_tsb_ps0,
1306                cx_config);
1307    ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1308                c0_tsb_ps1,
1309                c0_config,
1310                cx_tsb_ps1,
1311                cx_config);
1312    ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1313                itb->c0_tsb_ps0,
1314                itb->c0_config,
1315                itb->cx_tsb_ps0,
1316                itb->cx_config);
1317    ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1318                itb->c0_tsb_ps1,
1319                itb->c0_config,
1320                itb->cx_tsb_ps1,
1321                itb->cx_config);
1322}
1323
1324uint64_t
1325TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1326        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1327{
1328    uint64_t tsb;
1329    uint64_t config;
1330
1331    if (bits(tag_access, 12,0) == 0) {
1332        tsb = c0_tsb;
1333        config = c0_config;
1334    } else {
1335        tsb = cX_tsb;
1336        config = cX_config;
1337    }
1338
1339    uint64_t ptr = mbits(tsb,63,13);
1340    bool split = bits(tsb,12,12);
1341    int tsb_size = bits(tsb,3,0);
1342    int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1343
1344    if (ps == Ps1  && split)
1345        ptr |= ULL(1) << (13 + tsb_size);
1346    ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1347
1348    return ptr;
1349}
1350
1351void
1352TLB::serialize(std::ostream &os)
1353{
1354    SERIALIZE_SCALAR(size);
1355    SERIALIZE_SCALAR(usedEntries);
1356    SERIALIZE_SCALAR(lastReplaced);
1357
1358    // convert the pointer based free list into an index based one
1359    int *free_list = (int*)malloc(sizeof(int) * size);
1360    int cntr = 0;
1361    std::list<TlbEntry*>::iterator i;
1362    i = freeList.begin();
1363    while (i != freeList.end()) {
1364        free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1365        i++;
1366    }
1367    SERIALIZE_SCALAR(cntr);
1368    SERIALIZE_ARRAY(free_list,  cntr);
1369
1370    SERIALIZE_SCALAR(c0_tsb_ps0);
1371    SERIALIZE_SCALAR(c0_tsb_ps1);
1372    SERIALIZE_SCALAR(c0_config);
1373    SERIALIZE_SCALAR(cx_tsb_ps0);
1374    SERIALIZE_SCALAR(cx_tsb_ps1);
1375    SERIALIZE_SCALAR(cx_config);
1376    SERIALIZE_SCALAR(sfsr);
1377    SERIALIZE_SCALAR(tag_access);
1378
1379    for (int x = 0; x < size; x++) {
1380        nameOut(os, csprintf("%s.PTE%d", name(), x));
1381        tlb[x].serialize(os);
1382    }
1383    SERIALIZE_SCALAR(sfar);
1384}
1385
1386void
1387TLB::unserialize(Checkpoint *cp, const std::string &section)
1388{
1389    int oldSize;
1390
1391    paramIn(cp, section, "size", oldSize);
1392    if (oldSize != size)
1393        panic("Don't support unserializing different sized TLBs\n");
1394    UNSERIALIZE_SCALAR(usedEntries);
1395    UNSERIALIZE_SCALAR(lastReplaced);
1396
1397    int cntr;
1398    UNSERIALIZE_SCALAR(cntr);
1399
1400    int *free_list = (int*)malloc(sizeof(int) * cntr);
1401    freeList.clear();
1402    UNSERIALIZE_ARRAY(free_list,  cntr);
1403    for (int x = 0; x < cntr; x++)
1404        freeList.push_back(&tlb[free_list[x]]);
1405
1406    UNSERIALIZE_SCALAR(c0_tsb_ps0);
1407    UNSERIALIZE_SCALAR(c0_tsb_ps1);
1408    UNSERIALIZE_SCALAR(c0_config);
1409    UNSERIALIZE_SCALAR(cx_tsb_ps0);
1410    UNSERIALIZE_SCALAR(cx_tsb_ps1);
1411    UNSERIALIZE_SCALAR(cx_config);
1412    UNSERIALIZE_SCALAR(sfsr);
1413    UNSERIALIZE_SCALAR(tag_access);
1414
1415    lookupTable.clear();
1416    for (int x = 0; x < size; x++) {
1417        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1418        if (tlb[x].valid)
1419            lookupTable.insert(tlb[x].range, &tlb[x]);
1420
1421    }
1422    UNSERIALIZE_SCALAR(sfar);
1423}
1424
1425} // namespace SparcISA
1426
1427SparcISA::TLB *
1428SparcTLBParams::create()
1429{
1430    return new SparcISA::TLB(this);
1431}
1432