tlb.cc revision 9738
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 347678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 356335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 363569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 373824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 383811Ssaidi@eecs.umich.edu#include "base/trace.hh" 398229Snate@binkert.org#include "cpu/base.hh" 403811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 418232Snate@binkert.org#include "debug/IPR.hh" 428232Snate@binkert.org#include "debug/TLB.hh" 433823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 443823Ssaidi@eecs.umich.edu#include "mem/request.hh" 458751Sgblack@eecs.umich.edu#include "sim/full_system.hh" 464103Ssaidi@eecs.umich.edu#include "sim/system.hh" 473569Sgblack@eecs.umich.edu 483804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 493804Ssaidi@eecs.umich.edu * */ 504088Sbinkertn@umich.edunamespace SparcISA { 513569Sgblack@eecs.umich.edu 525034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 535358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 548374Sksewell@umich.edu cacheState(0), cacheValid(false) 553804Ssaidi@eecs.umich.edu{ 563804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 573804Ssaidi@eecs.umich.edu if (size > 64) 585555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 593569Sgblack@eecs.umich.edu 603804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 613918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 623881Ssaidi@eecs.umich.edu 633881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 643881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 654990Sgblack@eecs.umich.edu 664990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 674990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 684990Sgblack@eecs.umich.edu c0_config = 0; 694990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 704990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 714990Sgblack@eecs.umich.edu cx_config = 0; 724990Sgblack@eecs.umich.edu sfsr = 0; 734990Sgblack@eecs.umich.edu tag_access = 0; 746022Sgblack@eecs.umich.edu sfar = 0; 756022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 766022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 773804Ssaidi@eecs.umich.edu} 783569Sgblack@eecs.umich.edu 793804Ssaidi@eecs.umich.eduvoid 803804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 813804Ssaidi@eecs.umich.edu{ 823804Ssaidi@eecs.umich.edu MapIter i; 833881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 843804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 853804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 863804Ssaidi@eecs.umich.edu t->used = false; 873804Ssaidi@eecs.umich.edu usedEntries--; 883804Ssaidi@eecs.umich.edu } 893804Ssaidi@eecs.umich.edu } 903804Ssaidi@eecs.umich.edu} 913569Sgblack@eecs.umich.edu 923569Sgblack@eecs.umich.edu 933804Ssaidi@eecs.umich.eduvoid 943804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 953826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 963804Ssaidi@eecs.umich.edu{ 973804Ssaidi@eecs.umich.edu MapIter i; 983826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 993907Ssaidi@eecs.umich.edu// TlbRange tr; 1003826Ssaidi@eecs.umich.edu int x; 1013811Ssaidi@eecs.umich.edu 1023836Ssaidi@eecs.umich.edu cacheValid = false; 1033915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1043907Ssaidi@eecs.umich.edu /* tr.va = va; 1053881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1063881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1073881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1083881Ssaidi@eecs.umich.edu tr.real = real; 1093907Ssaidi@eecs.umich.edu*/ 1103881Ssaidi@eecs.umich.edu 1115555Snate@binkert.org DPRINTF(TLB, 1125555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1135555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1143881Ssaidi@eecs.umich.edu 1153881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1163907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1173907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1183907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1193907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1203907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1213907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1223907Ssaidi@eecs.umich.edu { 1233907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1243907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1253907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1263907Ssaidi@eecs.umich.edu 1273907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1283907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1293907Ssaidi@eecs.umich.edu tlb[x].used = false; 1303907Ssaidi@eecs.umich.edu usedEntries--; 1313907Ssaidi@eecs.umich.edu } 1323907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1333907Ssaidi@eecs.umich.edu } 1343907Ssaidi@eecs.umich.edu } 1353907Ssaidi@eecs.umich.edu } 1363907Ssaidi@eecs.umich.edu 1373826Ssaidi@eecs.umich.edu if (entry != -1) { 1383826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1393826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1403826Ssaidi@eecs.umich.edu } else { 1413881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1423881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1433881Ssaidi@eecs.umich.edu } else { 1443881Ssaidi@eecs.umich.edu x = lastReplaced; 1453881Ssaidi@eecs.umich.edu do { 1463881Ssaidi@eecs.umich.edu ++x; 1473881Ssaidi@eecs.umich.edu if (x == size) 1483881Ssaidi@eecs.umich.edu x = 0; 1493881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1503881Ssaidi@eecs.umich.edu goto insertAllLocked; 1513881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1523881Ssaidi@eecs.umich.edu lastReplaced = x; 1533881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1543881Ssaidi@eecs.umich.edu } 1553569Sgblack@eecs.umich.edu } 1563569Sgblack@eecs.umich.edu 1573881Ssaidi@eecs.umich.eduinsertAllLocked: 1583804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1593881Ssaidi@eecs.umich.edu if (!new_entry) { 1603826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1613881Ssaidi@eecs.umich.edu } 1623881Ssaidi@eecs.umich.edu 1633881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1643907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1653907Ssaidi@eecs.umich.edu usedEntries--; 1663929Ssaidi@eecs.umich.edu if (new_entry->valid) 1673929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1683907Ssaidi@eecs.umich.edu 1693907Ssaidi@eecs.umich.edu 1703804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1713804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1723881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1733804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1743804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1753804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1763804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1773804Ssaidi@eecs.umich.edu new_entry->used = true;; 1783804Ssaidi@eecs.umich.edu new_entry->valid = true; 1793804Ssaidi@eecs.umich.edu usedEntries++; 1803569Sgblack@eecs.umich.edu 1813863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1823863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1833804Ssaidi@eecs.umich.edu 1845555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 1855555Snate@binkert.org // but the one we just inserted 1863804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1873804Ssaidi@eecs.umich.edu clearUsedBits(); 1883804Ssaidi@eecs.umich.edu new_entry->used = true; 1893804Ssaidi@eecs.umich.edu usedEntries++; 1903804Ssaidi@eecs.umich.edu } 1913569Sgblack@eecs.umich.edu} 1923804Ssaidi@eecs.umich.edu 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.eduTlbEntry* 1955555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 1965555Snate@binkert.org bool update_used) 1973804Ssaidi@eecs.umich.edu{ 1983804Ssaidi@eecs.umich.edu MapIter i; 1993804Ssaidi@eecs.umich.edu TlbRange tr; 2003804Ssaidi@eecs.umich.edu TlbEntry *t; 2013804Ssaidi@eecs.umich.edu 2023811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2033811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2043804Ssaidi@eecs.umich.edu // Assemble full address structure 2053804Ssaidi@eecs.umich.edu tr.va = va; 2065312Sgblack@eecs.umich.edu tr.size = 1; 2073804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2083804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2093804Ssaidi@eecs.umich.edu tr.real = real; 2103804Ssaidi@eecs.umich.edu 2113804Ssaidi@eecs.umich.edu // Try to find the entry 2123804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2133804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2143811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2153804Ssaidi@eecs.umich.edu return NULL; 2163804Ssaidi@eecs.umich.edu } 2173804Ssaidi@eecs.umich.edu 2183804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2193804Ssaidi@eecs.umich.edu t = i->second; 2203826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2213826Ssaidi@eecs.umich.edu t->pte.size()); 2224070Ssaidi@eecs.umich.edu 2235555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2245555Snate@binkert.org // one from virttophys() 2254070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2263804Ssaidi@eecs.umich.edu t->used = true; 2273804Ssaidi@eecs.umich.edu usedEntries++; 2283804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2293804Ssaidi@eecs.umich.edu clearUsedBits(); 2303804Ssaidi@eecs.umich.edu t->used = true; 2313804Ssaidi@eecs.umich.edu usedEntries++; 2323804Ssaidi@eecs.umich.edu } 2333804Ssaidi@eecs.umich.edu } 2343804Ssaidi@eecs.umich.edu 2353804Ssaidi@eecs.umich.edu return t; 2363804Ssaidi@eecs.umich.edu} 2373804Ssaidi@eecs.umich.edu 2383826Ssaidi@eecs.umich.eduvoid 2393826Ssaidi@eecs.umich.eduTLB::dumpAll() 2403826Ssaidi@eecs.umich.edu{ 2413863Ssaidi@eecs.umich.edu MapIter i; 2423826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2433826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2443826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2453826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2463826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2473826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2483826Ssaidi@eecs.umich.edu } 2493826Ssaidi@eecs.umich.edu } 2503826Ssaidi@eecs.umich.edu} 2513804Ssaidi@eecs.umich.edu 2523804Ssaidi@eecs.umich.eduvoid 2533804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2543804Ssaidi@eecs.umich.edu{ 2553804Ssaidi@eecs.umich.edu TlbRange tr; 2563804Ssaidi@eecs.umich.edu MapIter i; 2573804Ssaidi@eecs.umich.edu 2583863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2593863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2603863Ssaidi@eecs.umich.edu 2613836Ssaidi@eecs.umich.edu cacheValid = false; 2623836Ssaidi@eecs.umich.edu 2633804Ssaidi@eecs.umich.edu // Assemble full address structure 2643804Ssaidi@eecs.umich.edu tr.va = va; 2655312Sgblack@eecs.umich.edu tr.size = 1; 2663804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2673804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2683804Ssaidi@eecs.umich.edu tr.real = real; 2693804Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2713804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2723804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2733863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2743804Ssaidi@eecs.umich.edu i->second->valid = false; 2753804Ssaidi@eecs.umich.edu if (i->second->used) { 2763804Ssaidi@eecs.umich.edu i->second->used = false; 2773804Ssaidi@eecs.umich.edu usedEntries--; 2783804Ssaidi@eecs.umich.edu } 2793881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2803804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2813804Ssaidi@eecs.umich.edu } 2823804Ssaidi@eecs.umich.edu} 2833804Ssaidi@eecs.umich.edu 2843804Ssaidi@eecs.umich.eduvoid 2853804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2863804Ssaidi@eecs.umich.edu{ 2873863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2883863Ssaidi@eecs.umich.edu partition_id, context_id); 2893836Ssaidi@eecs.umich.edu cacheValid = false; 2905555Snate@binkert.org for (int x = 0; x < size; x++) { 2913804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2923804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2933881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 2943881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2953881Ssaidi@eecs.umich.edu } 2963804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2973804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2983804Ssaidi@eecs.umich.edu tlb[x].used = false; 2993804Ssaidi@eecs.umich.edu usedEntries--; 3003804Ssaidi@eecs.umich.edu } 3013804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3023804Ssaidi@eecs.umich.edu } 3033804Ssaidi@eecs.umich.edu } 3043804Ssaidi@eecs.umich.edu} 3053804Ssaidi@eecs.umich.edu 3063804Ssaidi@eecs.umich.eduvoid 3073804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3083804Ssaidi@eecs.umich.edu{ 3093863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3103836Ssaidi@eecs.umich.edu cacheValid = false; 3115555Snate@binkert.org for (int x = 0; x < size; x++) { 3125288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3135288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3145288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3153804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3163804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3173804Ssaidi@eecs.umich.edu tlb[x].used = false; 3183804Ssaidi@eecs.umich.edu usedEntries--; 3193804Ssaidi@eecs.umich.edu } 3203804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3213804Ssaidi@eecs.umich.edu } 3223804Ssaidi@eecs.umich.edu } 3233804Ssaidi@eecs.umich.edu} 3243804Ssaidi@eecs.umich.edu 3253804Ssaidi@eecs.umich.eduvoid 3269423SAndreas.Sandberg@arm.comTLB::flushAll() 3273804Ssaidi@eecs.umich.edu{ 3283836Ssaidi@eecs.umich.edu cacheValid = false; 3295555Snate@binkert.org lookupTable.clear(); 3303836Ssaidi@eecs.umich.edu 3315555Snate@binkert.org for (int x = 0; x < size; x++) { 3323881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3333881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3343804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3353907Ssaidi@eecs.umich.edu tlb[x].used = false; 3363804Ssaidi@eecs.umich.edu } 3373804Ssaidi@eecs.umich.edu usedEntries = 0; 3383804Ssaidi@eecs.umich.edu} 3393804Ssaidi@eecs.umich.edu 3403804Ssaidi@eecs.umich.eduuint64_t 3415555Snate@binkert.orgTLB::TteRead(int entry) 3425555Snate@binkert.org{ 3433881Ssaidi@eecs.umich.edu if (entry >= size) 3443881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3453881Ssaidi@eecs.umich.edu 3463804Ssaidi@eecs.umich.edu assert(entry < size); 3473881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3483881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3493881Ssaidi@eecs.umich.edu else 3503881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3513804Ssaidi@eecs.umich.edu} 3523804Ssaidi@eecs.umich.edu 3533804Ssaidi@eecs.umich.eduuint64_t 3545555Snate@binkert.orgTLB::TagRead(int entry) 3555555Snate@binkert.org{ 3563804Ssaidi@eecs.umich.edu assert(entry < size); 3573804Ssaidi@eecs.umich.edu uint64_t tag; 3583881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3593881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3603804Ssaidi@eecs.umich.edu 3613881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3623881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3633881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3643804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3653804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3663804Ssaidi@eecs.umich.edu return tag; 3673804Ssaidi@eecs.umich.edu} 3683804Ssaidi@eecs.umich.edu 3693804Ssaidi@eecs.umich.edubool 3703804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3713804Ssaidi@eecs.umich.edu{ 3723804Ssaidi@eecs.umich.edu if (am) 3733804Ssaidi@eecs.umich.edu return true; 3743804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3753804Ssaidi@eecs.umich.edu return false; 3763804Ssaidi@eecs.umich.edu return true; 3773804Ssaidi@eecs.umich.edu} 3783804Ssaidi@eecs.umich.edu 3793804Ssaidi@eecs.umich.eduvoid 3804990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3813804Ssaidi@eecs.umich.edu{ 3823804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3833804Ssaidi@eecs.umich.edu sfsr = 0x3; 3843804Ssaidi@eecs.umich.edu else 3853804Ssaidi@eecs.umich.edu sfsr = 1; 3863804Ssaidi@eecs.umich.edu 3873804Ssaidi@eecs.umich.edu if (write) 3883804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3893804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3903804Ssaidi@eecs.umich.edu if (se) 3913804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3923804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3933804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3943804Ssaidi@eecs.umich.edu} 3953804Ssaidi@eecs.umich.edu 3963826Ssaidi@eecs.umich.eduvoid 3974990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 3983826Ssaidi@eecs.umich.edu{ 3993916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4003916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4013916Ssaidi@eecs.umich.edu 4024990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4033826Ssaidi@eecs.umich.edu} 4043804Ssaidi@eecs.umich.edu 4053804Ssaidi@eecs.umich.eduvoid 4066022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4073804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4083804Ssaidi@eecs.umich.edu{ 4096022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4103811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4114990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4124990Sgblack@eecs.umich.edu sfar = a; 4133804Ssaidi@eecs.umich.edu} 4143804Ssaidi@eecs.umich.edu 4153804Ssaidi@eecs.umich.eduFault 4166022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 4173804Ssaidi@eecs.umich.edu{ 4184172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4193833Ssaidi@eecs.umich.edu 4203836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4213836Ssaidi@eecs.umich.edu TlbEntry *e; 4223836Ssaidi@eecs.umich.edu 4233836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4243836Ssaidi@eecs.umich.edu 4253836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4263836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4273836Ssaidi@eecs.umich.edu 4283836Ssaidi@eecs.umich.edu // Be fast if we can! 4293836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4306022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4316022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4326022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4336022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4345555Snate@binkert.org return NoFault; 4353836Ssaidi@eecs.umich.edu } 4363836Ssaidi@eecs.umich.edu } else { 4373836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4383836Ssaidi@eecs.umich.edu return NoFault; 4393836Ssaidi@eecs.umich.edu } 4403836Ssaidi@eecs.umich.edu } 4413836Ssaidi@eecs.umich.edu 4423833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4433833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4443833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4453833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4463833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4473833Ssaidi@eecs.umich.edu 4483833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4493833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4503833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4513804Ssaidi@eecs.umich.edu int context; 4523804Ssaidi@eecs.umich.edu ContextType ct; 4533804Ssaidi@eecs.umich.edu int asi; 4543804Ssaidi@eecs.umich.edu bool real = false; 4553804Ssaidi@eecs.umich.edu 4563833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4573833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4583811Ssaidi@eecs.umich.edu 4593804Ssaidi@eecs.umich.edu if (tl > 0) { 4603804Ssaidi@eecs.umich.edu asi = ASI_N; 4613804Ssaidi@eecs.umich.edu ct = Nucleus; 4623804Ssaidi@eecs.umich.edu context = 0; 4633804Ssaidi@eecs.umich.edu } else { 4643804Ssaidi@eecs.umich.edu asi = ASI_P; 4653804Ssaidi@eecs.umich.edu ct = Primary; 4663833Ssaidi@eecs.umich.edu context = pri_context; 4673804Ssaidi@eecs.umich.edu } 4683804Ssaidi@eecs.umich.edu 4693833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4703836Ssaidi@eecs.umich.edu cacheValid = true; 4713836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4726022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4733836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4743804Ssaidi@eecs.umich.edu return NoFault; 4753804Ssaidi@eecs.umich.edu } 4763804Ssaidi@eecs.umich.edu 4773836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4783836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4794990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 4803804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4813804Ssaidi@eecs.umich.edu } 4823804Ssaidi@eecs.umich.edu 4833804Ssaidi@eecs.umich.edu if (addr_mask) 4843804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4853804Ssaidi@eecs.umich.edu 4863804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4874990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 4883804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4893804Ssaidi@eecs.umich.edu } 4903804Ssaidi@eecs.umich.edu 4913833Ssaidi@eecs.umich.edu if (!lsu_im) { 4923836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4933804Ssaidi@eecs.umich.edu real = true; 4943804Ssaidi@eecs.umich.edu context = 0; 4953804Ssaidi@eecs.umich.edu } else { 4963804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4973804Ssaidi@eecs.umich.edu } 4983804Ssaidi@eecs.umich.edu 4993804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5004990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5018751Sgblack@eecs.umich.edu if (real) { 5023804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5038751Sgblack@eecs.umich.edu } else { 5048751Sgblack@eecs.umich.edu if (FullSystem) 5058751Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5068751Sgblack@eecs.umich.edu else 5078751Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5088751Sgblack@eecs.umich.edu } 5093804Ssaidi@eecs.umich.edu } 5103804Ssaidi@eecs.umich.edu 5113804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5123804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5134990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5144990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5153804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5163804Ssaidi@eecs.umich.edu } 5173804Ssaidi@eecs.umich.edu 5183836Ssaidi@eecs.umich.edu // cache translation date for next translation 5193836Ssaidi@eecs.umich.edu cacheValid = true; 5203836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5216022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5223836Ssaidi@eecs.umich.edu 5235555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5243836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5253804Ssaidi@eecs.umich.edu return NoFault; 5263804Ssaidi@eecs.umich.edu} 5273804Ssaidi@eecs.umich.edu 5283804Ssaidi@eecs.umich.eduFault 5296022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 5303804Ssaidi@eecs.umich.edu{ 5315555Snate@binkert.org /* 5325555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5335555Snate@binkert.org * it faster! 5345555Snate@binkert.org */ 5354172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5363836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5373836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5383836Ssaidi@eecs.umich.edu ASI asi; 5393836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5403836Ssaidi@eecs.umich.edu bool implicit = false; 5413836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5425570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5433833Ssaidi@eecs.umich.edu 5443836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5453836Ssaidi@eecs.umich.edu vaddr, size, asi); 5463836Ssaidi@eecs.umich.edu 5473929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5483929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5493929Ssaidi@eecs.umich.edu freeList.size()); 5503836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5513836Ssaidi@eecs.umich.edu implicit = true; 5523836Ssaidi@eecs.umich.edu 5534996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5544996Sgblack@eecs.umich.edu // trap later 5554996Sgblack@eecs.umich.edu if (!unaligned) { 5564996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5574996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5584996Sgblack@eecs.umich.edu return NoFault; 5594996Sgblack@eecs.umich.edu } 5604996Sgblack@eecs.umich.edu 5614996Sgblack@eecs.umich.edu // Be fast if we can! 5624996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5634996Sgblack@eecs.umich.edu 5644996Sgblack@eecs.umich.edu 5654996Sgblack@eecs.umich.edu 5664996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5674996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5684996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5694996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5704996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5714996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5725555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5735555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5745736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5755555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5765555Snate@binkert.org return NoFault; 5774996Sgblack@eecs.umich.edu } // if matched 5784996Sgblack@eecs.umich.edu } // if cache entry valid 5794996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5804996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5814996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5824996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 5834996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5844996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5855555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5865555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5875736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5885555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5895555Snate@binkert.org return NoFault; 5904996Sgblack@eecs.umich.edu } // if matched 5914996Sgblack@eecs.umich.edu } // if cache entry valid 5924996Sgblack@eecs.umich.edu } 5933836Ssaidi@eecs.umich.edu } 5943836Ssaidi@eecs.umich.edu 5953833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 5963833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 5973833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 5983833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 5993833Ssaidi@eecs.umich.edu 6003833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6013833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6023833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6033916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6043833Ssaidi@eecs.umich.edu 6053804Ssaidi@eecs.umich.edu bool real = false; 6063832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6073832Ssaidi@eecs.umich.edu int context = 0; 6083804Ssaidi@eecs.umich.edu 6093804Ssaidi@eecs.umich.edu TlbEntry *e; 6103804Ssaidi@eecs.umich.edu 6113833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6125555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6133804Ssaidi@eecs.umich.edu 6143804Ssaidi@eecs.umich.edu if (implicit) { 6153804Ssaidi@eecs.umich.edu if (tl > 0) { 6163804Ssaidi@eecs.umich.edu asi = ASI_N; 6173804Ssaidi@eecs.umich.edu ct = Nucleus; 6183804Ssaidi@eecs.umich.edu context = 0; 6193804Ssaidi@eecs.umich.edu } else { 6203804Ssaidi@eecs.umich.edu asi = ASI_P; 6213804Ssaidi@eecs.umich.edu ct = Primary; 6223833Ssaidi@eecs.umich.edu context = pri_context; 6233804Ssaidi@eecs.umich.edu } 6243910Ssaidi@eecs.umich.edu } else { 6253804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6267741Sgblack@eecs.umich.edu if (!priv && !hpriv && !asiIsUnPriv(asi)) { 6273804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6284990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6293804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6303804Ssaidi@eecs.umich.edu } 6313910Ssaidi@eecs.umich.edu 6327741Sgblack@eecs.umich.edu if (!hpriv && asiIsHPriv(asi)) { 6334990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6343804Ssaidi@eecs.umich.edu return new DataAccessException; 6353804Ssaidi@eecs.umich.edu } 6363804Ssaidi@eecs.umich.edu 6377741Sgblack@eecs.umich.edu if (asiIsPrimary(asi)) { 6383910Ssaidi@eecs.umich.edu context = pri_context; 6393910Ssaidi@eecs.umich.edu ct = Primary; 6407741Sgblack@eecs.umich.edu } else if (asiIsSecondary(asi)) { 6413910Ssaidi@eecs.umich.edu context = sec_context; 6423910Ssaidi@eecs.umich.edu ct = Secondary; 6437741Sgblack@eecs.umich.edu } else if (asiIsNucleus(asi)) { 6443910Ssaidi@eecs.umich.edu ct = Nucleus; 6453910Ssaidi@eecs.umich.edu context = 0; 6463910Ssaidi@eecs.umich.edu } else { // ???? 6473910Ssaidi@eecs.umich.edu ct = Primary; 6483910Ssaidi@eecs.umich.edu context = pri_context; 6493910Ssaidi@eecs.umich.edu } 6503902Ssaidi@eecs.umich.edu } 6513804Ssaidi@eecs.umich.edu 6523926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6537741Sgblack@eecs.umich.edu if (asiIsLittle(asi)) 6543804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6554989Sgblack@eecs.umich.edu 6564989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6577741Sgblack@eecs.umich.edu // load differs from a regular one, other than what happens concerning 6587741Sgblack@eecs.umich.edu // nfo and e bits in the TTE 6597741Sgblack@eecs.umich.edu// if (asiIsNoFault(asi)) 6604989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6613856Ssaidi@eecs.umich.edu 6627741Sgblack@eecs.umich.edu if (asiIsPartialStore(asi)) 6633804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6644103Ssaidi@eecs.umich.edu 6657741Sgblack@eecs.umich.edu if (asiIsCmt(asi)) 6664191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6674191Ssaidi@eecs.umich.edu 6687741Sgblack@eecs.umich.edu if (asiIsInterrupt(asi)) 6694103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6707741Sgblack@eecs.umich.edu if (asiIsMmu(asi)) 6713804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6727741Sgblack@eecs.umich.edu if (asiIsScratchPad(asi)) 6733804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6747741Sgblack@eecs.umich.edu if (asiIsQueue(asi)) 6753824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6767741Sgblack@eecs.umich.edu if (asiIsSparcError(asi)) 6773825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6783823Ssaidi@eecs.umich.edu 6797741Sgblack@eecs.umich.edu if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 6807741Sgblack@eecs.umich.edu !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 6813823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6823804Ssaidi@eecs.umich.edu } 6833804Ssaidi@eecs.umich.edu 6843826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6854996Sgblack@eecs.umich.edu if (unaligned) { 6864990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 6873826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6883826Ssaidi@eecs.umich.edu } 6893826Ssaidi@eecs.umich.edu 6903826Ssaidi@eecs.umich.edu if (addr_mask) 6913826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6923826Ssaidi@eecs.umich.edu 6933826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 6944990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 6953826Ssaidi@eecs.umich.edu return new DataAccessException; 6963826Ssaidi@eecs.umich.edu } 6973826Ssaidi@eecs.umich.edu 6987741Sgblack@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 6993804Ssaidi@eecs.umich.edu real = true; 7003804Ssaidi@eecs.umich.edu context = 0; 7015555Snate@binkert.org } 7023804Ssaidi@eecs.umich.edu 7037741Sgblack@eecs.umich.edu if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 7043836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7053804Ssaidi@eecs.umich.edu return NoFault; 7063804Ssaidi@eecs.umich.edu } 7073804Ssaidi@eecs.umich.edu 7083836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7093804Ssaidi@eecs.umich.edu 7103804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7114990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7123811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7138751Sgblack@eecs.umich.edu if (real) { 7143804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7158751Sgblack@eecs.umich.edu } else { 7168751Sgblack@eecs.umich.edu if (FullSystem) 7178751Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss; 7188751Sgblack@eecs.umich.edu else 7198751Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7208751Sgblack@eecs.umich.edu } 7213804Ssaidi@eecs.umich.edu 7223804Ssaidi@eecs.umich.edu } 7233804Ssaidi@eecs.umich.edu 7243928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7254990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7264990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7273928Ssaidi@eecs.umich.edu return new DataAccessException; 7283928Ssaidi@eecs.umich.edu } 7293804Ssaidi@eecs.umich.edu 7303804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7314990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7324990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7333804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7343804Ssaidi@eecs.umich.edu } 7353804Ssaidi@eecs.umich.edu 7367741Sgblack@eecs.umich.edu if (e->pte.nofault() && !asiIsNoFault(asi)) { 7374990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7384990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7393804Ssaidi@eecs.umich.edu return new DataAccessException; 7403804Ssaidi@eecs.umich.edu } 7413804Ssaidi@eecs.umich.edu 7427741Sgblack@eecs.umich.edu if (e->pte.sideffect() && asiIsNoFault(asi)) { 7434990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7444990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7453928Ssaidi@eecs.umich.edu return new DataAccessException; 7463928Ssaidi@eecs.umich.edu } 7473928Ssaidi@eecs.umich.edu 7484090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7495736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 7503804Ssaidi@eecs.umich.edu 7513836Ssaidi@eecs.umich.edu // cache translation date for next translation 7523836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7533881Ssaidi@eecs.umich.edu if (!cacheValid) { 7543881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7553881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7563881Ssaidi@eecs.umich.edu } 7573881Ssaidi@eecs.umich.edu 7583836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7593836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7603836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7613836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7623836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7633836Ssaidi@eecs.umich.edu if (implicit) 7643836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7653836Ssaidi@eecs.umich.edu } 7663881Ssaidi@eecs.umich.edu cacheValid = true; 7675555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7683836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7693804Ssaidi@eecs.umich.edu return NoFault; 7704103Ssaidi@eecs.umich.edu 7713806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7724103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7734103Ssaidi@eecs.umich.edu if (!hpriv) { 7744990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7754103Ssaidi@eecs.umich.edu if (priv) 7764103Ssaidi@eecs.umich.edu return new DataAccessException; 7774103Ssaidi@eecs.umich.edu else 7784103Ssaidi@eecs.umich.edu return new PrivilegedAction; 7794103Ssaidi@eecs.umich.edu } 7804103Ssaidi@eecs.umich.edu 7815570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 7825570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 7834990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7844103Ssaidi@eecs.umich.edu return new DataAccessException; 7854103Ssaidi@eecs.umich.edu } 7864103Ssaidi@eecs.umich.edu 7874103Ssaidi@eecs.umich.edu goto regAccessOk; 7884103Ssaidi@eecs.umich.edu 7893804Ssaidi@eecs.umich.edu 7903806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7913806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7924990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7933806Ssaidi@eecs.umich.edu return new DataAccessException; 7943806Ssaidi@eecs.umich.edu } 7953824Ssaidi@eecs.umich.edu goto regAccessOk; 7963824Ssaidi@eecs.umich.edu 7973824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7983824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7994990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8003824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8013824Ssaidi@eecs.umich.edu } 8025570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8034990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8043824Ssaidi@eecs.umich.edu return new DataAccessException; 8053824Ssaidi@eecs.umich.edu } 8063824Ssaidi@eecs.umich.edu goto regAccessOk; 8073824Ssaidi@eecs.umich.edu 8083825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8093825Ssaidi@eecs.umich.edu if (!hpriv) { 8104990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8114070Ssaidi@eecs.umich.edu if (priv) 8123825Ssaidi@eecs.umich.edu return new DataAccessException; 8134070Ssaidi@eecs.umich.edu else 8143825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8153825Ssaidi@eecs.umich.edu } 8163825Ssaidi@eecs.umich.edu goto regAccessOk; 8173825Ssaidi@eecs.umich.edu 8183825Ssaidi@eecs.umich.edu 8193824Ssaidi@eecs.umich.eduregAccessOk: 8203804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8213811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8228105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 8233806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8243806Ssaidi@eecs.umich.edu return NoFault; 8253804Ssaidi@eecs.umich.edu}; 8263804Ssaidi@eecs.umich.edu 8276022Sgblack@eecs.umich.eduFault 8286023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 8296022Sgblack@eecs.umich.edu{ 8306023Snate@binkert.org if (mode == Execute) 8316022Sgblack@eecs.umich.edu return translateInst(req, tc); 8326022Sgblack@eecs.umich.edu else 8336023Snate@binkert.org return translateData(req, tc, mode == Write); 8346022Sgblack@eecs.umich.edu} 8356022Sgblack@eecs.umich.edu 8365894Sgblack@eecs.umich.eduvoid 8376022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 8386023Snate@binkert.org Translation *translation, Mode mode) 8395894Sgblack@eecs.umich.edu{ 8405894Sgblack@eecs.umich.edu assert(translation); 8416023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8425894Sgblack@eecs.umich.edu} 8435894Sgblack@eecs.umich.edu 8448888Sgeoffrey.blake@arm.comFault 8458888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 8468888Sgeoffrey.blake@arm.com{ 8478888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 8488888Sgeoffrey.blake@arm.com return NoFault; 8498888Sgeoffrey.blake@arm.com} 8508888Sgeoffrey.blake@arm.com 8519738Sandreas@sandberg.pp.seFault 8529738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 8539738Sandreas@sandberg.pp.se{ 8549738Sandreas@sandberg.pp.se return NoFault; 8559738Sandreas@sandberg.pp.se} 8569738Sandreas@sandberg.pp.se 8579180Sandreas.hansson@arm.comCycles 8586022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8593806Ssaidi@eecs.umich.edu{ 8603823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8613823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8624070Ssaidi@eecs.umich.edu uint64_t temp; 8633823Ssaidi@eecs.umich.edu 8643823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8653823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8663823Ssaidi@eecs.umich.edu 8676022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 8684990Sgblack@eecs.umich.edu 8693823Ssaidi@eecs.umich.edu switch (asi) { 8703823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8713823Ssaidi@eecs.umich.edu assert(va == 0); 8724172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8733823Ssaidi@eecs.umich.edu break; 8743823Ssaidi@eecs.umich.edu case ASI_MMU: 8753823Ssaidi@eecs.umich.edu switch (va) { 8763823Ssaidi@eecs.umich.edu case 0x8: 8774172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8783823Ssaidi@eecs.umich.edu break; 8793823Ssaidi@eecs.umich.edu case 0x10: 8804172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu default: 8833823Ssaidi@eecs.umich.edu goto doMmuReadError; 8843823Ssaidi@eecs.umich.edu } 8853823Ssaidi@eecs.umich.edu break; 8863824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8874172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8883824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8893824Ssaidi@eecs.umich.edu break; 8903823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8913823Ssaidi@eecs.umich.edu assert(va == 0); 8924990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8933823Ssaidi@eecs.umich.edu break; 8943823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8953823Ssaidi@eecs.umich.edu assert(va == 0); 8964990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8973823Ssaidi@eecs.umich.edu break; 8983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8993823Ssaidi@eecs.umich.edu assert(va == 0); 9004990Sgblack@eecs.umich.edu pkt->set(c0_config); 9013823Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9033823Ssaidi@eecs.umich.edu assert(va == 0); 9044990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9053823Ssaidi@eecs.umich.edu break; 9063823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9073823Ssaidi@eecs.umich.edu assert(va == 0); 9084990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9093823Ssaidi@eecs.umich.edu break; 9103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9113823Ssaidi@eecs.umich.edu assert(va == 0); 9124990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9133823Ssaidi@eecs.umich.edu break; 9143823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9153823Ssaidi@eecs.umich.edu assert(va == 0); 9164990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9173823Ssaidi@eecs.umich.edu break; 9183823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9193823Ssaidi@eecs.umich.edu assert(va == 0); 9204990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9213823Ssaidi@eecs.umich.edu break; 9223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9233823Ssaidi@eecs.umich.edu assert(va == 0); 9244990Sgblack@eecs.umich.edu pkt->set(cx_config); 9253823Ssaidi@eecs.umich.edu break; 9263823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9273823Ssaidi@eecs.umich.edu assert(va == 0); 9284990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9293823Ssaidi@eecs.umich.edu break; 9303823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9313823Ssaidi@eecs.umich.edu assert(va == 0); 9324990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9333823Ssaidi@eecs.umich.edu break; 9343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9353823Ssaidi@eecs.umich.edu assert(va == 0); 9364990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9373823Ssaidi@eecs.umich.edu break; 9383826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9393912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9403826Ssaidi@eecs.umich.edu break; 9413823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9423823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9434172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9443823Ssaidi@eecs.umich.edu break; 9453826Ssaidi@eecs.umich.edu case ASI_IMMU: 9463826Ssaidi@eecs.umich.edu switch (va) { 9473833Ssaidi@eecs.umich.edu case 0x0: 9484990Sgblack@eecs.umich.edu temp = itb->tag_access; 9493833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9503833Ssaidi@eecs.umich.edu break; 9513906Ssaidi@eecs.umich.edu case 0x18: 9524990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9533906Ssaidi@eecs.umich.edu break; 9543826Ssaidi@eecs.umich.edu case 0x30: 9554990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9563826Ssaidi@eecs.umich.edu break; 9573826Ssaidi@eecs.umich.edu default: 9583826Ssaidi@eecs.umich.edu goto doMmuReadError; 9593826Ssaidi@eecs.umich.edu } 9603826Ssaidi@eecs.umich.edu break; 9613823Ssaidi@eecs.umich.edu case ASI_DMMU: 9623823Ssaidi@eecs.umich.edu switch (va) { 9633833Ssaidi@eecs.umich.edu case 0x0: 9644990Sgblack@eecs.umich.edu temp = tag_access; 9653833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9663833Ssaidi@eecs.umich.edu break; 9673906Ssaidi@eecs.umich.edu case 0x18: 9684990Sgblack@eecs.umich.edu pkt->set(sfsr); 9693906Ssaidi@eecs.umich.edu break; 9703906Ssaidi@eecs.umich.edu case 0x20: 9714990Sgblack@eecs.umich.edu pkt->set(sfar); 9723906Ssaidi@eecs.umich.edu break; 9733826Ssaidi@eecs.umich.edu case 0x30: 9744990Sgblack@eecs.umich.edu pkt->set(tag_access); 9753826Ssaidi@eecs.umich.edu break; 9763823Ssaidi@eecs.umich.edu case 0x80: 9774172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9783823Ssaidi@eecs.umich.edu break; 9793823Ssaidi@eecs.umich.edu default: 9803823Ssaidi@eecs.umich.edu goto doMmuReadError; 9813823Ssaidi@eecs.umich.edu } 9823823Ssaidi@eecs.umich.edu break; 9833833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9844070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9854990Sgblack@eecs.umich.edu tag_access, 9864990Sgblack@eecs.umich.edu c0_tsb_ps0, 9874990Sgblack@eecs.umich.edu c0_config, 9884990Sgblack@eecs.umich.edu cx_tsb_ps0, 9894990Sgblack@eecs.umich.edu cx_config)); 9903833Ssaidi@eecs.umich.edu break; 9913833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9924070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9934990Sgblack@eecs.umich.edu tag_access, 9944990Sgblack@eecs.umich.edu c0_tsb_ps1, 9954990Sgblack@eecs.umich.edu c0_config, 9964990Sgblack@eecs.umich.edu cx_tsb_ps1, 9974990Sgblack@eecs.umich.edu cx_config)); 9983833Ssaidi@eecs.umich.edu break; 9993899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10004070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10014990Sgblack@eecs.umich.edu itb->tag_access, 10024990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10034990Sgblack@eecs.umich.edu itb->c0_config, 10044990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10054990Sgblack@eecs.umich.edu itb->cx_config)); 10063899Ssaidi@eecs.umich.edu break; 10073899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10084070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10094990Sgblack@eecs.umich.edu itb->tag_access, 10104990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10114990Sgblack@eecs.umich.edu itb->c0_config, 10124990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10134990Sgblack@eecs.umich.edu itb->cx_config)); 10143899Ssaidi@eecs.umich.edu break; 10154103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10165646Sgblack@eecs.umich.edu { 10175646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10185646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10195646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10205646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10215646Sgblack@eecs.umich.edu } 10224103Ssaidi@eecs.umich.edu break; 10234103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10245646Sgblack@eecs.umich.edu { 10255646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10265646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10275646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10285646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 10295704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 10305646Sgblack@eecs.umich.edu pkt->set(temp); 10315646Sgblack@eecs.umich.edu } 10324103Ssaidi@eecs.umich.edu break; 10333823Ssaidi@eecs.umich.edu default: 10343823Ssaidi@eecs.umich.edudoMmuReadError: 10353823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10363823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10373823Ssaidi@eecs.umich.edu } 10384870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10399180Sandreas.hansson@arm.com return Cycles(1); 10403806Ssaidi@eecs.umich.edu} 10413806Ssaidi@eecs.umich.edu 10429180Sandreas.hansson@arm.comCycles 10436022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10443806Ssaidi@eecs.umich.edu{ 10457518Sgblack@eecs.umich.edu uint64_t data = pkt->get<uint64_t>(); 10463823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10473823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10483823Ssaidi@eecs.umich.edu 10493826Ssaidi@eecs.umich.edu Addr ta_insert; 10503826Ssaidi@eecs.umich.edu Addr va_insert; 10513826Ssaidi@eecs.umich.edu Addr ct_insert; 10523826Ssaidi@eecs.umich.edu int part_insert; 10533826Ssaidi@eecs.umich.edu int entry_insert = -1; 10543826Ssaidi@eecs.umich.edu bool real_insert; 10553863Ssaidi@eecs.umich.edu bool ignore; 10563863Ssaidi@eecs.umich.edu int part_id; 10573863Ssaidi@eecs.umich.edu int ctx_id; 10583826Ssaidi@eecs.umich.edu PageTableEntry pte; 10593826Ssaidi@eecs.umich.edu 10603825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10613823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10623823Ssaidi@eecs.umich.edu 10636022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 10644990Sgblack@eecs.umich.edu 10653823Ssaidi@eecs.umich.edu switch (asi) { 10663823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10673823Ssaidi@eecs.umich.edu assert(va == 0); 10684172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10693823Ssaidi@eecs.umich.edu break; 10703823Ssaidi@eecs.umich.edu case ASI_MMU: 10713823Ssaidi@eecs.umich.edu switch (va) { 10723823Ssaidi@eecs.umich.edu case 0x8: 10734172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10743823Ssaidi@eecs.umich.edu break; 10753823Ssaidi@eecs.umich.edu case 0x10: 10764172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10773823Ssaidi@eecs.umich.edu break; 10783823Ssaidi@eecs.umich.edu default: 10793823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10803823Ssaidi@eecs.umich.edu } 10813823Ssaidi@eecs.umich.edu break; 10823824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10833825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10844172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10853824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10863824Ssaidi@eecs.umich.edu break; 10873823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10883823Ssaidi@eecs.umich.edu assert(va == 0); 10894990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10903823Ssaidi@eecs.umich.edu break; 10913823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10923823Ssaidi@eecs.umich.edu assert(va == 0); 10934990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10943823Ssaidi@eecs.umich.edu break; 10953823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10963823Ssaidi@eecs.umich.edu assert(va == 0); 10974990Sgblack@eecs.umich.edu c0_config = data; 10983823Ssaidi@eecs.umich.edu break; 10993823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 11003823Ssaidi@eecs.umich.edu assert(va == 0); 11014990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 11023823Ssaidi@eecs.umich.edu break; 11033823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11043823Ssaidi@eecs.umich.edu assert(va == 0); 11054990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11063823Ssaidi@eecs.umich.edu break; 11073823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11083823Ssaidi@eecs.umich.edu assert(va == 0); 11094990Sgblack@eecs.umich.edu itb->c0_config = data; 11103823Ssaidi@eecs.umich.edu break; 11113823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11123823Ssaidi@eecs.umich.edu assert(va == 0); 11134990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11143823Ssaidi@eecs.umich.edu break; 11153823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11163823Ssaidi@eecs.umich.edu assert(va == 0); 11174990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11183823Ssaidi@eecs.umich.edu break; 11193823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11203823Ssaidi@eecs.umich.edu assert(va == 0); 11214990Sgblack@eecs.umich.edu cx_config = data; 11223823Ssaidi@eecs.umich.edu break; 11233823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11243823Ssaidi@eecs.umich.edu assert(va == 0); 11254990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11263823Ssaidi@eecs.umich.edu break; 11273823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11283823Ssaidi@eecs.umich.edu assert(va == 0); 11294990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11303823Ssaidi@eecs.umich.edu break; 11313823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11323823Ssaidi@eecs.umich.edu assert(va == 0); 11334990Sgblack@eecs.umich.edu itb->cx_config = data; 11343823Ssaidi@eecs.umich.edu break; 11353825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11363825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11375823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11383825Ssaidi@eecs.umich.edu break; 11393823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11403823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11414172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11423823Ssaidi@eecs.umich.edu break; 11433826Ssaidi@eecs.umich.edu case ASI_IMMU: 11443826Ssaidi@eecs.umich.edu switch (va) { 11453906Ssaidi@eecs.umich.edu case 0x18: 11464990Sgblack@eecs.umich.edu itb->sfsr = data; 11473906Ssaidi@eecs.umich.edu break; 11483826Ssaidi@eecs.umich.edu case 0x30: 11493916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11504990Sgblack@eecs.umich.edu itb->tag_access = data; 11513826Ssaidi@eecs.umich.edu break; 11523826Ssaidi@eecs.umich.edu default: 11533826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11543826Ssaidi@eecs.umich.edu } 11553826Ssaidi@eecs.umich.edu break; 11563826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11573826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11583826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11593826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11604990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11613826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11623826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11634172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11643826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11653826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11663826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11673826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11683826Ssaidi@eecs.umich.edu pte, entry_insert); 11693826Ssaidi@eecs.umich.edu break; 11703826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11713826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11723826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11733826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11744990Sgblack@eecs.umich.edu ta_insert = tag_access; 11753826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11763826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11774172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11783826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11793826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11803826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11815555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11825555Snate@binkert.org entry_insert); 11833826Ssaidi@eecs.umich.edu break; 11843863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11853863Ssaidi@eecs.umich.edu ignore = false; 11863863Ssaidi@eecs.umich.edu ctx_id = -1; 11874172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11883863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11893863Ssaidi@eecs.umich.edu case 0: 11904172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11913863Ssaidi@eecs.umich.edu break; 11923863Ssaidi@eecs.umich.edu case 1: 11933863Ssaidi@eecs.umich.edu ignore = true; 11943863Ssaidi@eecs.umich.edu break; 11953863Ssaidi@eecs.umich.edu case 3: 11963863Ssaidi@eecs.umich.edu ctx_id = 0; 11973863Ssaidi@eecs.umich.edu break; 11983863Ssaidi@eecs.umich.edu default: 11993863Ssaidi@eecs.umich.edu ignore = true; 12003863Ssaidi@eecs.umich.edu } 12013863Ssaidi@eecs.umich.edu 12027741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12033863Ssaidi@eecs.umich.edu case 0: // demap page 12043863Ssaidi@eecs.umich.edu if (!ignore) 12053863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 12063863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 12073863Ssaidi@eecs.umich.edu break; 12087741Sgblack@eecs.umich.edu case 1: // demap context 12093863Ssaidi@eecs.umich.edu if (!ignore) 12103863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 12113863Ssaidi@eecs.umich.edu break; 12123863Ssaidi@eecs.umich.edu case 2: 12133863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12143863Ssaidi@eecs.umich.edu break; 12153863Ssaidi@eecs.umich.edu default: 12163863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12173863Ssaidi@eecs.umich.edu } 12183863Ssaidi@eecs.umich.edu break; 12193823Ssaidi@eecs.umich.edu case ASI_DMMU: 12203823Ssaidi@eecs.umich.edu switch (va) { 12213906Ssaidi@eecs.umich.edu case 0x18: 12224990Sgblack@eecs.umich.edu sfsr = data; 12233906Ssaidi@eecs.umich.edu break; 12243826Ssaidi@eecs.umich.edu case 0x30: 12253916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12264990Sgblack@eecs.umich.edu tag_access = data; 12273826Ssaidi@eecs.umich.edu break; 12283823Ssaidi@eecs.umich.edu case 0x80: 12294172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12303823Ssaidi@eecs.umich.edu break; 12313823Ssaidi@eecs.umich.edu default: 12323823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12333823Ssaidi@eecs.umich.edu } 12343823Ssaidi@eecs.umich.edu break; 12353863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12363863Ssaidi@eecs.umich.edu ignore = false; 12373863Ssaidi@eecs.umich.edu ctx_id = -1; 12384172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12393863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12403863Ssaidi@eecs.umich.edu case 0: 12414172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12423863Ssaidi@eecs.umich.edu break; 12433863Ssaidi@eecs.umich.edu case 1: 12444172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12453863Ssaidi@eecs.umich.edu break; 12463863Ssaidi@eecs.umich.edu case 3: 12473863Ssaidi@eecs.umich.edu ctx_id = 0; 12483863Ssaidi@eecs.umich.edu break; 12493863Ssaidi@eecs.umich.edu default: 12503863Ssaidi@eecs.umich.edu ignore = true; 12513863Ssaidi@eecs.umich.edu } 12523863Ssaidi@eecs.umich.edu 12537741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12543863Ssaidi@eecs.umich.edu case 0: // demap page 12553863Ssaidi@eecs.umich.edu if (!ignore) 12563863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12573863Ssaidi@eecs.umich.edu break; 12587741Sgblack@eecs.umich.edu case 1: // demap context 12593863Ssaidi@eecs.umich.edu if (!ignore) 12603863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12613863Ssaidi@eecs.umich.edu break; 12623863Ssaidi@eecs.umich.edu case 2: 12633863Ssaidi@eecs.umich.edu demapAll(part_id); 12643863Ssaidi@eecs.umich.edu break; 12653863Ssaidi@eecs.umich.edu default: 12663863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12673863Ssaidi@eecs.umich.edu } 12683863Ssaidi@eecs.umich.edu break; 12694103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12705646Sgblack@eecs.umich.edu { 12715646Sgblack@eecs.umich.edu int msb; 12725646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12735646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12745646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 12755646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 12765704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12775646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 12785704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 12795646Sgblack@eecs.umich.edu } 12804103Ssaidi@eecs.umich.edu } 12814103Ssaidi@eecs.umich.edu break; 12824103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12834103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12845704Snate@binkert.org postInterrupt(bits(data, 5, 0), 0); 12854103Ssaidi@eecs.umich.edu break; 12865555Snate@binkert.org default: 12873823Ssaidi@eecs.umich.edudoMmuWriteError: 12883823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12893823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12903823Ssaidi@eecs.umich.edu } 12914870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12929180Sandreas.hansson@arm.com return Cycles(1); 12933806Ssaidi@eecs.umich.edu} 12943806Ssaidi@eecs.umich.edu 12953804Ssaidi@eecs.umich.eduvoid 12966022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12974070Ssaidi@eecs.umich.edu{ 12984070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12996022Sgblack@eecs.umich.edu TLB * itb = tc->getITBPtr(); 13004070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 13014990Sgblack@eecs.umich.edu c0_tsb_ps0, 13024990Sgblack@eecs.umich.edu c0_config, 13034990Sgblack@eecs.umich.edu cx_tsb_ps0, 13044990Sgblack@eecs.umich.edu cx_config); 13054070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13064990Sgblack@eecs.umich.edu c0_tsb_ps1, 13074990Sgblack@eecs.umich.edu c0_config, 13084990Sgblack@eecs.umich.edu cx_tsb_ps1, 13094990Sgblack@eecs.umich.edu cx_config); 13104070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13114990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13124990Sgblack@eecs.umich.edu itb->c0_config, 13134990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13144990Sgblack@eecs.umich.edu itb->cx_config); 13154070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13164990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13174990Sgblack@eecs.umich.edu itb->c0_config, 13184990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13194990Sgblack@eecs.umich.edu itb->cx_config); 13204070Ssaidi@eecs.umich.edu} 13214070Ssaidi@eecs.umich.edu 13224070Ssaidi@eecs.umich.eduuint64_t 13236022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13244070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13254070Ssaidi@eecs.umich.edu{ 13264070Ssaidi@eecs.umich.edu uint64_t tsb; 13274070Ssaidi@eecs.umich.edu uint64_t config; 13284070Ssaidi@eecs.umich.edu 13294070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13304070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13314070Ssaidi@eecs.umich.edu config = c0_config; 13324070Ssaidi@eecs.umich.edu } else { 13334070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13344070Ssaidi@eecs.umich.edu config = cX_config; 13354070Ssaidi@eecs.umich.edu } 13364070Ssaidi@eecs.umich.edu 13374070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13384070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13394070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13404070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13414070Ssaidi@eecs.umich.edu 13424070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13434070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13444070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13454070Ssaidi@eecs.umich.edu 13464070Ssaidi@eecs.umich.edu return ptr; 13474070Ssaidi@eecs.umich.edu} 13484070Ssaidi@eecs.umich.edu 13494070Ssaidi@eecs.umich.eduvoid 13503804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13513804Ssaidi@eecs.umich.edu{ 13524000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13534000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13544000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13554000Ssaidi@eecs.umich.edu 13564000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13574000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13584000Ssaidi@eecs.umich.edu int cntr = 0; 13594000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13604000Ssaidi@eecs.umich.edu i = freeList.begin(); 13614000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13624000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13634000Ssaidi@eecs.umich.edu i++; 13644000Ssaidi@eecs.umich.edu } 13654000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13664000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13674000Ssaidi@eecs.umich.edu 13684990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13694990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13704990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13714990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13724990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13734990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13744990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13754990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13765276Ssaidi@eecs.umich.edu 13775276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13785276Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13795276Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13805276Ssaidi@eecs.umich.edu } 13816022Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 13823804Ssaidi@eecs.umich.edu} 13833804Ssaidi@eecs.umich.edu 13843804Ssaidi@eecs.umich.eduvoid 13853804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13863804Ssaidi@eecs.umich.edu{ 13874000Ssaidi@eecs.umich.edu int oldSize; 13884000Ssaidi@eecs.umich.edu 13894000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13904000Ssaidi@eecs.umich.edu if (oldSize != size) 13914000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13924000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13934000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13944000Ssaidi@eecs.umich.edu 13954000Ssaidi@eecs.umich.edu int cntr; 13964000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13974000Ssaidi@eecs.umich.edu 13984000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13994000Ssaidi@eecs.umich.edu freeList.clear(); 14004000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 14014000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 14024000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 14034000Ssaidi@eecs.umich.edu 14044990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14054990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14064990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14074990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14084990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14094990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14104990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14114990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14125276Ssaidi@eecs.umich.edu 14135276Ssaidi@eecs.umich.edu lookupTable.clear(); 14145276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14155276Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14165276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14175276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14185276Ssaidi@eecs.umich.edu 14195276Ssaidi@eecs.umich.edu } 14204990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14213804Ssaidi@eecs.umich.edu} 14223804Ssaidi@eecs.umich.edu 14237811Ssteve.reinhardt@amd.com} // namespace SparcISA 14244088Sbinkertn@umich.edu 14256022Sgblack@eecs.umich.eduSparcISA::TLB * 14266022Sgblack@eecs.umich.eduSparcTLBParams::create() 14273804Ssaidi@eecs.umich.edu{ 14286022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14293804Ssaidi@eecs.umich.edu} 1430