tlb.cc revision 8751 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/IPR.hh"
42#include "debug/TLB.hh"
43#include "mem/packet_access.hh"
44#include "mem/request.hh"
45#include "sim/full_system.hh"
46#include "sim/system.hh"
47
48/* @todo remove some of the magic constants.  -- ali
49 * */
50namespace SparcISA {
51
52TLB::TLB(const Params *p)
53    : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
54      cacheState(0), cacheValid(false)
55{
56    // To make this work you'll have to change the hypervisor and OS
57    if (size > 64)
58        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
59
60    tlb = new TlbEntry[size];
61    std::memset(tlb, 0, sizeof(TlbEntry) * size);
62
63    for (int x = 0; x < size; x++)
64        freeList.push_back(&tlb[x]);
65
66    c0_tsb_ps0 = 0;
67    c0_tsb_ps1 = 0;
68    c0_config = 0;
69    cx_tsb_ps0 = 0;
70    cx_tsb_ps1 = 0;
71    cx_config = 0;
72    sfsr = 0;
73    tag_access = 0;
74    sfar = 0;
75    cacheEntry[0] = NULL;
76    cacheEntry[1] = NULL;
77}
78
79void
80TLB::clearUsedBits()
81{
82    MapIter i;
83    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
84        TlbEntry *t = i->second;
85        if (!t->pte.locked()) {
86            t->used = false;
87            usedEntries--;
88        }
89    }
90}
91
92
93void
94TLB::insert(Addr va, int partition_id, int context_id, bool real,
95        const PageTableEntry& PTE, int entry)
96{
97    MapIter i;
98    TlbEntry *new_entry = NULL;
99//    TlbRange tr;
100    int x;
101
102    cacheValid = false;
103    va &= ~(PTE.size()-1);
104 /*   tr.va = va;
105    tr.size = PTE.size() - 1;
106    tr.contextId = context_id;
107    tr.partitionId = partition_id;
108    tr.real = real;
109*/
110
111    DPRINTF(TLB,
112        "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
113        va, PTE.paddr(), partition_id, context_id, (int)real, entry);
114
115    // Demap any entry that conflicts
116    for (x = 0; x < size; x++) {
117        if (tlb[x].range.real == real &&
118            tlb[x].range.partitionId == partition_id &&
119            tlb[x].range.va < va + PTE.size() - 1 &&
120            tlb[x].range.va + tlb[x].range.size >= va &&
121            (real || tlb[x].range.contextId == context_id ))
122        {
123            if (tlb[x].valid) {
124                freeList.push_front(&tlb[x]);
125                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
126
127                tlb[x].valid = false;
128                if (tlb[x].used) {
129                    tlb[x].used = false;
130                    usedEntries--;
131                }
132                lookupTable.erase(tlb[x].range);
133            }
134        }
135    }
136
137    if (entry != -1) {
138        assert(entry < size && entry >= 0);
139        new_entry = &tlb[entry];
140    } else {
141        if (!freeList.empty()) {
142            new_entry = freeList.front();
143        } else {
144            x = lastReplaced;
145            do {
146                ++x;
147                if (x == size)
148                    x = 0;
149                if (x == lastReplaced)
150                    goto insertAllLocked;
151            } while (tlb[x].pte.locked());
152            lastReplaced = x;
153            new_entry = &tlb[x];
154        }
155    }
156
157insertAllLocked:
158    // Update the last ently if their all locked
159    if (!new_entry) {
160        new_entry = &tlb[size-1];
161    }
162
163    freeList.remove(new_entry);
164    if (new_entry->valid && new_entry->used)
165        usedEntries--;
166    if (new_entry->valid)
167        lookupTable.erase(new_entry->range);
168
169
170    assert(PTE.valid());
171    new_entry->range.va = va;
172    new_entry->range.size = PTE.size() - 1;
173    new_entry->range.partitionId = partition_id;
174    new_entry->range.contextId = context_id;
175    new_entry->range.real = real;
176    new_entry->pte = PTE;
177    new_entry->used = true;;
178    new_entry->valid = true;
179    usedEntries++;
180
181    i = lookupTable.insert(new_entry->range, new_entry);
182    assert(i != lookupTable.end());
183
184    // If all entries have their used bit set, clear it on them all,
185    // but the one we just inserted
186    if (usedEntries == size) {
187        clearUsedBits();
188        new_entry->used = true;
189        usedEntries++;
190    }
191}
192
193
194TlbEntry*
195TLB::lookup(Addr va, int partition_id, bool real, int context_id,
196            bool update_used)
197{
198    MapIter i;
199    TlbRange tr;
200    TlbEntry *t;
201
202    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
203            va, partition_id, context_id, real);
204    // Assemble full address structure
205    tr.va = va;
206    tr.size = 1;
207    tr.contextId = context_id;
208    tr.partitionId = partition_id;
209    tr.real = real;
210
211    // Try to find the entry
212    i = lookupTable.find(tr);
213    if (i == lookupTable.end()) {
214        DPRINTF(TLB, "TLB: No valid entry found\n");
215        return NULL;
216    }
217
218    // Mark the entries used bit and clear other used bits in needed
219    t = i->second;
220    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
221            t->pte.size());
222
223    // Update the used bits only if this is a real access (not a fake
224    // one from virttophys()
225    if (!t->used && update_used) {
226        t->used = true;
227        usedEntries++;
228        if (usedEntries == size) {
229            clearUsedBits();
230            t->used = true;
231            usedEntries++;
232        }
233    }
234
235    return t;
236}
237
238void
239TLB::dumpAll()
240{
241    MapIter i;
242    for (int x = 0; x < size; x++) {
243        if (tlb[x].valid) {
244           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
245                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
246                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
247                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
248        }
249    }
250}
251
252void
253TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
254{
255    TlbRange tr;
256    MapIter i;
257
258    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
259            va, partition_id, context_id, real);
260
261    cacheValid = false;
262
263    // Assemble full address structure
264    tr.va = va;
265    tr.size = 1;
266    tr.contextId = context_id;
267    tr.partitionId = partition_id;
268    tr.real = real;
269
270    // Demap any entry that conflicts
271    i = lookupTable.find(tr);
272    if (i != lookupTable.end()) {
273        DPRINTF(IPR, "TLB: Demapped page\n");
274        i->second->valid = false;
275        if (i->second->used) {
276            i->second->used = false;
277            usedEntries--;
278        }
279        freeList.push_front(i->second);
280        lookupTable.erase(i);
281    }
282}
283
284void
285TLB::demapContext(int partition_id, int context_id)
286{
287    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
288            partition_id, context_id);
289    cacheValid = false;
290    for (int x = 0; x < size; x++) {
291        if (tlb[x].range.contextId == context_id &&
292            tlb[x].range.partitionId == partition_id) {
293            if (tlb[x].valid == true) {
294                freeList.push_front(&tlb[x]);
295            }
296            tlb[x].valid = false;
297            if (tlb[x].used) {
298                tlb[x].used = false;
299                usedEntries--;
300            }
301            lookupTable.erase(tlb[x].range);
302        }
303    }
304}
305
306void
307TLB::demapAll(int partition_id)
308{
309    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
310    cacheValid = false;
311    for (int x = 0; x < size; x++) {
312        if (tlb[x].valid && !tlb[x].pte.locked() &&
313                tlb[x].range.partitionId == partition_id) {
314            freeList.push_front(&tlb[x]);
315            tlb[x].valid = false;
316            if (tlb[x].used) {
317                tlb[x].used = false;
318                usedEntries--;
319            }
320            lookupTable.erase(tlb[x].range);
321        }
322    }
323}
324
325void
326TLB::invalidateAll()
327{
328    cacheValid = false;
329    lookupTable.clear();
330
331    for (int x = 0; x < size; x++) {
332        if (tlb[x].valid == true)
333            freeList.push_back(&tlb[x]);
334        tlb[x].valid = false;
335        tlb[x].used = false;
336    }
337    usedEntries = 0;
338}
339
340uint64_t
341TLB::TteRead(int entry)
342{
343    if (entry >= size)
344        panic("entry: %d\n", entry);
345
346    assert(entry < size);
347    if (tlb[entry].valid)
348        return tlb[entry].pte();
349    else
350        return (uint64_t)-1ll;
351}
352
353uint64_t
354TLB::TagRead(int entry)
355{
356    assert(entry < size);
357    uint64_t tag;
358    if (!tlb[entry].valid)
359        return (uint64_t)-1ll;
360
361    tag = tlb[entry].range.contextId;
362    tag |= tlb[entry].range.va;
363    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
364    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
365    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
366    return tag;
367}
368
369bool
370TLB::validVirtualAddress(Addr va, bool am)
371{
372    if (am)
373        return true;
374    if (va >= StartVAddrHole && va <= EndVAddrHole)
375        return false;
376    return true;
377}
378
379void
380TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
381{
382    if (sfsr & 0x1)
383        sfsr = 0x3;
384    else
385        sfsr = 1;
386
387    if (write)
388        sfsr |= 1 << 2;
389    sfsr |= ct << 4;
390    if (se)
391        sfsr |= 1 << 6;
392    sfsr |= ft << 7;
393    sfsr |= asi << 16;
394}
395
396void
397TLB::writeTagAccess(Addr va, int context)
398{
399    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
400            va, context, mbits(va, 63,13) | mbits(context,12,0));
401
402    tag_access = mbits(va, 63,13) | mbits(context,12,0);
403}
404
405void
406TLB::writeSfsr(Addr a, bool write, ContextType ct,
407        bool se, FaultTypes ft, int asi)
408{
409    DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
410            a, (int)write, ct, ft, asi);
411    TLB::writeSfsr(write, ct, se, ft, asi);
412    sfar = a;
413}
414
415Fault
416TLB::translateInst(RequestPtr req, ThreadContext *tc)
417{
418    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
419
420    Addr vaddr = req->getVaddr();
421    TlbEntry *e;
422
423    assert(req->getAsi() == ASI_IMPLICIT);
424
425    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
426            vaddr, req->getSize());
427
428    // Be fast if we can!
429    if (cacheValid && cacheState == tlbdata) {
430        if (cacheEntry[0]) {
431            if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
432                cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
433                req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
434                return NoFault;
435            }
436        } else {
437            req->setPaddr(vaddr & PAddrImplMask);
438            return NoFault;
439        }
440    }
441
442    bool hpriv = bits(tlbdata,0,0);
443    bool red = bits(tlbdata,1,1);
444    bool priv = bits(tlbdata,2,2);
445    bool addr_mask = bits(tlbdata,3,3);
446    bool lsu_im = bits(tlbdata,4,4);
447
448    int part_id = bits(tlbdata,15,8);
449    int tl = bits(tlbdata,18,16);
450    int pri_context = bits(tlbdata,47,32);
451    int context;
452    ContextType ct;
453    int asi;
454    bool real = false;
455
456    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
457           priv, hpriv, red, lsu_im, part_id);
458
459    if (tl > 0) {
460        asi = ASI_N;
461        ct = Nucleus;
462        context = 0;
463    } else {
464        asi = ASI_P;
465        ct = Primary;
466        context = pri_context;
467    }
468
469    if ( hpriv || red ) {
470        cacheValid = true;
471        cacheState = tlbdata;
472        cacheEntry[0] = NULL;
473        req->setPaddr(vaddr & PAddrImplMask);
474        return NoFault;
475    }
476
477    // If the access is unaligned trap
478    if (vaddr & 0x3) {
479        writeSfsr(false, ct, false, OtherFault, asi);
480        return new MemAddressNotAligned;
481    }
482
483    if (addr_mask)
484        vaddr = vaddr & VAddrAMask;
485
486    if (!validVirtualAddress(vaddr, addr_mask)) {
487        writeSfsr(false, ct, false, VaOutOfRange, asi);
488        return new InstructionAccessException;
489    }
490
491    if (!lsu_im) {
492        e = lookup(vaddr, part_id, true);
493        real = true;
494        context = 0;
495    } else {
496        e = lookup(vaddr, part_id, false, context);
497    }
498
499    if (e == NULL || !e->valid) {
500        writeTagAccess(vaddr, context);
501        if (real) {
502            return new InstructionRealTranslationMiss;
503        } else {
504            if (FullSystem)
505                return new FastInstructionAccessMMUMiss;
506            else
507                return new FastInstructionAccessMMUMiss(req->getVaddr());
508        }
509    }
510
511    // were not priviledged accesing priv page
512    if (!priv && e->pte.priv()) {
513        writeTagAccess(vaddr, context);
514        writeSfsr(false, ct, false, PrivViolation, asi);
515        return new InstructionAccessException;
516    }
517
518    // cache translation date for next translation
519    cacheValid = true;
520    cacheState = tlbdata;
521    cacheEntry[0] = e;
522
523    req->setPaddr(e->pte.translate(vaddr));
524    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
525    return NoFault;
526}
527
528Fault
529TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
530{
531    /*
532     * @todo this could really use some profiling and fixing to make
533     * it faster!
534     */
535    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
536    Addr vaddr = req->getVaddr();
537    Addr size = req->getSize();
538    ASI asi;
539    asi = (ASI)req->getAsi();
540    bool implicit = false;
541    bool hpriv = bits(tlbdata,0,0);
542    bool unaligned = vaddr & (size - 1);
543
544    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
545            vaddr, size, asi);
546
547    if (lookupTable.size() != 64 - freeList.size())
548       panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
549               freeList.size());
550    if (asi == ASI_IMPLICIT)
551        implicit = true;
552
553    // Only use the fast path here if there doesn't need to be an unaligned
554    // trap later
555    if (!unaligned) {
556        if (hpriv && implicit) {
557            req->setPaddr(vaddr & PAddrImplMask);
558            return NoFault;
559        }
560
561        // Be fast if we can!
562        if (cacheValid &&  cacheState == tlbdata) {
563
564
565
566            if (cacheEntry[0]) {
567                TlbEntry *ce = cacheEntry[0];
568                Addr ce_va = ce->range.va;
569                if (cacheAsi[0] == asi &&
570                    ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
571                    (!write || ce->pte.writable())) {
572                    req->setPaddr(ce->pte.translate(vaddr));
573                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
574                        req->setFlags(Request::UNCACHEABLE);
575                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
576                    return NoFault;
577                } // if matched
578            } // if cache entry valid
579            if (cacheEntry[1]) {
580                TlbEntry *ce = cacheEntry[1];
581                Addr ce_va = ce->range.va;
582                if (cacheAsi[1] == asi &&
583                    ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
584                    (!write || ce->pte.writable())) {
585                    req->setPaddr(ce->pte.translate(vaddr));
586                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
587                        req->setFlags(Request::UNCACHEABLE);
588                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
589                    return NoFault;
590                } // if matched
591            } // if cache entry valid
592        }
593    }
594
595    bool red = bits(tlbdata,1,1);
596    bool priv = bits(tlbdata,2,2);
597    bool addr_mask = bits(tlbdata,3,3);
598    bool lsu_dm = bits(tlbdata,5,5);
599
600    int part_id = bits(tlbdata,15,8);
601    int tl = bits(tlbdata,18,16);
602    int pri_context = bits(tlbdata,47,32);
603    int sec_context = bits(tlbdata,63,48);
604
605    bool real = false;
606    ContextType ct = Primary;
607    int context = 0;
608
609    TlbEntry *e;
610
611    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
612            priv, hpriv, red, lsu_dm, part_id);
613
614    if (implicit) {
615        if (tl > 0) {
616            asi = ASI_N;
617            ct = Nucleus;
618            context = 0;
619        } else {
620            asi = ASI_P;
621            ct = Primary;
622            context = pri_context;
623        }
624    } else {
625        // We need to check for priv level/asi priv
626        if (!priv && !hpriv && !asiIsUnPriv(asi)) {
627            // It appears that context should be Nucleus in these cases?
628            writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
629            return new PrivilegedAction;
630        }
631
632        if (!hpriv && asiIsHPriv(asi)) {
633            writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
634            return new DataAccessException;
635        }
636
637        if (asiIsPrimary(asi)) {
638            context = pri_context;
639            ct = Primary;
640        } else if (asiIsSecondary(asi)) {
641            context = sec_context;
642            ct = Secondary;
643        } else if (asiIsNucleus(asi)) {
644            ct = Nucleus;
645            context = 0;
646        } else {  // ????
647            ct = Primary;
648            context = pri_context;
649        }
650    }
651
652    if (!implicit && asi != ASI_P && asi != ASI_S) {
653        if (asiIsLittle(asi))
654            panic("Little Endian ASIs not supported\n");
655
656        //XXX It's unclear from looking at the documentation how a no fault
657        // load differs from a regular one, other than what happens concerning
658        // nfo and e bits in the TTE
659//        if (asiIsNoFault(asi))
660//            panic("No Fault ASIs not supported\n");
661
662        if (asiIsPartialStore(asi))
663            panic("Partial Store ASIs not supported\n");
664
665        if (asiIsCmt(asi))
666            panic("Cmt ASI registers not implmented\n");
667
668        if (asiIsInterrupt(asi))
669            goto handleIntRegAccess;
670        if (asiIsMmu(asi))
671            goto handleMmuRegAccess;
672        if (asiIsScratchPad(asi))
673            goto handleScratchRegAccess;
674        if (asiIsQueue(asi))
675            goto handleQueueRegAccess;
676        if (asiIsSparcError(asi))
677            goto handleSparcErrorRegAccess;
678
679        if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
680                !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
681            panic("Accessing ASI %#X. Should we?\n", asi);
682    }
683
684    // If the asi is unaligned trap
685    if (unaligned) {
686        writeSfsr(vaddr, false, ct, false, OtherFault, asi);
687        return new MemAddressNotAligned;
688    }
689
690    if (addr_mask)
691        vaddr = vaddr & VAddrAMask;
692
693    if (!validVirtualAddress(vaddr, addr_mask)) {
694        writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
695        return new DataAccessException;
696    }
697
698    if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
699        real = true;
700        context = 0;
701    }
702
703    if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
704        req->setPaddr(vaddr & PAddrImplMask);
705        return NoFault;
706    }
707
708    e = lookup(vaddr, part_id, real, context);
709
710    if (e == NULL || !e->valid) {
711        writeTagAccess(vaddr, context);
712        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
713        if (real) {
714            return new DataRealTranslationMiss;
715        } else {
716            if (FullSystem)
717                return new FastDataAccessMMUMiss;
718            else
719                return new FastDataAccessMMUMiss(req->getVaddr());
720        }
721
722    }
723
724    if (!priv && e->pte.priv()) {
725        writeTagAccess(vaddr, context);
726        writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
727        return new DataAccessException;
728    }
729
730    if (write && !e->pte.writable()) {
731        writeTagAccess(vaddr, context);
732        writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
733        return new FastDataAccessProtection;
734    }
735
736    if (e->pte.nofault() && !asiIsNoFault(asi)) {
737        writeTagAccess(vaddr, context);
738        writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
739        return new DataAccessException;
740    }
741
742    if (e->pte.sideffect() && asiIsNoFault(asi)) {
743        writeTagAccess(vaddr, context);
744        writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
745        return new DataAccessException;
746    }
747
748    if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
749        req->setFlags(Request::UNCACHEABLE);
750
751    // cache translation date for next translation
752    cacheState = tlbdata;
753    if (!cacheValid) {
754        cacheEntry[1] = NULL;
755        cacheEntry[0] = NULL;
756    }
757
758    if (cacheEntry[0] != e && cacheEntry[1] != e) {
759        cacheEntry[1] = cacheEntry[0];
760        cacheEntry[0] = e;
761        cacheAsi[1] = cacheAsi[0];
762        cacheAsi[0] = asi;
763        if (implicit)
764            cacheAsi[0] = (ASI)0;
765    }
766    cacheValid = true;
767    req->setPaddr(e->pte.translate(vaddr));
768    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
769    return NoFault;
770
771    /** Normal flow ends here. */
772handleIntRegAccess:
773    if (!hpriv) {
774        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
775        if (priv)
776            return new DataAccessException;
777         else
778            return new PrivilegedAction;
779    }
780
781    if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
782        (asi == ASI_SWVR_UDB_INTR_R && write)) {
783        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
784        return new DataAccessException;
785    }
786
787    goto regAccessOk;
788
789
790handleScratchRegAccess:
791    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
792        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
793        return new DataAccessException;
794    }
795    goto regAccessOk;
796
797handleQueueRegAccess:
798    if (!priv  && !hpriv) {
799        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
800        return new PrivilegedAction;
801    }
802    if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
803        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
804        return new DataAccessException;
805    }
806    goto regAccessOk;
807
808handleSparcErrorRegAccess:
809    if (!hpriv) {
810        writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
811        if (priv)
812            return new DataAccessException;
813         else
814            return new PrivilegedAction;
815    }
816    goto regAccessOk;
817
818
819regAccessOk:
820handleMmuRegAccess:
821    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
822    req->setFlags(Request::MMAPPED_IPR);
823    req->setPaddr(req->getVaddr());
824    return NoFault;
825};
826
827Fault
828TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
829{
830    if (mode == Execute)
831        return translateInst(req, tc);
832    else
833        return translateData(req, tc, mode == Write);
834}
835
836void
837TLB::translateTiming(RequestPtr req, ThreadContext *tc,
838        Translation *translation, Mode mode)
839{
840    assert(translation);
841    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
842}
843
844Tick
845TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
846{
847    Addr va = pkt->getAddr();
848    ASI asi = (ASI)pkt->req->getAsi();
849    uint64_t temp;
850
851    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
852         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
853
854    TLB *itb = tc->getITBPtr();
855
856    switch (asi) {
857      case ASI_LSU_CONTROL_REG:
858        assert(va == 0);
859        pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
860        break;
861      case ASI_MMU:
862        switch (va) {
863          case 0x8:
864            pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
865            break;
866          case 0x10:
867            pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
868            break;
869          default:
870            goto doMmuReadError;
871        }
872        break;
873      case ASI_QUEUE:
874        pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
875                    (va >> 4) - 0x3c));
876        break;
877      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
878        assert(va == 0);
879        pkt->set(c0_tsb_ps0);
880        break;
881      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
882        assert(va == 0);
883        pkt->set(c0_tsb_ps1);
884        break;
885      case ASI_DMMU_CTXT_ZERO_CONFIG:
886        assert(va == 0);
887        pkt->set(c0_config);
888        break;
889      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
890        assert(va == 0);
891        pkt->set(itb->c0_tsb_ps0);
892        break;
893      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
894        assert(va == 0);
895        pkt->set(itb->c0_tsb_ps1);
896        break;
897      case ASI_IMMU_CTXT_ZERO_CONFIG:
898        assert(va == 0);
899        pkt->set(itb->c0_config);
900        break;
901      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
902        assert(va == 0);
903        pkt->set(cx_tsb_ps0);
904        break;
905      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
906        assert(va == 0);
907        pkt->set(cx_tsb_ps1);
908        break;
909      case ASI_DMMU_CTXT_NONZERO_CONFIG:
910        assert(va == 0);
911        pkt->set(cx_config);
912        break;
913      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
914        assert(va == 0);
915        pkt->set(itb->cx_tsb_ps0);
916        break;
917      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
918        assert(va == 0);
919        pkt->set(itb->cx_tsb_ps1);
920        break;
921      case ASI_IMMU_CTXT_NONZERO_CONFIG:
922        assert(va == 0);
923        pkt->set(itb->cx_config);
924        break;
925      case ASI_SPARC_ERROR_STATUS_REG:
926        pkt->set((uint64_t)0);
927        break;
928      case ASI_HYP_SCRATCHPAD:
929      case ASI_SCRATCHPAD:
930        pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
931        break;
932      case ASI_IMMU:
933        switch (va) {
934          case 0x0:
935            temp = itb->tag_access;
936            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
937            break;
938          case 0x18:
939            pkt->set(itb->sfsr);
940            break;
941          case 0x30:
942            pkt->set(itb->tag_access);
943            break;
944          default:
945            goto doMmuReadError;
946        }
947        break;
948      case ASI_DMMU:
949        switch (va) {
950          case 0x0:
951            temp = tag_access;
952            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
953            break;
954          case 0x18:
955            pkt->set(sfsr);
956            break;
957          case 0x20:
958            pkt->set(sfar);
959            break;
960          case 0x30:
961            pkt->set(tag_access);
962            break;
963          case 0x80:
964            pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
965            break;
966          default:
967                goto doMmuReadError;
968        }
969        break;
970      case ASI_DMMU_TSB_PS0_PTR_REG:
971        pkt->set(MakeTsbPtr(Ps0,
972            tag_access,
973            c0_tsb_ps0,
974            c0_config,
975            cx_tsb_ps0,
976            cx_config));
977        break;
978      case ASI_DMMU_TSB_PS1_PTR_REG:
979        pkt->set(MakeTsbPtr(Ps1,
980                tag_access,
981                c0_tsb_ps1,
982                c0_config,
983                cx_tsb_ps1,
984                cx_config));
985        break;
986      case ASI_IMMU_TSB_PS0_PTR_REG:
987          pkt->set(MakeTsbPtr(Ps0,
988                itb->tag_access,
989                itb->c0_tsb_ps0,
990                itb->c0_config,
991                itb->cx_tsb_ps0,
992                itb->cx_config));
993        break;
994      case ASI_IMMU_TSB_PS1_PTR_REG:
995          pkt->set(MakeTsbPtr(Ps1,
996                itb->tag_access,
997                itb->c0_tsb_ps1,
998                itb->c0_config,
999                itb->cx_tsb_ps1,
1000                itb->cx_config));
1001        break;
1002      case ASI_SWVR_INTR_RECEIVE:
1003        {
1004            SparcISA::Interrupts * interrupts =
1005                dynamic_cast<SparcISA::Interrupts *>(
1006                        tc->getCpuPtr()->getInterruptController());
1007            pkt->set(interrupts->get_vec(IT_INT_VEC));
1008        }
1009        break;
1010      case ASI_SWVR_UDB_INTR_R:
1011        {
1012            SparcISA::Interrupts * interrupts =
1013                dynamic_cast<SparcISA::Interrupts *>(
1014                        tc->getCpuPtr()->getInterruptController());
1015            temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1016            tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
1017            pkt->set(temp);
1018        }
1019        break;
1020      default:
1021doMmuReadError:
1022        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1023            (uint32_t)asi, va);
1024    }
1025    pkt->makeAtomicResponse();
1026    return tc->getCpuPtr()->ticks(1);
1027}
1028
1029Tick
1030TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1031{
1032    uint64_t data = pkt->get<uint64_t>();
1033    Addr va = pkt->getAddr();
1034    ASI asi = (ASI)pkt->req->getAsi();
1035
1036    Addr ta_insert;
1037    Addr va_insert;
1038    Addr ct_insert;
1039    int part_insert;
1040    int entry_insert = -1;
1041    bool real_insert;
1042    bool ignore;
1043    int part_id;
1044    int ctx_id;
1045    PageTableEntry pte;
1046
1047    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1048         (uint32_t)asi, va, data);
1049
1050    TLB *itb = tc->getITBPtr();
1051
1052    switch (asi) {
1053      case ASI_LSU_CONTROL_REG:
1054        assert(va == 0);
1055        tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1056        break;
1057      case ASI_MMU:
1058        switch (va) {
1059          case 0x8:
1060            tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1061            break;
1062          case 0x10:
1063            tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1064            break;
1065          default:
1066            goto doMmuWriteError;
1067        }
1068        break;
1069      case ASI_QUEUE:
1070        assert(mbits(data,13,6) == data);
1071        tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1072                    (va >> 4) - 0x3c, data);
1073        break;
1074      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1075        assert(va == 0);
1076        c0_tsb_ps0 = data;
1077        break;
1078      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1079        assert(va == 0);
1080        c0_tsb_ps1 = data;
1081        break;
1082      case ASI_DMMU_CTXT_ZERO_CONFIG:
1083        assert(va == 0);
1084        c0_config = data;
1085        break;
1086      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1087        assert(va == 0);
1088        itb->c0_tsb_ps0 = data;
1089        break;
1090      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1091        assert(va == 0);
1092        itb->c0_tsb_ps1 = data;
1093        break;
1094      case ASI_IMMU_CTXT_ZERO_CONFIG:
1095        assert(va == 0);
1096        itb->c0_config = data;
1097        break;
1098      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1099        assert(va == 0);
1100        cx_tsb_ps0 = data;
1101        break;
1102      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1103        assert(va == 0);
1104        cx_tsb_ps1 = data;
1105        break;
1106      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1107        assert(va == 0);
1108        cx_config = data;
1109        break;
1110      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1111        assert(va == 0);
1112        itb->cx_tsb_ps0 = data;
1113        break;
1114      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1115        assert(va == 0);
1116        itb->cx_tsb_ps1 = data;
1117        break;
1118      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1119        assert(va == 0);
1120        itb->cx_config = data;
1121        break;
1122      case ASI_SPARC_ERROR_EN_REG:
1123      case ASI_SPARC_ERROR_STATUS_REG:
1124        inform("Ignoring write to SPARC ERROR regsiter\n");
1125        break;
1126      case ASI_HYP_SCRATCHPAD:
1127      case ASI_SCRATCHPAD:
1128        tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1129        break;
1130      case ASI_IMMU:
1131        switch (va) {
1132          case 0x18:
1133            itb->sfsr = data;
1134            break;
1135          case 0x30:
1136            sext<59>(bits(data, 59,0));
1137            itb->tag_access = data;
1138            break;
1139          default:
1140            goto doMmuWriteError;
1141        }
1142        break;
1143      case ASI_ITLB_DATA_ACCESS_REG:
1144        entry_insert = bits(va, 8,3);
1145      case ASI_ITLB_DATA_IN_REG:
1146        assert(entry_insert != -1 || mbits(va,10,9) == va);
1147        ta_insert = itb->tag_access;
1148        va_insert = mbits(ta_insert, 63,13);
1149        ct_insert = mbits(ta_insert, 12,0);
1150        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1151        real_insert = bits(va, 9,9);
1152        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1153                PageTableEntry::sun4u);
1154        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1155                pte, entry_insert);
1156        break;
1157      case ASI_DTLB_DATA_ACCESS_REG:
1158        entry_insert = bits(va, 8,3);
1159      case ASI_DTLB_DATA_IN_REG:
1160        assert(entry_insert != -1 || mbits(va,10,9) == va);
1161        ta_insert = tag_access;
1162        va_insert = mbits(ta_insert, 63,13);
1163        ct_insert = mbits(ta_insert, 12,0);
1164        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1165        real_insert = bits(va, 9,9);
1166        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1167                PageTableEntry::sun4u);
1168        insert(va_insert, part_insert, ct_insert, real_insert, pte,
1169               entry_insert);
1170        break;
1171      case ASI_IMMU_DEMAP:
1172        ignore = false;
1173        ctx_id = -1;
1174        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1175        switch (bits(va,5,4)) {
1176          case 0:
1177            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1178            break;
1179          case 1:
1180            ignore = true;
1181            break;
1182          case 3:
1183            ctx_id = 0;
1184            break;
1185          default:
1186            ignore = true;
1187        }
1188
1189        switch (bits(va,7,6)) {
1190          case 0: // demap page
1191            if (!ignore)
1192                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1193                        bits(va,9,9), ctx_id);
1194            break;
1195          case 1: // demap context
1196            if (!ignore)
1197                tc->getITBPtr()->demapContext(part_id, ctx_id);
1198            break;
1199          case 2:
1200            tc->getITBPtr()->demapAll(part_id);
1201            break;
1202          default:
1203            panic("Invalid type for IMMU demap\n");
1204        }
1205        break;
1206      case ASI_DMMU:
1207        switch (va) {
1208          case 0x18:
1209            sfsr = data;
1210            break;
1211          case 0x30:
1212            sext<59>(bits(data, 59,0));
1213            tag_access = data;
1214            break;
1215          case 0x80:
1216            tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1217            break;
1218          default:
1219            goto doMmuWriteError;
1220        }
1221        break;
1222      case ASI_DMMU_DEMAP:
1223        ignore = false;
1224        ctx_id = -1;
1225        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1226        switch (bits(va,5,4)) {
1227          case 0:
1228            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1229            break;
1230          case 1:
1231            ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1232            break;
1233          case 3:
1234            ctx_id = 0;
1235            break;
1236          default:
1237            ignore = true;
1238        }
1239
1240        switch (bits(va,7,6)) {
1241          case 0: // demap page
1242            if (!ignore)
1243                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1244            break;
1245          case 1: // demap context
1246            if (!ignore)
1247                demapContext(part_id, ctx_id);
1248            break;
1249          case 2:
1250            demapAll(part_id);
1251            break;
1252          default:
1253            panic("Invalid type for IMMU demap\n");
1254        }
1255        break;
1256       case ASI_SWVR_INTR_RECEIVE:
1257        {
1258            int msb;
1259            // clear all the interrupts that aren't set in the write
1260            SparcISA::Interrupts * interrupts =
1261                dynamic_cast<SparcISA::Interrupts *>(
1262                        tc->getCpuPtr()->getInterruptController());
1263            while (interrupts->get_vec(IT_INT_VEC) & data) {
1264                msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1265                tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
1266            }
1267        }
1268        break;
1269      case ASI_SWVR_UDB_INTR_W:
1270            tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1271            postInterrupt(bits(data, 5, 0), 0);
1272        break;
1273      default:
1274doMmuWriteError:
1275        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1276            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1277    }
1278    pkt->makeAtomicResponse();
1279    return tc->getCpuPtr()->ticks(1);
1280}
1281
1282void
1283TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1284{
1285    uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1286    TLB * itb = tc->getITBPtr();
1287    ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1288                c0_tsb_ps0,
1289                c0_config,
1290                cx_tsb_ps0,
1291                cx_config);
1292    ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1293                c0_tsb_ps1,
1294                c0_config,
1295                cx_tsb_ps1,
1296                cx_config);
1297    ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1298                itb->c0_tsb_ps0,
1299                itb->c0_config,
1300                itb->cx_tsb_ps0,
1301                itb->cx_config);
1302    ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1303                itb->c0_tsb_ps1,
1304                itb->c0_config,
1305                itb->cx_tsb_ps1,
1306                itb->cx_config);
1307}
1308
1309uint64_t
1310TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1311        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1312{
1313    uint64_t tsb;
1314    uint64_t config;
1315
1316    if (bits(tag_access, 12,0) == 0) {
1317        tsb = c0_tsb;
1318        config = c0_config;
1319    } else {
1320        tsb = cX_tsb;
1321        config = cX_config;
1322    }
1323
1324    uint64_t ptr = mbits(tsb,63,13);
1325    bool split = bits(tsb,12,12);
1326    int tsb_size = bits(tsb,3,0);
1327    int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1328
1329    if (ps == Ps1  && split)
1330        ptr |= ULL(1) << (13 + tsb_size);
1331    ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1332
1333    return ptr;
1334}
1335
1336void
1337TLB::serialize(std::ostream &os)
1338{
1339    SERIALIZE_SCALAR(size);
1340    SERIALIZE_SCALAR(usedEntries);
1341    SERIALIZE_SCALAR(lastReplaced);
1342
1343    // convert the pointer based free list into an index based one
1344    int *free_list = (int*)malloc(sizeof(int) * size);
1345    int cntr = 0;
1346    std::list<TlbEntry*>::iterator i;
1347    i = freeList.begin();
1348    while (i != freeList.end()) {
1349        free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1350        i++;
1351    }
1352    SERIALIZE_SCALAR(cntr);
1353    SERIALIZE_ARRAY(free_list,  cntr);
1354
1355    SERIALIZE_SCALAR(c0_tsb_ps0);
1356    SERIALIZE_SCALAR(c0_tsb_ps1);
1357    SERIALIZE_SCALAR(c0_config);
1358    SERIALIZE_SCALAR(cx_tsb_ps0);
1359    SERIALIZE_SCALAR(cx_tsb_ps1);
1360    SERIALIZE_SCALAR(cx_config);
1361    SERIALIZE_SCALAR(sfsr);
1362    SERIALIZE_SCALAR(tag_access);
1363
1364    for (int x = 0; x < size; x++) {
1365        nameOut(os, csprintf("%s.PTE%d", name(), x));
1366        tlb[x].serialize(os);
1367    }
1368    SERIALIZE_SCALAR(sfar);
1369}
1370
1371void
1372TLB::unserialize(Checkpoint *cp, const std::string &section)
1373{
1374    int oldSize;
1375
1376    paramIn(cp, section, "size", oldSize);
1377    if (oldSize != size)
1378        panic("Don't support unserializing different sized TLBs\n");
1379    UNSERIALIZE_SCALAR(usedEntries);
1380    UNSERIALIZE_SCALAR(lastReplaced);
1381
1382    int cntr;
1383    UNSERIALIZE_SCALAR(cntr);
1384
1385    int *free_list = (int*)malloc(sizeof(int) * cntr);
1386    freeList.clear();
1387    UNSERIALIZE_ARRAY(free_list,  cntr);
1388    for (int x = 0; x < cntr; x++)
1389        freeList.push_back(&tlb[free_list[x]]);
1390
1391    UNSERIALIZE_SCALAR(c0_tsb_ps0);
1392    UNSERIALIZE_SCALAR(c0_tsb_ps1);
1393    UNSERIALIZE_SCALAR(c0_config);
1394    UNSERIALIZE_SCALAR(cx_tsb_ps0);
1395    UNSERIALIZE_SCALAR(cx_tsb_ps1);
1396    UNSERIALIZE_SCALAR(cx_config);
1397    UNSERIALIZE_SCALAR(sfsr);
1398    UNSERIALIZE_SCALAR(tag_access);
1399
1400    lookupTable.clear();
1401    for (int x = 0; x < size; x++) {
1402        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1403        if (tlb[x].valid)
1404            lookupTable.insert(tlb[x].range, &tlb[x]);
1405
1406    }
1407    UNSERIALIZE_SCALAR(sfar);
1408}
1409
1410} // namespace SparcISA
1411
1412SparcISA::TLB *
1413SparcTLBParams::create()
1414{
1415    return new SparcISA::TLB(this);
1416}
1417