tlb.cc revision 8374
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 347678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 356335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 363569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 373824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 383811Ssaidi@eecs.umich.edu#include "base/trace.hh" 398229Snate@binkert.org#include "cpu/base.hh" 403811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 418232Snate@binkert.org#include "debug/IPR.hh" 428232Snate@binkert.org#include "debug/TLB.hh" 433823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 443823Ssaidi@eecs.umich.edu#include "mem/request.hh" 454103Ssaidi@eecs.umich.edu#include "sim/system.hh" 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 483804Ssaidi@eecs.umich.edu * */ 494088Sbinkertn@umich.edunamespace SparcISA { 503569Sgblack@eecs.umich.edu 515034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 525358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 538374Sksewell@umich.edu cacheState(0), cacheValid(false) 543804Ssaidi@eecs.umich.edu{ 553804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 563804Ssaidi@eecs.umich.edu if (size > 64) 575555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 583569Sgblack@eecs.umich.edu 593804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 603918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 613881Ssaidi@eecs.umich.edu 623881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 633881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 644990Sgblack@eecs.umich.edu 654990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 664990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 674990Sgblack@eecs.umich.edu c0_config = 0; 684990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 694990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 704990Sgblack@eecs.umich.edu cx_config = 0; 714990Sgblack@eecs.umich.edu sfsr = 0; 724990Sgblack@eecs.umich.edu tag_access = 0; 736022Sgblack@eecs.umich.edu sfar = 0; 746022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 756022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 763804Ssaidi@eecs.umich.edu} 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.eduvoid 793804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 803804Ssaidi@eecs.umich.edu{ 813804Ssaidi@eecs.umich.edu MapIter i; 823881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 833804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 843804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 853804Ssaidi@eecs.umich.edu t->used = false; 863804Ssaidi@eecs.umich.edu usedEntries--; 873804Ssaidi@eecs.umich.edu } 883804Ssaidi@eecs.umich.edu } 893804Ssaidi@eecs.umich.edu} 903569Sgblack@eecs.umich.edu 913569Sgblack@eecs.umich.edu 923804Ssaidi@eecs.umich.eduvoid 933804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 943826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 953804Ssaidi@eecs.umich.edu{ 963804Ssaidi@eecs.umich.edu MapIter i; 973826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 983907Ssaidi@eecs.umich.edu// TlbRange tr; 993826Ssaidi@eecs.umich.edu int x; 1003811Ssaidi@eecs.umich.edu 1013836Ssaidi@eecs.umich.edu cacheValid = false; 1023915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1033907Ssaidi@eecs.umich.edu /* tr.va = va; 1043881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1053881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1063881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1073881Ssaidi@eecs.umich.edu tr.real = real; 1083907Ssaidi@eecs.umich.edu*/ 1093881Ssaidi@eecs.umich.edu 1105555Snate@binkert.org DPRINTF(TLB, 1115555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1125555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1133881Ssaidi@eecs.umich.edu 1143881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1153907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1163907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1173907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1183907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1193907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1203907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1213907Ssaidi@eecs.umich.edu { 1223907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1233907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1243907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1253907Ssaidi@eecs.umich.edu 1263907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1273907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1283907Ssaidi@eecs.umich.edu tlb[x].used = false; 1293907Ssaidi@eecs.umich.edu usedEntries--; 1303907Ssaidi@eecs.umich.edu } 1313907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1323907Ssaidi@eecs.umich.edu } 1333907Ssaidi@eecs.umich.edu } 1343907Ssaidi@eecs.umich.edu } 1353907Ssaidi@eecs.umich.edu 1363826Ssaidi@eecs.umich.edu if (entry != -1) { 1373826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1383826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1393826Ssaidi@eecs.umich.edu } else { 1403881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1413881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1423881Ssaidi@eecs.umich.edu } else { 1433881Ssaidi@eecs.umich.edu x = lastReplaced; 1443881Ssaidi@eecs.umich.edu do { 1453881Ssaidi@eecs.umich.edu ++x; 1463881Ssaidi@eecs.umich.edu if (x == size) 1473881Ssaidi@eecs.umich.edu x = 0; 1483881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1493881Ssaidi@eecs.umich.edu goto insertAllLocked; 1503881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1513881Ssaidi@eecs.umich.edu lastReplaced = x; 1523881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1533881Ssaidi@eecs.umich.edu } 1543569Sgblack@eecs.umich.edu } 1553569Sgblack@eecs.umich.edu 1563881Ssaidi@eecs.umich.eduinsertAllLocked: 1573804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1583881Ssaidi@eecs.umich.edu if (!new_entry) { 1593826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1603881Ssaidi@eecs.umich.edu } 1613881Ssaidi@eecs.umich.edu 1623881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1633907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1643907Ssaidi@eecs.umich.edu usedEntries--; 1653929Ssaidi@eecs.umich.edu if (new_entry->valid) 1663929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1673907Ssaidi@eecs.umich.edu 1683907Ssaidi@eecs.umich.edu 1693804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1703804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1713881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1723804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1733804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1743804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1753804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1763804Ssaidi@eecs.umich.edu new_entry->used = true;; 1773804Ssaidi@eecs.umich.edu new_entry->valid = true; 1783804Ssaidi@eecs.umich.edu usedEntries++; 1793569Sgblack@eecs.umich.edu 1803863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1813863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1823804Ssaidi@eecs.umich.edu 1835555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 1845555Snate@binkert.org // but the one we just inserted 1853804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1863804Ssaidi@eecs.umich.edu clearUsedBits(); 1873804Ssaidi@eecs.umich.edu new_entry->used = true; 1883804Ssaidi@eecs.umich.edu usedEntries++; 1893804Ssaidi@eecs.umich.edu } 1903569Sgblack@eecs.umich.edu} 1913804Ssaidi@eecs.umich.edu 1923804Ssaidi@eecs.umich.edu 1933804Ssaidi@eecs.umich.eduTlbEntry* 1945555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 1955555Snate@binkert.org bool update_used) 1963804Ssaidi@eecs.umich.edu{ 1973804Ssaidi@eecs.umich.edu MapIter i; 1983804Ssaidi@eecs.umich.edu TlbRange tr; 1993804Ssaidi@eecs.umich.edu TlbEntry *t; 2003804Ssaidi@eecs.umich.edu 2013811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2023811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2033804Ssaidi@eecs.umich.edu // Assemble full address structure 2043804Ssaidi@eecs.umich.edu tr.va = va; 2055312Sgblack@eecs.umich.edu tr.size = 1; 2063804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2073804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2083804Ssaidi@eecs.umich.edu tr.real = real; 2093804Ssaidi@eecs.umich.edu 2103804Ssaidi@eecs.umich.edu // Try to find the entry 2113804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2123804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2133811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2143804Ssaidi@eecs.umich.edu return NULL; 2153804Ssaidi@eecs.umich.edu } 2163804Ssaidi@eecs.umich.edu 2173804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2183804Ssaidi@eecs.umich.edu t = i->second; 2193826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2203826Ssaidi@eecs.umich.edu t->pte.size()); 2214070Ssaidi@eecs.umich.edu 2225555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2235555Snate@binkert.org // one from virttophys() 2244070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2253804Ssaidi@eecs.umich.edu t->used = true; 2263804Ssaidi@eecs.umich.edu usedEntries++; 2273804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2283804Ssaidi@eecs.umich.edu clearUsedBits(); 2293804Ssaidi@eecs.umich.edu t->used = true; 2303804Ssaidi@eecs.umich.edu usedEntries++; 2313804Ssaidi@eecs.umich.edu } 2323804Ssaidi@eecs.umich.edu } 2333804Ssaidi@eecs.umich.edu 2343804Ssaidi@eecs.umich.edu return t; 2353804Ssaidi@eecs.umich.edu} 2363804Ssaidi@eecs.umich.edu 2373826Ssaidi@eecs.umich.eduvoid 2383826Ssaidi@eecs.umich.eduTLB::dumpAll() 2393826Ssaidi@eecs.umich.edu{ 2403863Ssaidi@eecs.umich.edu MapIter i; 2413826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2423826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2433826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2443826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2453826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2463826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2473826Ssaidi@eecs.umich.edu } 2483826Ssaidi@eecs.umich.edu } 2493826Ssaidi@eecs.umich.edu} 2503804Ssaidi@eecs.umich.edu 2513804Ssaidi@eecs.umich.eduvoid 2523804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2533804Ssaidi@eecs.umich.edu{ 2543804Ssaidi@eecs.umich.edu TlbRange tr; 2553804Ssaidi@eecs.umich.edu MapIter i; 2563804Ssaidi@eecs.umich.edu 2573863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2583863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2593863Ssaidi@eecs.umich.edu 2603836Ssaidi@eecs.umich.edu cacheValid = false; 2613836Ssaidi@eecs.umich.edu 2623804Ssaidi@eecs.umich.edu // Assemble full address structure 2633804Ssaidi@eecs.umich.edu tr.va = va; 2645312Sgblack@eecs.umich.edu tr.size = 1; 2653804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2663804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2673804Ssaidi@eecs.umich.edu tr.real = real; 2683804Ssaidi@eecs.umich.edu 2693804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2703804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2713804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2723863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2733804Ssaidi@eecs.umich.edu i->second->valid = false; 2743804Ssaidi@eecs.umich.edu if (i->second->used) { 2753804Ssaidi@eecs.umich.edu i->second->used = false; 2763804Ssaidi@eecs.umich.edu usedEntries--; 2773804Ssaidi@eecs.umich.edu } 2783881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2793804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2803804Ssaidi@eecs.umich.edu } 2813804Ssaidi@eecs.umich.edu} 2823804Ssaidi@eecs.umich.edu 2833804Ssaidi@eecs.umich.eduvoid 2843804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2853804Ssaidi@eecs.umich.edu{ 2863863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2873863Ssaidi@eecs.umich.edu partition_id, context_id); 2883836Ssaidi@eecs.umich.edu cacheValid = false; 2895555Snate@binkert.org for (int x = 0; x < size; x++) { 2903804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2913804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2923881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 2933881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2943881Ssaidi@eecs.umich.edu } 2953804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2963804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2973804Ssaidi@eecs.umich.edu tlb[x].used = false; 2983804Ssaidi@eecs.umich.edu usedEntries--; 2993804Ssaidi@eecs.umich.edu } 3003804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3013804Ssaidi@eecs.umich.edu } 3023804Ssaidi@eecs.umich.edu } 3033804Ssaidi@eecs.umich.edu} 3043804Ssaidi@eecs.umich.edu 3053804Ssaidi@eecs.umich.eduvoid 3063804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3073804Ssaidi@eecs.umich.edu{ 3083863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3093836Ssaidi@eecs.umich.edu cacheValid = false; 3105555Snate@binkert.org for (int x = 0; x < size; x++) { 3115288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3125288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3135288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3143804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3153804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3163804Ssaidi@eecs.umich.edu tlb[x].used = false; 3173804Ssaidi@eecs.umich.edu usedEntries--; 3183804Ssaidi@eecs.umich.edu } 3193804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3203804Ssaidi@eecs.umich.edu } 3213804Ssaidi@eecs.umich.edu } 3223804Ssaidi@eecs.umich.edu} 3233804Ssaidi@eecs.umich.edu 3243804Ssaidi@eecs.umich.eduvoid 3253804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3263804Ssaidi@eecs.umich.edu{ 3273836Ssaidi@eecs.umich.edu cacheValid = false; 3285555Snate@binkert.org lookupTable.clear(); 3293836Ssaidi@eecs.umich.edu 3305555Snate@binkert.org for (int x = 0; x < size; x++) { 3313881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3323881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3333804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3343907Ssaidi@eecs.umich.edu tlb[x].used = false; 3353804Ssaidi@eecs.umich.edu } 3363804Ssaidi@eecs.umich.edu usedEntries = 0; 3373804Ssaidi@eecs.umich.edu} 3383804Ssaidi@eecs.umich.edu 3393804Ssaidi@eecs.umich.eduuint64_t 3405555Snate@binkert.orgTLB::TteRead(int entry) 3415555Snate@binkert.org{ 3423881Ssaidi@eecs.umich.edu if (entry >= size) 3433881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3443881Ssaidi@eecs.umich.edu 3453804Ssaidi@eecs.umich.edu assert(entry < size); 3463881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3473881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3483881Ssaidi@eecs.umich.edu else 3493881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3503804Ssaidi@eecs.umich.edu} 3513804Ssaidi@eecs.umich.edu 3523804Ssaidi@eecs.umich.eduuint64_t 3535555Snate@binkert.orgTLB::TagRead(int entry) 3545555Snate@binkert.org{ 3553804Ssaidi@eecs.umich.edu assert(entry < size); 3563804Ssaidi@eecs.umich.edu uint64_t tag; 3573881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3583881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3593804Ssaidi@eecs.umich.edu 3603881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3613881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3623881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3633804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3643804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3653804Ssaidi@eecs.umich.edu return tag; 3663804Ssaidi@eecs.umich.edu} 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.edubool 3693804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3703804Ssaidi@eecs.umich.edu{ 3713804Ssaidi@eecs.umich.edu if (am) 3723804Ssaidi@eecs.umich.edu return true; 3733804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3743804Ssaidi@eecs.umich.edu return false; 3753804Ssaidi@eecs.umich.edu return true; 3763804Ssaidi@eecs.umich.edu} 3773804Ssaidi@eecs.umich.edu 3783804Ssaidi@eecs.umich.eduvoid 3794990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3803804Ssaidi@eecs.umich.edu{ 3813804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3823804Ssaidi@eecs.umich.edu sfsr = 0x3; 3833804Ssaidi@eecs.umich.edu else 3843804Ssaidi@eecs.umich.edu sfsr = 1; 3853804Ssaidi@eecs.umich.edu 3863804Ssaidi@eecs.umich.edu if (write) 3873804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3883804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3893804Ssaidi@eecs.umich.edu if (se) 3903804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3913804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3923804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3933804Ssaidi@eecs.umich.edu} 3943804Ssaidi@eecs.umich.edu 3953826Ssaidi@eecs.umich.eduvoid 3964990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 3973826Ssaidi@eecs.umich.edu{ 3983916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 3993916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4003916Ssaidi@eecs.umich.edu 4014990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4023826Ssaidi@eecs.umich.edu} 4033804Ssaidi@eecs.umich.edu 4043804Ssaidi@eecs.umich.eduvoid 4056022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4063804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4073804Ssaidi@eecs.umich.edu{ 4086022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4093811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4104990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4114990Sgblack@eecs.umich.edu sfar = a; 4123804Ssaidi@eecs.umich.edu} 4133804Ssaidi@eecs.umich.edu 4143804Ssaidi@eecs.umich.eduFault 4156022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 4163804Ssaidi@eecs.umich.edu{ 4174172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4183833Ssaidi@eecs.umich.edu 4193836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4203836Ssaidi@eecs.umich.edu TlbEntry *e; 4213836Ssaidi@eecs.umich.edu 4223836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4233836Ssaidi@eecs.umich.edu 4243836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4253836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4263836Ssaidi@eecs.umich.edu 4273836Ssaidi@eecs.umich.edu // Be fast if we can! 4283836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4296022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4306022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4316022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4326022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4335555Snate@binkert.org return NoFault; 4343836Ssaidi@eecs.umich.edu } 4353836Ssaidi@eecs.umich.edu } else { 4363836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4373836Ssaidi@eecs.umich.edu return NoFault; 4383836Ssaidi@eecs.umich.edu } 4393836Ssaidi@eecs.umich.edu } 4403836Ssaidi@eecs.umich.edu 4413833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4423833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4433833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4443833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4453833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4463833Ssaidi@eecs.umich.edu 4473833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4483833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4493833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4503804Ssaidi@eecs.umich.edu int context; 4513804Ssaidi@eecs.umich.edu ContextType ct; 4523804Ssaidi@eecs.umich.edu int asi; 4533804Ssaidi@eecs.umich.edu bool real = false; 4543804Ssaidi@eecs.umich.edu 4553833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4563833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4573811Ssaidi@eecs.umich.edu 4583804Ssaidi@eecs.umich.edu if (tl > 0) { 4593804Ssaidi@eecs.umich.edu asi = ASI_N; 4603804Ssaidi@eecs.umich.edu ct = Nucleus; 4613804Ssaidi@eecs.umich.edu context = 0; 4623804Ssaidi@eecs.umich.edu } else { 4633804Ssaidi@eecs.umich.edu asi = ASI_P; 4643804Ssaidi@eecs.umich.edu ct = Primary; 4653833Ssaidi@eecs.umich.edu context = pri_context; 4663804Ssaidi@eecs.umich.edu } 4673804Ssaidi@eecs.umich.edu 4683833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4693836Ssaidi@eecs.umich.edu cacheValid = true; 4703836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4716022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4723836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4733804Ssaidi@eecs.umich.edu return NoFault; 4743804Ssaidi@eecs.umich.edu } 4753804Ssaidi@eecs.umich.edu 4763836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4773836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4784990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 4793804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4803804Ssaidi@eecs.umich.edu } 4813804Ssaidi@eecs.umich.edu 4823804Ssaidi@eecs.umich.edu if (addr_mask) 4833804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4843804Ssaidi@eecs.umich.edu 4853804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4864990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 4873804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4883804Ssaidi@eecs.umich.edu } 4893804Ssaidi@eecs.umich.edu 4903833Ssaidi@eecs.umich.edu if (!lsu_im) { 4913836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4923804Ssaidi@eecs.umich.edu real = true; 4933804Ssaidi@eecs.umich.edu context = 0; 4943804Ssaidi@eecs.umich.edu } else { 4953804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4963804Ssaidi@eecs.umich.edu } 4973804Ssaidi@eecs.umich.edu 4983804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4994990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5003804Ssaidi@eecs.umich.edu if (real) 5013804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5023804Ssaidi@eecs.umich.edu else 5034997Sgblack@eecs.umich.edu#if FULL_SYSTEM 5043804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5054997Sgblack@eecs.umich.edu#else 5064997Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5074997Sgblack@eecs.umich.edu#endif 5083804Ssaidi@eecs.umich.edu } 5093804Ssaidi@eecs.umich.edu 5103804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5113804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5124990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5134990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5143804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5153804Ssaidi@eecs.umich.edu } 5163804Ssaidi@eecs.umich.edu 5173836Ssaidi@eecs.umich.edu // cache translation date for next translation 5183836Ssaidi@eecs.umich.edu cacheValid = true; 5193836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5206022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5213836Ssaidi@eecs.umich.edu 5225555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5233836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5243804Ssaidi@eecs.umich.edu return NoFault; 5253804Ssaidi@eecs.umich.edu} 5263804Ssaidi@eecs.umich.edu 5273804Ssaidi@eecs.umich.eduFault 5286022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 5293804Ssaidi@eecs.umich.edu{ 5305555Snate@binkert.org /* 5315555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5325555Snate@binkert.org * it faster! 5335555Snate@binkert.org */ 5344172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5353836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5363836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5373836Ssaidi@eecs.umich.edu ASI asi; 5383836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5393836Ssaidi@eecs.umich.edu bool implicit = false; 5403836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5415570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5423833Ssaidi@eecs.umich.edu 5433836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5443836Ssaidi@eecs.umich.edu vaddr, size, asi); 5453836Ssaidi@eecs.umich.edu 5463929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5473929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5483929Ssaidi@eecs.umich.edu freeList.size()); 5493836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5503836Ssaidi@eecs.umich.edu implicit = true; 5513836Ssaidi@eecs.umich.edu 5524996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5534996Sgblack@eecs.umich.edu // trap later 5544996Sgblack@eecs.umich.edu if (!unaligned) { 5554996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5564996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5574996Sgblack@eecs.umich.edu return NoFault; 5584996Sgblack@eecs.umich.edu } 5594996Sgblack@eecs.umich.edu 5604996Sgblack@eecs.umich.edu // Be fast if we can! 5614996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5624996Sgblack@eecs.umich.edu 5634996Sgblack@eecs.umich.edu 5644996Sgblack@eecs.umich.edu 5654996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5664996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5674996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5684996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5694996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5704996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5715555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5725555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5735736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5745555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5755555Snate@binkert.org return NoFault; 5764996Sgblack@eecs.umich.edu } // if matched 5774996Sgblack@eecs.umich.edu } // if cache entry valid 5784996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5794996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5804996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5814996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 5824996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5834996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5845555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5855555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5865736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5875555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5885555Snate@binkert.org return NoFault; 5894996Sgblack@eecs.umich.edu } // if matched 5904996Sgblack@eecs.umich.edu } // if cache entry valid 5914996Sgblack@eecs.umich.edu } 5923836Ssaidi@eecs.umich.edu } 5933836Ssaidi@eecs.umich.edu 5943833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 5953833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 5963833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 5973833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 5983833Ssaidi@eecs.umich.edu 5993833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6003833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6013833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6023916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6033833Ssaidi@eecs.umich.edu 6043804Ssaidi@eecs.umich.edu bool real = false; 6053832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6063832Ssaidi@eecs.umich.edu int context = 0; 6073804Ssaidi@eecs.umich.edu 6083804Ssaidi@eecs.umich.edu TlbEntry *e; 6093804Ssaidi@eecs.umich.edu 6103833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6115555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6123804Ssaidi@eecs.umich.edu 6133804Ssaidi@eecs.umich.edu if (implicit) { 6143804Ssaidi@eecs.umich.edu if (tl > 0) { 6153804Ssaidi@eecs.umich.edu asi = ASI_N; 6163804Ssaidi@eecs.umich.edu ct = Nucleus; 6173804Ssaidi@eecs.umich.edu context = 0; 6183804Ssaidi@eecs.umich.edu } else { 6193804Ssaidi@eecs.umich.edu asi = ASI_P; 6203804Ssaidi@eecs.umich.edu ct = Primary; 6213833Ssaidi@eecs.umich.edu context = pri_context; 6223804Ssaidi@eecs.umich.edu } 6233910Ssaidi@eecs.umich.edu } else { 6243804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6257741Sgblack@eecs.umich.edu if (!priv && !hpriv && !asiIsUnPriv(asi)) { 6263804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6274990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6283804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6293804Ssaidi@eecs.umich.edu } 6303910Ssaidi@eecs.umich.edu 6317741Sgblack@eecs.umich.edu if (!hpriv && asiIsHPriv(asi)) { 6324990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6333804Ssaidi@eecs.umich.edu return new DataAccessException; 6343804Ssaidi@eecs.umich.edu } 6353804Ssaidi@eecs.umich.edu 6367741Sgblack@eecs.umich.edu if (asiIsPrimary(asi)) { 6373910Ssaidi@eecs.umich.edu context = pri_context; 6383910Ssaidi@eecs.umich.edu ct = Primary; 6397741Sgblack@eecs.umich.edu } else if (asiIsSecondary(asi)) { 6403910Ssaidi@eecs.umich.edu context = sec_context; 6413910Ssaidi@eecs.umich.edu ct = Secondary; 6427741Sgblack@eecs.umich.edu } else if (asiIsNucleus(asi)) { 6433910Ssaidi@eecs.umich.edu ct = Nucleus; 6443910Ssaidi@eecs.umich.edu context = 0; 6453910Ssaidi@eecs.umich.edu } else { // ???? 6463910Ssaidi@eecs.umich.edu ct = Primary; 6473910Ssaidi@eecs.umich.edu context = pri_context; 6483910Ssaidi@eecs.umich.edu } 6493902Ssaidi@eecs.umich.edu } 6503804Ssaidi@eecs.umich.edu 6513926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6527741Sgblack@eecs.umich.edu if (asiIsLittle(asi)) 6533804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6544989Sgblack@eecs.umich.edu 6554989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6567741Sgblack@eecs.umich.edu // load differs from a regular one, other than what happens concerning 6577741Sgblack@eecs.umich.edu // nfo and e bits in the TTE 6587741Sgblack@eecs.umich.edu// if (asiIsNoFault(asi)) 6594989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6603856Ssaidi@eecs.umich.edu 6617741Sgblack@eecs.umich.edu if (asiIsPartialStore(asi)) 6623804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6634103Ssaidi@eecs.umich.edu 6647741Sgblack@eecs.umich.edu if (asiIsCmt(asi)) 6654191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6664191Ssaidi@eecs.umich.edu 6677741Sgblack@eecs.umich.edu if (asiIsInterrupt(asi)) 6684103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6697741Sgblack@eecs.umich.edu if (asiIsMmu(asi)) 6703804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6717741Sgblack@eecs.umich.edu if (asiIsScratchPad(asi)) 6723804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6737741Sgblack@eecs.umich.edu if (asiIsQueue(asi)) 6743824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6757741Sgblack@eecs.umich.edu if (asiIsSparcError(asi)) 6763825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6773823Ssaidi@eecs.umich.edu 6787741Sgblack@eecs.umich.edu if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 6797741Sgblack@eecs.umich.edu !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 6803823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6813804Ssaidi@eecs.umich.edu } 6823804Ssaidi@eecs.umich.edu 6833826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6844996Sgblack@eecs.umich.edu if (unaligned) { 6854990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 6863826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6873826Ssaidi@eecs.umich.edu } 6883826Ssaidi@eecs.umich.edu 6893826Ssaidi@eecs.umich.edu if (addr_mask) 6903826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6913826Ssaidi@eecs.umich.edu 6923826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 6934990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 6943826Ssaidi@eecs.umich.edu return new DataAccessException; 6953826Ssaidi@eecs.umich.edu } 6963826Ssaidi@eecs.umich.edu 6977741Sgblack@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 6983804Ssaidi@eecs.umich.edu real = true; 6993804Ssaidi@eecs.umich.edu context = 0; 7005555Snate@binkert.org } 7013804Ssaidi@eecs.umich.edu 7027741Sgblack@eecs.umich.edu if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 7033836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7043804Ssaidi@eecs.umich.edu return NoFault; 7053804Ssaidi@eecs.umich.edu } 7063804Ssaidi@eecs.umich.edu 7073836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7083804Ssaidi@eecs.umich.edu 7093804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7104990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7113811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7123804Ssaidi@eecs.umich.edu if (real) 7133804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7143804Ssaidi@eecs.umich.edu else 7154997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7163804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7174997Sgblack@eecs.umich.edu#else 7184997Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7194997Sgblack@eecs.umich.edu#endif 7203804Ssaidi@eecs.umich.edu 7213804Ssaidi@eecs.umich.edu } 7223804Ssaidi@eecs.umich.edu 7233928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7244990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7254990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7263928Ssaidi@eecs.umich.edu return new DataAccessException; 7273928Ssaidi@eecs.umich.edu } 7283804Ssaidi@eecs.umich.edu 7293804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7304990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7314990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7323804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7333804Ssaidi@eecs.umich.edu } 7343804Ssaidi@eecs.umich.edu 7357741Sgblack@eecs.umich.edu if (e->pte.nofault() && !asiIsNoFault(asi)) { 7364990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7374990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7383804Ssaidi@eecs.umich.edu return new DataAccessException; 7393804Ssaidi@eecs.umich.edu } 7403804Ssaidi@eecs.umich.edu 7417741Sgblack@eecs.umich.edu if (e->pte.sideffect() && asiIsNoFault(asi)) { 7424990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7434990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7443928Ssaidi@eecs.umich.edu return new DataAccessException; 7453928Ssaidi@eecs.umich.edu } 7463928Ssaidi@eecs.umich.edu 7474090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7485736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 7493804Ssaidi@eecs.umich.edu 7503836Ssaidi@eecs.umich.edu // cache translation date for next translation 7513836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7523881Ssaidi@eecs.umich.edu if (!cacheValid) { 7533881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7543881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7553881Ssaidi@eecs.umich.edu } 7563881Ssaidi@eecs.umich.edu 7573836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7583836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7593836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7603836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7613836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7623836Ssaidi@eecs.umich.edu if (implicit) 7633836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7643836Ssaidi@eecs.umich.edu } 7653881Ssaidi@eecs.umich.edu cacheValid = true; 7665555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7673836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7683804Ssaidi@eecs.umich.edu return NoFault; 7694103Ssaidi@eecs.umich.edu 7703806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7714103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7724103Ssaidi@eecs.umich.edu if (!hpriv) { 7734990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7744103Ssaidi@eecs.umich.edu if (priv) 7754103Ssaidi@eecs.umich.edu return new DataAccessException; 7764103Ssaidi@eecs.umich.edu else 7774103Ssaidi@eecs.umich.edu return new PrivilegedAction; 7784103Ssaidi@eecs.umich.edu } 7794103Ssaidi@eecs.umich.edu 7805570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 7815570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 7824990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7834103Ssaidi@eecs.umich.edu return new DataAccessException; 7844103Ssaidi@eecs.umich.edu } 7854103Ssaidi@eecs.umich.edu 7864103Ssaidi@eecs.umich.edu goto regAccessOk; 7874103Ssaidi@eecs.umich.edu 7883804Ssaidi@eecs.umich.edu 7893806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7903806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7914990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7923806Ssaidi@eecs.umich.edu return new DataAccessException; 7933806Ssaidi@eecs.umich.edu } 7943824Ssaidi@eecs.umich.edu goto regAccessOk; 7953824Ssaidi@eecs.umich.edu 7963824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7973824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7984990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7993824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8003824Ssaidi@eecs.umich.edu } 8015570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8024990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8033824Ssaidi@eecs.umich.edu return new DataAccessException; 8043824Ssaidi@eecs.umich.edu } 8053824Ssaidi@eecs.umich.edu goto regAccessOk; 8063824Ssaidi@eecs.umich.edu 8073825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8083825Ssaidi@eecs.umich.edu if (!hpriv) { 8094990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8104070Ssaidi@eecs.umich.edu if (priv) 8113825Ssaidi@eecs.umich.edu return new DataAccessException; 8124070Ssaidi@eecs.umich.edu else 8133825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8143825Ssaidi@eecs.umich.edu } 8153825Ssaidi@eecs.umich.edu goto regAccessOk; 8163825Ssaidi@eecs.umich.edu 8173825Ssaidi@eecs.umich.edu 8183824Ssaidi@eecs.umich.eduregAccessOk: 8193804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8203811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8218105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 8223806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8233806Ssaidi@eecs.umich.edu return NoFault; 8243804Ssaidi@eecs.umich.edu}; 8253804Ssaidi@eecs.umich.edu 8266022Sgblack@eecs.umich.eduFault 8276023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 8286022Sgblack@eecs.umich.edu{ 8296023Snate@binkert.org if (mode == Execute) 8306022Sgblack@eecs.umich.edu return translateInst(req, tc); 8316022Sgblack@eecs.umich.edu else 8326023Snate@binkert.org return translateData(req, tc, mode == Write); 8336022Sgblack@eecs.umich.edu} 8346022Sgblack@eecs.umich.edu 8355894Sgblack@eecs.umich.eduvoid 8366022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 8376023Snate@binkert.org Translation *translation, Mode mode) 8385894Sgblack@eecs.umich.edu{ 8395894Sgblack@eecs.umich.edu assert(translation); 8406023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8415894Sgblack@eecs.umich.edu} 8425894Sgblack@eecs.umich.edu 8434997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8444997Sgblack@eecs.umich.edu 8453806Ssaidi@eecs.umich.eduTick 8466022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8473806Ssaidi@eecs.umich.edu{ 8483823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8493823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8504070Ssaidi@eecs.umich.edu uint64_t temp; 8513823Ssaidi@eecs.umich.edu 8523823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8533823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8543823Ssaidi@eecs.umich.edu 8556022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 8564990Sgblack@eecs.umich.edu 8573823Ssaidi@eecs.umich.edu switch (asi) { 8583823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8593823Ssaidi@eecs.umich.edu assert(va == 0); 8604172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8613823Ssaidi@eecs.umich.edu break; 8623823Ssaidi@eecs.umich.edu case ASI_MMU: 8633823Ssaidi@eecs.umich.edu switch (va) { 8643823Ssaidi@eecs.umich.edu case 0x8: 8654172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8663823Ssaidi@eecs.umich.edu break; 8673823Ssaidi@eecs.umich.edu case 0x10: 8684172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8693823Ssaidi@eecs.umich.edu break; 8703823Ssaidi@eecs.umich.edu default: 8713823Ssaidi@eecs.umich.edu goto doMmuReadError; 8723823Ssaidi@eecs.umich.edu } 8733823Ssaidi@eecs.umich.edu break; 8743824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8754172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8763824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8773824Ssaidi@eecs.umich.edu break; 8783823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8793823Ssaidi@eecs.umich.edu assert(va == 0); 8804990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8833823Ssaidi@eecs.umich.edu assert(va == 0); 8844990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8853823Ssaidi@eecs.umich.edu break; 8863823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8873823Ssaidi@eecs.umich.edu assert(va == 0); 8884990Sgblack@eecs.umich.edu pkt->set(c0_config); 8893823Ssaidi@eecs.umich.edu break; 8903823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8913823Ssaidi@eecs.umich.edu assert(va == 0); 8924990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 8933823Ssaidi@eecs.umich.edu break; 8943823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8953823Ssaidi@eecs.umich.edu assert(va == 0); 8964990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 8973823Ssaidi@eecs.umich.edu break; 8983823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8993823Ssaidi@eecs.umich.edu assert(va == 0); 9004990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9013823Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9033823Ssaidi@eecs.umich.edu assert(va == 0); 9044990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9053823Ssaidi@eecs.umich.edu break; 9063823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9073823Ssaidi@eecs.umich.edu assert(va == 0); 9084990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9093823Ssaidi@eecs.umich.edu break; 9103823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9113823Ssaidi@eecs.umich.edu assert(va == 0); 9124990Sgblack@eecs.umich.edu pkt->set(cx_config); 9133823Ssaidi@eecs.umich.edu break; 9143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9153823Ssaidi@eecs.umich.edu assert(va == 0); 9164990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9173823Ssaidi@eecs.umich.edu break; 9183823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9193823Ssaidi@eecs.umich.edu assert(va == 0); 9204990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9213823Ssaidi@eecs.umich.edu break; 9223823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9233823Ssaidi@eecs.umich.edu assert(va == 0); 9244990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9253823Ssaidi@eecs.umich.edu break; 9263826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9273912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9283826Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9303823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9314172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9323823Ssaidi@eecs.umich.edu break; 9333826Ssaidi@eecs.umich.edu case ASI_IMMU: 9343826Ssaidi@eecs.umich.edu switch (va) { 9353833Ssaidi@eecs.umich.edu case 0x0: 9364990Sgblack@eecs.umich.edu temp = itb->tag_access; 9373833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9383833Ssaidi@eecs.umich.edu break; 9393906Ssaidi@eecs.umich.edu case 0x18: 9404990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9413906Ssaidi@eecs.umich.edu break; 9423826Ssaidi@eecs.umich.edu case 0x30: 9434990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9443826Ssaidi@eecs.umich.edu break; 9453826Ssaidi@eecs.umich.edu default: 9463826Ssaidi@eecs.umich.edu goto doMmuReadError; 9473826Ssaidi@eecs.umich.edu } 9483826Ssaidi@eecs.umich.edu break; 9493823Ssaidi@eecs.umich.edu case ASI_DMMU: 9503823Ssaidi@eecs.umich.edu switch (va) { 9513833Ssaidi@eecs.umich.edu case 0x0: 9524990Sgblack@eecs.umich.edu temp = tag_access; 9533833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9543833Ssaidi@eecs.umich.edu break; 9553906Ssaidi@eecs.umich.edu case 0x18: 9564990Sgblack@eecs.umich.edu pkt->set(sfsr); 9573906Ssaidi@eecs.umich.edu break; 9583906Ssaidi@eecs.umich.edu case 0x20: 9594990Sgblack@eecs.umich.edu pkt->set(sfar); 9603906Ssaidi@eecs.umich.edu break; 9613826Ssaidi@eecs.umich.edu case 0x30: 9624990Sgblack@eecs.umich.edu pkt->set(tag_access); 9633826Ssaidi@eecs.umich.edu break; 9643823Ssaidi@eecs.umich.edu case 0x80: 9654172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9663823Ssaidi@eecs.umich.edu break; 9673823Ssaidi@eecs.umich.edu default: 9683823Ssaidi@eecs.umich.edu goto doMmuReadError; 9693823Ssaidi@eecs.umich.edu } 9703823Ssaidi@eecs.umich.edu break; 9713833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9724070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9734990Sgblack@eecs.umich.edu tag_access, 9744990Sgblack@eecs.umich.edu c0_tsb_ps0, 9754990Sgblack@eecs.umich.edu c0_config, 9764990Sgblack@eecs.umich.edu cx_tsb_ps0, 9774990Sgblack@eecs.umich.edu cx_config)); 9783833Ssaidi@eecs.umich.edu break; 9793833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9804070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9814990Sgblack@eecs.umich.edu tag_access, 9824990Sgblack@eecs.umich.edu c0_tsb_ps1, 9834990Sgblack@eecs.umich.edu c0_config, 9844990Sgblack@eecs.umich.edu cx_tsb_ps1, 9854990Sgblack@eecs.umich.edu cx_config)); 9863833Ssaidi@eecs.umich.edu break; 9873899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9884070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9894990Sgblack@eecs.umich.edu itb->tag_access, 9904990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 9914990Sgblack@eecs.umich.edu itb->c0_config, 9924990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 9934990Sgblack@eecs.umich.edu itb->cx_config)); 9943899Ssaidi@eecs.umich.edu break; 9953899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 9964070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9974990Sgblack@eecs.umich.edu itb->tag_access, 9984990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 9994990Sgblack@eecs.umich.edu itb->c0_config, 10004990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10014990Sgblack@eecs.umich.edu itb->cx_config)); 10023899Ssaidi@eecs.umich.edu break; 10034103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10045646Sgblack@eecs.umich.edu { 10055646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10065646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10075646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10085646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10095646Sgblack@eecs.umich.edu } 10104103Ssaidi@eecs.umich.edu break; 10114103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10125646Sgblack@eecs.umich.edu { 10135646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10145646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10155646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10165646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 10175704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 10185646Sgblack@eecs.umich.edu pkt->set(temp); 10195646Sgblack@eecs.umich.edu } 10204103Ssaidi@eecs.umich.edu break; 10213823Ssaidi@eecs.umich.edu default: 10223823Ssaidi@eecs.umich.edudoMmuReadError: 10233823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10243823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10253823Ssaidi@eecs.umich.edu } 10264870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10275100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 10283806Ssaidi@eecs.umich.edu} 10293806Ssaidi@eecs.umich.edu 10303806Ssaidi@eecs.umich.eduTick 10316022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10323806Ssaidi@eecs.umich.edu{ 10337518Sgblack@eecs.umich.edu uint64_t data = pkt->get<uint64_t>(); 10343823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10353823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10363823Ssaidi@eecs.umich.edu 10373826Ssaidi@eecs.umich.edu Addr ta_insert; 10383826Ssaidi@eecs.umich.edu Addr va_insert; 10393826Ssaidi@eecs.umich.edu Addr ct_insert; 10403826Ssaidi@eecs.umich.edu int part_insert; 10413826Ssaidi@eecs.umich.edu int entry_insert = -1; 10423826Ssaidi@eecs.umich.edu bool real_insert; 10433863Ssaidi@eecs.umich.edu bool ignore; 10443863Ssaidi@eecs.umich.edu int part_id; 10453863Ssaidi@eecs.umich.edu int ctx_id; 10463826Ssaidi@eecs.umich.edu PageTableEntry pte; 10473826Ssaidi@eecs.umich.edu 10483825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10493823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10503823Ssaidi@eecs.umich.edu 10516022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 10524990Sgblack@eecs.umich.edu 10533823Ssaidi@eecs.umich.edu switch (asi) { 10543823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10553823Ssaidi@eecs.umich.edu assert(va == 0); 10564172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10573823Ssaidi@eecs.umich.edu break; 10583823Ssaidi@eecs.umich.edu case ASI_MMU: 10593823Ssaidi@eecs.umich.edu switch (va) { 10603823Ssaidi@eecs.umich.edu case 0x8: 10614172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10623823Ssaidi@eecs.umich.edu break; 10633823Ssaidi@eecs.umich.edu case 0x10: 10644172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10653823Ssaidi@eecs.umich.edu break; 10663823Ssaidi@eecs.umich.edu default: 10673823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10683823Ssaidi@eecs.umich.edu } 10693823Ssaidi@eecs.umich.edu break; 10703824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10713825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10724172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10733824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10743824Ssaidi@eecs.umich.edu break; 10753823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10763823Ssaidi@eecs.umich.edu assert(va == 0); 10774990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10783823Ssaidi@eecs.umich.edu break; 10793823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10803823Ssaidi@eecs.umich.edu assert(va == 0); 10814990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10823823Ssaidi@eecs.umich.edu break; 10833823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10843823Ssaidi@eecs.umich.edu assert(va == 0); 10854990Sgblack@eecs.umich.edu c0_config = data; 10863823Ssaidi@eecs.umich.edu break; 10873823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10883823Ssaidi@eecs.umich.edu assert(va == 0); 10894990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 10903823Ssaidi@eecs.umich.edu break; 10913823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10923823Ssaidi@eecs.umich.edu assert(va == 0); 10934990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 10943823Ssaidi@eecs.umich.edu break; 10953823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10963823Ssaidi@eecs.umich.edu assert(va == 0); 10974990Sgblack@eecs.umich.edu itb->c0_config = data; 10983823Ssaidi@eecs.umich.edu break; 10993823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11003823Ssaidi@eecs.umich.edu assert(va == 0); 11014990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11023823Ssaidi@eecs.umich.edu break; 11033823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11043823Ssaidi@eecs.umich.edu assert(va == 0); 11054990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11063823Ssaidi@eecs.umich.edu break; 11073823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11083823Ssaidi@eecs.umich.edu assert(va == 0); 11094990Sgblack@eecs.umich.edu cx_config = data; 11103823Ssaidi@eecs.umich.edu break; 11113823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11123823Ssaidi@eecs.umich.edu assert(va == 0); 11134990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11143823Ssaidi@eecs.umich.edu break; 11153823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11163823Ssaidi@eecs.umich.edu assert(va == 0); 11174990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11183823Ssaidi@eecs.umich.edu break; 11193823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11203823Ssaidi@eecs.umich.edu assert(va == 0); 11214990Sgblack@eecs.umich.edu itb->cx_config = data; 11223823Ssaidi@eecs.umich.edu break; 11233825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11243825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11255823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11263825Ssaidi@eecs.umich.edu break; 11273823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11283823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11294172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11303823Ssaidi@eecs.umich.edu break; 11313826Ssaidi@eecs.umich.edu case ASI_IMMU: 11323826Ssaidi@eecs.umich.edu switch (va) { 11333906Ssaidi@eecs.umich.edu case 0x18: 11344990Sgblack@eecs.umich.edu itb->sfsr = data; 11353906Ssaidi@eecs.umich.edu break; 11363826Ssaidi@eecs.umich.edu case 0x30: 11373916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11384990Sgblack@eecs.umich.edu itb->tag_access = data; 11393826Ssaidi@eecs.umich.edu break; 11403826Ssaidi@eecs.umich.edu default: 11413826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11423826Ssaidi@eecs.umich.edu } 11433826Ssaidi@eecs.umich.edu break; 11443826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11453826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11463826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11473826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11484990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11493826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11503826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11514172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11523826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11533826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11543826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11553826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11563826Ssaidi@eecs.umich.edu pte, entry_insert); 11573826Ssaidi@eecs.umich.edu break; 11583826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11593826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11603826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11613826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11624990Sgblack@eecs.umich.edu ta_insert = tag_access; 11633826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11643826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11654172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11663826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11673826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11683826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11695555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11705555Snate@binkert.org entry_insert); 11713826Ssaidi@eecs.umich.edu break; 11723863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11733863Ssaidi@eecs.umich.edu ignore = false; 11743863Ssaidi@eecs.umich.edu ctx_id = -1; 11754172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11763863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11773863Ssaidi@eecs.umich.edu case 0: 11784172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11793863Ssaidi@eecs.umich.edu break; 11803863Ssaidi@eecs.umich.edu case 1: 11813863Ssaidi@eecs.umich.edu ignore = true; 11823863Ssaidi@eecs.umich.edu break; 11833863Ssaidi@eecs.umich.edu case 3: 11843863Ssaidi@eecs.umich.edu ctx_id = 0; 11853863Ssaidi@eecs.umich.edu break; 11863863Ssaidi@eecs.umich.edu default: 11873863Ssaidi@eecs.umich.edu ignore = true; 11883863Ssaidi@eecs.umich.edu } 11893863Ssaidi@eecs.umich.edu 11907741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 11913863Ssaidi@eecs.umich.edu case 0: // demap page 11923863Ssaidi@eecs.umich.edu if (!ignore) 11933863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11943863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11953863Ssaidi@eecs.umich.edu break; 11967741Sgblack@eecs.umich.edu case 1: // demap context 11973863Ssaidi@eecs.umich.edu if (!ignore) 11983863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11993863Ssaidi@eecs.umich.edu break; 12003863Ssaidi@eecs.umich.edu case 2: 12013863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12023863Ssaidi@eecs.umich.edu break; 12033863Ssaidi@eecs.umich.edu default: 12043863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12053863Ssaidi@eecs.umich.edu } 12063863Ssaidi@eecs.umich.edu break; 12073823Ssaidi@eecs.umich.edu case ASI_DMMU: 12083823Ssaidi@eecs.umich.edu switch (va) { 12093906Ssaidi@eecs.umich.edu case 0x18: 12104990Sgblack@eecs.umich.edu sfsr = data; 12113906Ssaidi@eecs.umich.edu break; 12123826Ssaidi@eecs.umich.edu case 0x30: 12133916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12144990Sgblack@eecs.umich.edu tag_access = data; 12153826Ssaidi@eecs.umich.edu break; 12163823Ssaidi@eecs.umich.edu case 0x80: 12174172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12183823Ssaidi@eecs.umich.edu break; 12193823Ssaidi@eecs.umich.edu default: 12203823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12213823Ssaidi@eecs.umich.edu } 12223823Ssaidi@eecs.umich.edu break; 12233863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12243863Ssaidi@eecs.umich.edu ignore = false; 12253863Ssaidi@eecs.umich.edu ctx_id = -1; 12264172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12273863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12283863Ssaidi@eecs.umich.edu case 0: 12294172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12303863Ssaidi@eecs.umich.edu break; 12313863Ssaidi@eecs.umich.edu case 1: 12324172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12333863Ssaidi@eecs.umich.edu break; 12343863Ssaidi@eecs.umich.edu case 3: 12353863Ssaidi@eecs.umich.edu ctx_id = 0; 12363863Ssaidi@eecs.umich.edu break; 12373863Ssaidi@eecs.umich.edu default: 12383863Ssaidi@eecs.umich.edu ignore = true; 12393863Ssaidi@eecs.umich.edu } 12403863Ssaidi@eecs.umich.edu 12417741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12423863Ssaidi@eecs.umich.edu case 0: // demap page 12433863Ssaidi@eecs.umich.edu if (!ignore) 12443863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12453863Ssaidi@eecs.umich.edu break; 12467741Sgblack@eecs.umich.edu case 1: // demap context 12473863Ssaidi@eecs.umich.edu if (!ignore) 12483863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12493863Ssaidi@eecs.umich.edu break; 12503863Ssaidi@eecs.umich.edu case 2: 12513863Ssaidi@eecs.umich.edu demapAll(part_id); 12523863Ssaidi@eecs.umich.edu break; 12533863Ssaidi@eecs.umich.edu default: 12543863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12553863Ssaidi@eecs.umich.edu } 12563863Ssaidi@eecs.umich.edu break; 12574103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12585646Sgblack@eecs.umich.edu { 12595646Sgblack@eecs.umich.edu int msb; 12605646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12615646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12625646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 12635646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 12645704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12655646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 12665704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 12675646Sgblack@eecs.umich.edu } 12684103Ssaidi@eecs.umich.edu } 12694103Ssaidi@eecs.umich.edu break; 12704103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12714103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12725704Snate@binkert.org postInterrupt(bits(data, 5, 0), 0); 12734103Ssaidi@eecs.umich.edu break; 12745555Snate@binkert.org default: 12753823Ssaidi@eecs.umich.edudoMmuWriteError: 12763823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12773823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12783823Ssaidi@eecs.umich.edu } 12794870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12805100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 12813806Ssaidi@eecs.umich.edu} 12823806Ssaidi@eecs.umich.edu 12834997Sgblack@eecs.umich.edu#endif 12844997Sgblack@eecs.umich.edu 12853804Ssaidi@eecs.umich.eduvoid 12866022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12874070Ssaidi@eecs.umich.edu{ 12884070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12896022Sgblack@eecs.umich.edu TLB * itb = tc->getITBPtr(); 12904070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12914990Sgblack@eecs.umich.edu c0_tsb_ps0, 12924990Sgblack@eecs.umich.edu c0_config, 12934990Sgblack@eecs.umich.edu cx_tsb_ps0, 12944990Sgblack@eecs.umich.edu cx_config); 12954070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12964990Sgblack@eecs.umich.edu c0_tsb_ps1, 12974990Sgblack@eecs.umich.edu c0_config, 12984990Sgblack@eecs.umich.edu cx_tsb_ps1, 12994990Sgblack@eecs.umich.edu cx_config); 13004070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13014990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13024990Sgblack@eecs.umich.edu itb->c0_config, 13034990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13044990Sgblack@eecs.umich.edu itb->cx_config); 13054070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13064990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13074990Sgblack@eecs.umich.edu itb->c0_config, 13084990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13094990Sgblack@eecs.umich.edu itb->cx_config); 13104070Ssaidi@eecs.umich.edu} 13114070Ssaidi@eecs.umich.edu 13124070Ssaidi@eecs.umich.eduuint64_t 13136022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13144070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13154070Ssaidi@eecs.umich.edu{ 13164070Ssaidi@eecs.umich.edu uint64_t tsb; 13174070Ssaidi@eecs.umich.edu uint64_t config; 13184070Ssaidi@eecs.umich.edu 13194070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13204070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13214070Ssaidi@eecs.umich.edu config = c0_config; 13224070Ssaidi@eecs.umich.edu } else { 13234070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13244070Ssaidi@eecs.umich.edu config = cX_config; 13254070Ssaidi@eecs.umich.edu } 13264070Ssaidi@eecs.umich.edu 13274070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13284070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13294070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13304070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13314070Ssaidi@eecs.umich.edu 13324070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13334070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13344070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13354070Ssaidi@eecs.umich.edu 13364070Ssaidi@eecs.umich.edu return ptr; 13374070Ssaidi@eecs.umich.edu} 13384070Ssaidi@eecs.umich.edu 13394070Ssaidi@eecs.umich.eduvoid 13403804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13413804Ssaidi@eecs.umich.edu{ 13424000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13434000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13444000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13454000Ssaidi@eecs.umich.edu 13464000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13474000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13484000Ssaidi@eecs.umich.edu int cntr = 0; 13494000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13504000Ssaidi@eecs.umich.edu i = freeList.begin(); 13514000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13524000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13534000Ssaidi@eecs.umich.edu i++; 13544000Ssaidi@eecs.umich.edu } 13554000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13564000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13574000Ssaidi@eecs.umich.edu 13584990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13594990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13604990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13614990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13624990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13634990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13644990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13654990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13665276Ssaidi@eecs.umich.edu 13675276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13685276Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13695276Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13705276Ssaidi@eecs.umich.edu } 13716022Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 13723804Ssaidi@eecs.umich.edu} 13733804Ssaidi@eecs.umich.edu 13743804Ssaidi@eecs.umich.eduvoid 13753804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13763804Ssaidi@eecs.umich.edu{ 13774000Ssaidi@eecs.umich.edu int oldSize; 13784000Ssaidi@eecs.umich.edu 13794000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13804000Ssaidi@eecs.umich.edu if (oldSize != size) 13814000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13824000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13834000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13844000Ssaidi@eecs.umich.edu 13854000Ssaidi@eecs.umich.edu int cntr; 13864000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13874000Ssaidi@eecs.umich.edu 13884000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13894000Ssaidi@eecs.umich.edu freeList.clear(); 13904000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13914000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13924000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13934000Ssaidi@eecs.umich.edu 13944990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 13954990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 13964990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 13974990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 13984990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 13994990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14004990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14014990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14025276Ssaidi@eecs.umich.edu 14035276Ssaidi@eecs.umich.edu lookupTable.clear(); 14045276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14055276Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14065276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14075276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14085276Ssaidi@eecs.umich.edu 14095276Ssaidi@eecs.umich.edu } 14104990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14113804Ssaidi@eecs.umich.edu} 14123804Ssaidi@eecs.umich.edu 14137811Ssteve.reinhardt@amd.com} // namespace SparcISA 14144088Sbinkertn@umich.edu 14156022Sgblack@eecs.umich.eduSparcISA::TLB * 14166022Sgblack@eecs.umich.eduSparcTLBParams::create() 14173804Ssaidi@eecs.umich.edu{ 14186022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14193804Ssaidi@eecs.umich.edu} 1420