tlb.cc revision 8229
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 347678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 356335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 363569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 373824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 383811Ssaidi@eecs.umich.edu#include "base/trace.hh" 398229Snate@binkert.org#include "cpu/base.hh" 403811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 413823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 423823Ssaidi@eecs.umich.edu#include "mem/request.hh" 434103Ssaidi@eecs.umich.edu#include "sim/system.hh" 443569Sgblack@eecs.umich.edu 453804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 463804Ssaidi@eecs.umich.edu * */ 474088Sbinkertn@umich.edunamespace SparcISA { 483569Sgblack@eecs.umich.edu 495034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 505358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 513881Ssaidi@eecs.umich.edu cacheValid(false) 523804Ssaidi@eecs.umich.edu{ 533804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 543804Ssaidi@eecs.umich.edu if (size > 64) 555555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 563569Sgblack@eecs.umich.edu 573804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 583918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 593881Ssaidi@eecs.umich.edu 603881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 613881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 624990Sgblack@eecs.umich.edu 634990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 644990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 654990Sgblack@eecs.umich.edu c0_config = 0; 664990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 674990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 684990Sgblack@eecs.umich.edu cx_config = 0; 694990Sgblack@eecs.umich.edu sfsr = 0; 704990Sgblack@eecs.umich.edu tag_access = 0; 716022Sgblack@eecs.umich.edu sfar = 0; 726022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 736022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 743804Ssaidi@eecs.umich.edu} 753569Sgblack@eecs.umich.edu 763804Ssaidi@eecs.umich.eduvoid 773804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 783804Ssaidi@eecs.umich.edu{ 793804Ssaidi@eecs.umich.edu MapIter i; 803881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 813804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 823804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 833804Ssaidi@eecs.umich.edu t->used = false; 843804Ssaidi@eecs.umich.edu usedEntries--; 853804Ssaidi@eecs.umich.edu } 863804Ssaidi@eecs.umich.edu } 873804Ssaidi@eecs.umich.edu} 883569Sgblack@eecs.umich.edu 893569Sgblack@eecs.umich.edu 903804Ssaidi@eecs.umich.eduvoid 913804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 923826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 933804Ssaidi@eecs.umich.edu{ 943804Ssaidi@eecs.umich.edu MapIter i; 953826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 963907Ssaidi@eecs.umich.edu// TlbRange tr; 973826Ssaidi@eecs.umich.edu int x; 983811Ssaidi@eecs.umich.edu 993836Ssaidi@eecs.umich.edu cacheValid = false; 1003915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1013907Ssaidi@eecs.umich.edu /* tr.va = va; 1023881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1033881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1043881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1053881Ssaidi@eecs.umich.edu tr.real = real; 1063907Ssaidi@eecs.umich.edu*/ 1073881Ssaidi@eecs.umich.edu 1085555Snate@binkert.org DPRINTF(TLB, 1095555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1105555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1113881Ssaidi@eecs.umich.edu 1123881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1133907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1143907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1153907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1163907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1173907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1183907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1193907Ssaidi@eecs.umich.edu { 1203907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1213907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1223907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1233907Ssaidi@eecs.umich.edu 1243907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1253907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1263907Ssaidi@eecs.umich.edu tlb[x].used = false; 1273907Ssaidi@eecs.umich.edu usedEntries--; 1283907Ssaidi@eecs.umich.edu } 1293907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1303907Ssaidi@eecs.umich.edu } 1313907Ssaidi@eecs.umich.edu } 1323907Ssaidi@eecs.umich.edu } 1333907Ssaidi@eecs.umich.edu 1343826Ssaidi@eecs.umich.edu if (entry != -1) { 1353826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1363826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1373826Ssaidi@eecs.umich.edu } else { 1383881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1393881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1403881Ssaidi@eecs.umich.edu } else { 1413881Ssaidi@eecs.umich.edu x = lastReplaced; 1423881Ssaidi@eecs.umich.edu do { 1433881Ssaidi@eecs.umich.edu ++x; 1443881Ssaidi@eecs.umich.edu if (x == size) 1453881Ssaidi@eecs.umich.edu x = 0; 1463881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1473881Ssaidi@eecs.umich.edu goto insertAllLocked; 1483881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1493881Ssaidi@eecs.umich.edu lastReplaced = x; 1503881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1513881Ssaidi@eecs.umich.edu } 1523569Sgblack@eecs.umich.edu } 1533569Sgblack@eecs.umich.edu 1543881Ssaidi@eecs.umich.eduinsertAllLocked: 1553804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1563881Ssaidi@eecs.umich.edu if (!new_entry) { 1573826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1583881Ssaidi@eecs.umich.edu } 1593881Ssaidi@eecs.umich.edu 1603881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1613907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1623907Ssaidi@eecs.umich.edu usedEntries--; 1633929Ssaidi@eecs.umich.edu if (new_entry->valid) 1643929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1653907Ssaidi@eecs.umich.edu 1663907Ssaidi@eecs.umich.edu 1673804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1683804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1693881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1703804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1713804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1723804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1733804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1743804Ssaidi@eecs.umich.edu new_entry->used = true;; 1753804Ssaidi@eecs.umich.edu new_entry->valid = true; 1763804Ssaidi@eecs.umich.edu usedEntries++; 1773569Sgblack@eecs.umich.edu 1783863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1793863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1803804Ssaidi@eecs.umich.edu 1815555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 1825555Snate@binkert.org // but the one we just inserted 1833804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1843804Ssaidi@eecs.umich.edu clearUsedBits(); 1853804Ssaidi@eecs.umich.edu new_entry->used = true; 1863804Ssaidi@eecs.umich.edu usedEntries++; 1873804Ssaidi@eecs.umich.edu } 1883569Sgblack@eecs.umich.edu} 1893804Ssaidi@eecs.umich.edu 1903804Ssaidi@eecs.umich.edu 1913804Ssaidi@eecs.umich.eduTlbEntry* 1925555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 1935555Snate@binkert.org bool update_used) 1943804Ssaidi@eecs.umich.edu{ 1953804Ssaidi@eecs.umich.edu MapIter i; 1963804Ssaidi@eecs.umich.edu TlbRange tr; 1973804Ssaidi@eecs.umich.edu TlbEntry *t; 1983804Ssaidi@eecs.umich.edu 1993811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2003811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2013804Ssaidi@eecs.umich.edu // Assemble full address structure 2023804Ssaidi@eecs.umich.edu tr.va = va; 2035312Sgblack@eecs.umich.edu tr.size = 1; 2043804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2053804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2063804Ssaidi@eecs.umich.edu tr.real = real; 2073804Ssaidi@eecs.umich.edu 2083804Ssaidi@eecs.umich.edu // Try to find the entry 2093804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2103804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2113811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2123804Ssaidi@eecs.umich.edu return NULL; 2133804Ssaidi@eecs.umich.edu } 2143804Ssaidi@eecs.umich.edu 2153804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2163804Ssaidi@eecs.umich.edu t = i->second; 2173826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2183826Ssaidi@eecs.umich.edu t->pte.size()); 2194070Ssaidi@eecs.umich.edu 2205555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2215555Snate@binkert.org // one from virttophys() 2224070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2233804Ssaidi@eecs.umich.edu t->used = true; 2243804Ssaidi@eecs.umich.edu usedEntries++; 2253804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2263804Ssaidi@eecs.umich.edu clearUsedBits(); 2273804Ssaidi@eecs.umich.edu t->used = true; 2283804Ssaidi@eecs.umich.edu usedEntries++; 2293804Ssaidi@eecs.umich.edu } 2303804Ssaidi@eecs.umich.edu } 2313804Ssaidi@eecs.umich.edu 2323804Ssaidi@eecs.umich.edu return t; 2333804Ssaidi@eecs.umich.edu} 2343804Ssaidi@eecs.umich.edu 2353826Ssaidi@eecs.umich.eduvoid 2363826Ssaidi@eecs.umich.eduTLB::dumpAll() 2373826Ssaidi@eecs.umich.edu{ 2383863Ssaidi@eecs.umich.edu MapIter i; 2393826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2403826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2413826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2423826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2433826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2443826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2453826Ssaidi@eecs.umich.edu } 2463826Ssaidi@eecs.umich.edu } 2473826Ssaidi@eecs.umich.edu} 2483804Ssaidi@eecs.umich.edu 2493804Ssaidi@eecs.umich.eduvoid 2503804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2513804Ssaidi@eecs.umich.edu{ 2523804Ssaidi@eecs.umich.edu TlbRange tr; 2533804Ssaidi@eecs.umich.edu MapIter i; 2543804Ssaidi@eecs.umich.edu 2553863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2563863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2573863Ssaidi@eecs.umich.edu 2583836Ssaidi@eecs.umich.edu cacheValid = false; 2593836Ssaidi@eecs.umich.edu 2603804Ssaidi@eecs.umich.edu // Assemble full address structure 2613804Ssaidi@eecs.umich.edu tr.va = va; 2625312Sgblack@eecs.umich.edu tr.size = 1; 2633804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2643804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2653804Ssaidi@eecs.umich.edu tr.real = real; 2663804Ssaidi@eecs.umich.edu 2673804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2683804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2693804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2703863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2713804Ssaidi@eecs.umich.edu i->second->valid = false; 2723804Ssaidi@eecs.umich.edu if (i->second->used) { 2733804Ssaidi@eecs.umich.edu i->second->used = false; 2743804Ssaidi@eecs.umich.edu usedEntries--; 2753804Ssaidi@eecs.umich.edu } 2763881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2773804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2783804Ssaidi@eecs.umich.edu } 2793804Ssaidi@eecs.umich.edu} 2803804Ssaidi@eecs.umich.edu 2813804Ssaidi@eecs.umich.eduvoid 2823804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2833804Ssaidi@eecs.umich.edu{ 2843863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2853863Ssaidi@eecs.umich.edu partition_id, context_id); 2863836Ssaidi@eecs.umich.edu cacheValid = false; 2875555Snate@binkert.org for (int x = 0; x < size; x++) { 2883804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2893804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2903881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 2913881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2923881Ssaidi@eecs.umich.edu } 2933804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2943804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2953804Ssaidi@eecs.umich.edu tlb[x].used = false; 2963804Ssaidi@eecs.umich.edu usedEntries--; 2973804Ssaidi@eecs.umich.edu } 2983804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2993804Ssaidi@eecs.umich.edu } 3003804Ssaidi@eecs.umich.edu } 3013804Ssaidi@eecs.umich.edu} 3023804Ssaidi@eecs.umich.edu 3033804Ssaidi@eecs.umich.eduvoid 3043804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3053804Ssaidi@eecs.umich.edu{ 3063863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3073836Ssaidi@eecs.umich.edu cacheValid = false; 3085555Snate@binkert.org for (int x = 0; x < size; x++) { 3095288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3105288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3115288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3123804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3133804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3143804Ssaidi@eecs.umich.edu tlb[x].used = false; 3153804Ssaidi@eecs.umich.edu usedEntries--; 3163804Ssaidi@eecs.umich.edu } 3173804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3183804Ssaidi@eecs.umich.edu } 3193804Ssaidi@eecs.umich.edu } 3203804Ssaidi@eecs.umich.edu} 3213804Ssaidi@eecs.umich.edu 3223804Ssaidi@eecs.umich.eduvoid 3233804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3243804Ssaidi@eecs.umich.edu{ 3253836Ssaidi@eecs.umich.edu cacheValid = false; 3265555Snate@binkert.org lookupTable.clear(); 3273836Ssaidi@eecs.umich.edu 3285555Snate@binkert.org for (int x = 0; x < size; x++) { 3293881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3303881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3313804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3323907Ssaidi@eecs.umich.edu tlb[x].used = false; 3333804Ssaidi@eecs.umich.edu } 3343804Ssaidi@eecs.umich.edu usedEntries = 0; 3353804Ssaidi@eecs.umich.edu} 3363804Ssaidi@eecs.umich.edu 3373804Ssaidi@eecs.umich.eduuint64_t 3385555Snate@binkert.orgTLB::TteRead(int entry) 3395555Snate@binkert.org{ 3403881Ssaidi@eecs.umich.edu if (entry >= size) 3413881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3423881Ssaidi@eecs.umich.edu 3433804Ssaidi@eecs.umich.edu assert(entry < size); 3443881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3453881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3463881Ssaidi@eecs.umich.edu else 3473881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3483804Ssaidi@eecs.umich.edu} 3493804Ssaidi@eecs.umich.edu 3503804Ssaidi@eecs.umich.eduuint64_t 3515555Snate@binkert.orgTLB::TagRead(int entry) 3525555Snate@binkert.org{ 3533804Ssaidi@eecs.umich.edu assert(entry < size); 3543804Ssaidi@eecs.umich.edu uint64_t tag; 3553881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3563881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3573804Ssaidi@eecs.umich.edu 3583881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3593881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3603881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3613804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3623804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3633804Ssaidi@eecs.umich.edu return tag; 3643804Ssaidi@eecs.umich.edu} 3653804Ssaidi@eecs.umich.edu 3663804Ssaidi@eecs.umich.edubool 3673804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3683804Ssaidi@eecs.umich.edu{ 3693804Ssaidi@eecs.umich.edu if (am) 3703804Ssaidi@eecs.umich.edu return true; 3713804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3723804Ssaidi@eecs.umich.edu return false; 3733804Ssaidi@eecs.umich.edu return true; 3743804Ssaidi@eecs.umich.edu} 3753804Ssaidi@eecs.umich.edu 3763804Ssaidi@eecs.umich.eduvoid 3774990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3783804Ssaidi@eecs.umich.edu{ 3793804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3803804Ssaidi@eecs.umich.edu sfsr = 0x3; 3813804Ssaidi@eecs.umich.edu else 3823804Ssaidi@eecs.umich.edu sfsr = 1; 3833804Ssaidi@eecs.umich.edu 3843804Ssaidi@eecs.umich.edu if (write) 3853804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3863804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3873804Ssaidi@eecs.umich.edu if (se) 3883804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3893804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3903804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3913804Ssaidi@eecs.umich.edu} 3923804Ssaidi@eecs.umich.edu 3933826Ssaidi@eecs.umich.eduvoid 3944990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 3953826Ssaidi@eecs.umich.edu{ 3963916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 3973916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 3983916Ssaidi@eecs.umich.edu 3994990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4003826Ssaidi@eecs.umich.edu} 4013804Ssaidi@eecs.umich.edu 4023804Ssaidi@eecs.umich.eduvoid 4036022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4043804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4053804Ssaidi@eecs.umich.edu{ 4066022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4073811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4084990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4094990Sgblack@eecs.umich.edu sfar = a; 4103804Ssaidi@eecs.umich.edu} 4113804Ssaidi@eecs.umich.edu 4123804Ssaidi@eecs.umich.eduFault 4136022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 4143804Ssaidi@eecs.umich.edu{ 4154172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4163833Ssaidi@eecs.umich.edu 4173836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4183836Ssaidi@eecs.umich.edu TlbEntry *e; 4193836Ssaidi@eecs.umich.edu 4203836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4213836Ssaidi@eecs.umich.edu 4223836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4233836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4243836Ssaidi@eecs.umich.edu 4253836Ssaidi@eecs.umich.edu // Be fast if we can! 4263836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4276022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4286022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4296022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4306022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4315555Snate@binkert.org return NoFault; 4323836Ssaidi@eecs.umich.edu } 4333836Ssaidi@eecs.umich.edu } else { 4343836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4353836Ssaidi@eecs.umich.edu return NoFault; 4363836Ssaidi@eecs.umich.edu } 4373836Ssaidi@eecs.umich.edu } 4383836Ssaidi@eecs.umich.edu 4393833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4403833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4413833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4423833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4433833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4443833Ssaidi@eecs.umich.edu 4453833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4463833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4473833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4483804Ssaidi@eecs.umich.edu int context; 4493804Ssaidi@eecs.umich.edu ContextType ct; 4503804Ssaidi@eecs.umich.edu int asi; 4513804Ssaidi@eecs.umich.edu bool real = false; 4523804Ssaidi@eecs.umich.edu 4533833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4543833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4553811Ssaidi@eecs.umich.edu 4563804Ssaidi@eecs.umich.edu if (tl > 0) { 4573804Ssaidi@eecs.umich.edu asi = ASI_N; 4583804Ssaidi@eecs.umich.edu ct = Nucleus; 4593804Ssaidi@eecs.umich.edu context = 0; 4603804Ssaidi@eecs.umich.edu } else { 4613804Ssaidi@eecs.umich.edu asi = ASI_P; 4623804Ssaidi@eecs.umich.edu ct = Primary; 4633833Ssaidi@eecs.umich.edu context = pri_context; 4643804Ssaidi@eecs.umich.edu } 4653804Ssaidi@eecs.umich.edu 4663833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4673836Ssaidi@eecs.umich.edu cacheValid = true; 4683836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4696022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4703836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4713804Ssaidi@eecs.umich.edu return NoFault; 4723804Ssaidi@eecs.umich.edu } 4733804Ssaidi@eecs.umich.edu 4743836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4753836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4764990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 4773804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4783804Ssaidi@eecs.umich.edu } 4793804Ssaidi@eecs.umich.edu 4803804Ssaidi@eecs.umich.edu if (addr_mask) 4813804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4823804Ssaidi@eecs.umich.edu 4833804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4844990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 4853804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4863804Ssaidi@eecs.umich.edu } 4873804Ssaidi@eecs.umich.edu 4883833Ssaidi@eecs.umich.edu if (!lsu_im) { 4893836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4903804Ssaidi@eecs.umich.edu real = true; 4913804Ssaidi@eecs.umich.edu context = 0; 4923804Ssaidi@eecs.umich.edu } else { 4933804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4943804Ssaidi@eecs.umich.edu } 4953804Ssaidi@eecs.umich.edu 4963804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4974990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 4983804Ssaidi@eecs.umich.edu if (real) 4993804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5003804Ssaidi@eecs.umich.edu else 5014997Sgblack@eecs.umich.edu#if FULL_SYSTEM 5023804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5034997Sgblack@eecs.umich.edu#else 5044997Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5054997Sgblack@eecs.umich.edu#endif 5063804Ssaidi@eecs.umich.edu } 5073804Ssaidi@eecs.umich.edu 5083804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5093804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5104990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5114990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5123804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5133804Ssaidi@eecs.umich.edu } 5143804Ssaidi@eecs.umich.edu 5153836Ssaidi@eecs.umich.edu // cache translation date for next translation 5163836Ssaidi@eecs.umich.edu cacheValid = true; 5173836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5186022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5193836Ssaidi@eecs.umich.edu 5205555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5213836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5223804Ssaidi@eecs.umich.edu return NoFault; 5233804Ssaidi@eecs.umich.edu} 5243804Ssaidi@eecs.umich.edu 5253804Ssaidi@eecs.umich.eduFault 5266022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 5273804Ssaidi@eecs.umich.edu{ 5285555Snate@binkert.org /* 5295555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5305555Snate@binkert.org * it faster! 5315555Snate@binkert.org */ 5324172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5333836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5343836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5353836Ssaidi@eecs.umich.edu ASI asi; 5363836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5373836Ssaidi@eecs.umich.edu bool implicit = false; 5383836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5395570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5403833Ssaidi@eecs.umich.edu 5413836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5423836Ssaidi@eecs.umich.edu vaddr, size, asi); 5433836Ssaidi@eecs.umich.edu 5443929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5453929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5463929Ssaidi@eecs.umich.edu freeList.size()); 5473836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5483836Ssaidi@eecs.umich.edu implicit = true; 5493836Ssaidi@eecs.umich.edu 5504996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5514996Sgblack@eecs.umich.edu // trap later 5524996Sgblack@eecs.umich.edu if (!unaligned) { 5534996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5544996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5554996Sgblack@eecs.umich.edu return NoFault; 5564996Sgblack@eecs.umich.edu } 5574996Sgblack@eecs.umich.edu 5584996Sgblack@eecs.umich.edu // Be fast if we can! 5594996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5604996Sgblack@eecs.umich.edu 5614996Sgblack@eecs.umich.edu 5624996Sgblack@eecs.umich.edu 5634996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5644996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5654996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5664996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5674996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5684996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5695555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5705555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5715736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5725555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5735555Snate@binkert.org return NoFault; 5744996Sgblack@eecs.umich.edu } // if matched 5754996Sgblack@eecs.umich.edu } // if cache entry valid 5764996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5774996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5784996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5794996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 5804996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5814996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5825555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5835555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5845736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 5855555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5865555Snate@binkert.org return NoFault; 5874996Sgblack@eecs.umich.edu } // if matched 5884996Sgblack@eecs.umich.edu } // if cache entry valid 5894996Sgblack@eecs.umich.edu } 5903836Ssaidi@eecs.umich.edu } 5913836Ssaidi@eecs.umich.edu 5923833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 5933833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 5943833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 5953833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 5963833Ssaidi@eecs.umich.edu 5973833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 5983833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 5993833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6003916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6013833Ssaidi@eecs.umich.edu 6023804Ssaidi@eecs.umich.edu bool real = false; 6033832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6043832Ssaidi@eecs.umich.edu int context = 0; 6053804Ssaidi@eecs.umich.edu 6063804Ssaidi@eecs.umich.edu TlbEntry *e; 6073804Ssaidi@eecs.umich.edu 6083833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6095555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6103804Ssaidi@eecs.umich.edu 6113804Ssaidi@eecs.umich.edu if (implicit) { 6123804Ssaidi@eecs.umich.edu if (tl > 0) { 6133804Ssaidi@eecs.umich.edu asi = ASI_N; 6143804Ssaidi@eecs.umich.edu ct = Nucleus; 6153804Ssaidi@eecs.umich.edu context = 0; 6163804Ssaidi@eecs.umich.edu } else { 6173804Ssaidi@eecs.umich.edu asi = ASI_P; 6183804Ssaidi@eecs.umich.edu ct = Primary; 6193833Ssaidi@eecs.umich.edu context = pri_context; 6203804Ssaidi@eecs.umich.edu } 6213910Ssaidi@eecs.umich.edu } else { 6223804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6237741Sgblack@eecs.umich.edu if (!priv && !hpriv && !asiIsUnPriv(asi)) { 6243804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6254990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6263804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6273804Ssaidi@eecs.umich.edu } 6283910Ssaidi@eecs.umich.edu 6297741Sgblack@eecs.umich.edu if (!hpriv && asiIsHPriv(asi)) { 6304990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6313804Ssaidi@eecs.umich.edu return new DataAccessException; 6323804Ssaidi@eecs.umich.edu } 6333804Ssaidi@eecs.umich.edu 6347741Sgblack@eecs.umich.edu if (asiIsPrimary(asi)) { 6353910Ssaidi@eecs.umich.edu context = pri_context; 6363910Ssaidi@eecs.umich.edu ct = Primary; 6377741Sgblack@eecs.umich.edu } else if (asiIsSecondary(asi)) { 6383910Ssaidi@eecs.umich.edu context = sec_context; 6393910Ssaidi@eecs.umich.edu ct = Secondary; 6407741Sgblack@eecs.umich.edu } else if (asiIsNucleus(asi)) { 6413910Ssaidi@eecs.umich.edu ct = Nucleus; 6423910Ssaidi@eecs.umich.edu context = 0; 6433910Ssaidi@eecs.umich.edu } else { // ???? 6443910Ssaidi@eecs.umich.edu ct = Primary; 6453910Ssaidi@eecs.umich.edu context = pri_context; 6463910Ssaidi@eecs.umich.edu } 6473902Ssaidi@eecs.umich.edu } 6483804Ssaidi@eecs.umich.edu 6493926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6507741Sgblack@eecs.umich.edu if (asiIsLittle(asi)) 6513804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6524989Sgblack@eecs.umich.edu 6534989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6547741Sgblack@eecs.umich.edu // load differs from a regular one, other than what happens concerning 6557741Sgblack@eecs.umich.edu // nfo and e bits in the TTE 6567741Sgblack@eecs.umich.edu// if (asiIsNoFault(asi)) 6574989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6583856Ssaidi@eecs.umich.edu 6597741Sgblack@eecs.umich.edu if (asiIsPartialStore(asi)) 6603804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6614103Ssaidi@eecs.umich.edu 6627741Sgblack@eecs.umich.edu if (asiIsCmt(asi)) 6634191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6644191Ssaidi@eecs.umich.edu 6657741Sgblack@eecs.umich.edu if (asiIsInterrupt(asi)) 6664103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6677741Sgblack@eecs.umich.edu if (asiIsMmu(asi)) 6683804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6697741Sgblack@eecs.umich.edu if (asiIsScratchPad(asi)) 6703804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6717741Sgblack@eecs.umich.edu if (asiIsQueue(asi)) 6723824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6737741Sgblack@eecs.umich.edu if (asiIsSparcError(asi)) 6743825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6753823Ssaidi@eecs.umich.edu 6767741Sgblack@eecs.umich.edu if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 6777741Sgblack@eecs.umich.edu !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 6783823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6793804Ssaidi@eecs.umich.edu } 6803804Ssaidi@eecs.umich.edu 6813826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6824996Sgblack@eecs.umich.edu if (unaligned) { 6834990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 6843826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6853826Ssaidi@eecs.umich.edu } 6863826Ssaidi@eecs.umich.edu 6873826Ssaidi@eecs.umich.edu if (addr_mask) 6883826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6893826Ssaidi@eecs.umich.edu 6903826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 6914990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 6923826Ssaidi@eecs.umich.edu return new DataAccessException; 6933826Ssaidi@eecs.umich.edu } 6943826Ssaidi@eecs.umich.edu 6957741Sgblack@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 6963804Ssaidi@eecs.umich.edu real = true; 6973804Ssaidi@eecs.umich.edu context = 0; 6985555Snate@binkert.org } 6993804Ssaidi@eecs.umich.edu 7007741Sgblack@eecs.umich.edu if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 7013836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7023804Ssaidi@eecs.umich.edu return NoFault; 7033804Ssaidi@eecs.umich.edu } 7043804Ssaidi@eecs.umich.edu 7053836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7063804Ssaidi@eecs.umich.edu 7073804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7084990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7093811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7103804Ssaidi@eecs.umich.edu if (real) 7113804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7123804Ssaidi@eecs.umich.edu else 7134997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7143804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7154997Sgblack@eecs.umich.edu#else 7164997Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7174997Sgblack@eecs.umich.edu#endif 7183804Ssaidi@eecs.umich.edu 7193804Ssaidi@eecs.umich.edu } 7203804Ssaidi@eecs.umich.edu 7213928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7224990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7234990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7243928Ssaidi@eecs.umich.edu return new DataAccessException; 7253928Ssaidi@eecs.umich.edu } 7263804Ssaidi@eecs.umich.edu 7273804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7284990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7294990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7303804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7313804Ssaidi@eecs.umich.edu } 7323804Ssaidi@eecs.umich.edu 7337741Sgblack@eecs.umich.edu if (e->pte.nofault() && !asiIsNoFault(asi)) { 7344990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7354990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7363804Ssaidi@eecs.umich.edu return new DataAccessException; 7373804Ssaidi@eecs.umich.edu } 7383804Ssaidi@eecs.umich.edu 7397741Sgblack@eecs.umich.edu if (e->pte.sideffect() && asiIsNoFault(asi)) { 7404990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7414990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7423928Ssaidi@eecs.umich.edu return new DataAccessException; 7433928Ssaidi@eecs.umich.edu } 7443928Ssaidi@eecs.umich.edu 7454090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7465736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 7473804Ssaidi@eecs.umich.edu 7483836Ssaidi@eecs.umich.edu // cache translation date for next translation 7493836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7503881Ssaidi@eecs.umich.edu if (!cacheValid) { 7513881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7523881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7533881Ssaidi@eecs.umich.edu } 7543881Ssaidi@eecs.umich.edu 7553836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7563836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7573836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7583836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7593836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7603836Ssaidi@eecs.umich.edu if (implicit) 7613836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7623836Ssaidi@eecs.umich.edu } 7633881Ssaidi@eecs.umich.edu cacheValid = true; 7645555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7653836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7663804Ssaidi@eecs.umich.edu return NoFault; 7674103Ssaidi@eecs.umich.edu 7683806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7694103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7704103Ssaidi@eecs.umich.edu if (!hpriv) { 7714990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7724103Ssaidi@eecs.umich.edu if (priv) 7734103Ssaidi@eecs.umich.edu return new DataAccessException; 7744103Ssaidi@eecs.umich.edu else 7754103Ssaidi@eecs.umich.edu return new PrivilegedAction; 7764103Ssaidi@eecs.umich.edu } 7774103Ssaidi@eecs.umich.edu 7785570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 7795570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 7804990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7814103Ssaidi@eecs.umich.edu return new DataAccessException; 7824103Ssaidi@eecs.umich.edu } 7834103Ssaidi@eecs.umich.edu 7844103Ssaidi@eecs.umich.edu goto regAccessOk; 7854103Ssaidi@eecs.umich.edu 7863804Ssaidi@eecs.umich.edu 7873806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7883806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7894990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7903806Ssaidi@eecs.umich.edu return new DataAccessException; 7913806Ssaidi@eecs.umich.edu } 7923824Ssaidi@eecs.umich.edu goto regAccessOk; 7933824Ssaidi@eecs.umich.edu 7943824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7953824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7964990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7973824Ssaidi@eecs.umich.edu return new PrivilegedAction; 7983824Ssaidi@eecs.umich.edu } 7995570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8004990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8013824Ssaidi@eecs.umich.edu return new DataAccessException; 8023824Ssaidi@eecs.umich.edu } 8033824Ssaidi@eecs.umich.edu goto regAccessOk; 8043824Ssaidi@eecs.umich.edu 8053825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8063825Ssaidi@eecs.umich.edu if (!hpriv) { 8074990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8084070Ssaidi@eecs.umich.edu if (priv) 8093825Ssaidi@eecs.umich.edu return new DataAccessException; 8104070Ssaidi@eecs.umich.edu else 8113825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8123825Ssaidi@eecs.umich.edu } 8133825Ssaidi@eecs.umich.edu goto regAccessOk; 8143825Ssaidi@eecs.umich.edu 8153825Ssaidi@eecs.umich.edu 8163824Ssaidi@eecs.umich.eduregAccessOk: 8173804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8183811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8198105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 8203806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8213806Ssaidi@eecs.umich.edu return NoFault; 8223804Ssaidi@eecs.umich.edu}; 8233804Ssaidi@eecs.umich.edu 8246022Sgblack@eecs.umich.eduFault 8256023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 8266022Sgblack@eecs.umich.edu{ 8276023Snate@binkert.org if (mode == Execute) 8286022Sgblack@eecs.umich.edu return translateInst(req, tc); 8296022Sgblack@eecs.umich.edu else 8306023Snate@binkert.org return translateData(req, tc, mode == Write); 8316022Sgblack@eecs.umich.edu} 8326022Sgblack@eecs.umich.edu 8335894Sgblack@eecs.umich.eduvoid 8346022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 8356023Snate@binkert.org Translation *translation, Mode mode) 8365894Sgblack@eecs.umich.edu{ 8375894Sgblack@eecs.umich.edu assert(translation); 8386023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8395894Sgblack@eecs.umich.edu} 8405894Sgblack@eecs.umich.edu 8414997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8424997Sgblack@eecs.umich.edu 8433806Ssaidi@eecs.umich.eduTick 8446022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8453806Ssaidi@eecs.umich.edu{ 8463823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8473823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8484070Ssaidi@eecs.umich.edu uint64_t temp; 8493823Ssaidi@eecs.umich.edu 8503823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8513823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8523823Ssaidi@eecs.umich.edu 8536022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 8544990Sgblack@eecs.umich.edu 8553823Ssaidi@eecs.umich.edu switch (asi) { 8563823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8573823Ssaidi@eecs.umich.edu assert(va == 0); 8584172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8593823Ssaidi@eecs.umich.edu break; 8603823Ssaidi@eecs.umich.edu case ASI_MMU: 8613823Ssaidi@eecs.umich.edu switch (va) { 8623823Ssaidi@eecs.umich.edu case 0x8: 8634172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8643823Ssaidi@eecs.umich.edu break; 8653823Ssaidi@eecs.umich.edu case 0x10: 8664172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8673823Ssaidi@eecs.umich.edu break; 8683823Ssaidi@eecs.umich.edu default: 8693823Ssaidi@eecs.umich.edu goto doMmuReadError; 8703823Ssaidi@eecs.umich.edu } 8713823Ssaidi@eecs.umich.edu break; 8723824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8734172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8743824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8753824Ssaidi@eecs.umich.edu break; 8763823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8773823Ssaidi@eecs.umich.edu assert(va == 0); 8784990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8793823Ssaidi@eecs.umich.edu break; 8803823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8813823Ssaidi@eecs.umich.edu assert(va == 0); 8824990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8833823Ssaidi@eecs.umich.edu break; 8843823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8853823Ssaidi@eecs.umich.edu assert(va == 0); 8864990Sgblack@eecs.umich.edu pkt->set(c0_config); 8873823Ssaidi@eecs.umich.edu break; 8883823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8893823Ssaidi@eecs.umich.edu assert(va == 0); 8904990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 8913823Ssaidi@eecs.umich.edu break; 8923823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8933823Ssaidi@eecs.umich.edu assert(va == 0); 8944990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 8953823Ssaidi@eecs.umich.edu break; 8963823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8973823Ssaidi@eecs.umich.edu assert(va == 0); 8984990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 8993823Ssaidi@eecs.umich.edu break; 9003823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9013823Ssaidi@eecs.umich.edu assert(va == 0); 9024990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9033823Ssaidi@eecs.umich.edu break; 9043823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9053823Ssaidi@eecs.umich.edu assert(va == 0); 9064990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9073823Ssaidi@eecs.umich.edu break; 9083823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9093823Ssaidi@eecs.umich.edu assert(va == 0); 9104990Sgblack@eecs.umich.edu pkt->set(cx_config); 9113823Ssaidi@eecs.umich.edu break; 9123823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9133823Ssaidi@eecs.umich.edu assert(va == 0); 9144990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9153823Ssaidi@eecs.umich.edu break; 9163823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9173823Ssaidi@eecs.umich.edu assert(va == 0); 9184990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9193823Ssaidi@eecs.umich.edu break; 9203823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9213823Ssaidi@eecs.umich.edu assert(va == 0); 9224990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9233823Ssaidi@eecs.umich.edu break; 9243826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9253912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9263826Ssaidi@eecs.umich.edu break; 9273823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9283823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9294172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9303823Ssaidi@eecs.umich.edu break; 9313826Ssaidi@eecs.umich.edu case ASI_IMMU: 9323826Ssaidi@eecs.umich.edu switch (va) { 9333833Ssaidi@eecs.umich.edu case 0x0: 9344990Sgblack@eecs.umich.edu temp = itb->tag_access; 9353833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9363833Ssaidi@eecs.umich.edu break; 9373906Ssaidi@eecs.umich.edu case 0x18: 9384990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9393906Ssaidi@eecs.umich.edu break; 9403826Ssaidi@eecs.umich.edu case 0x30: 9414990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9423826Ssaidi@eecs.umich.edu break; 9433826Ssaidi@eecs.umich.edu default: 9443826Ssaidi@eecs.umich.edu goto doMmuReadError; 9453826Ssaidi@eecs.umich.edu } 9463826Ssaidi@eecs.umich.edu break; 9473823Ssaidi@eecs.umich.edu case ASI_DMMU: 9483823Ssaidi@eecs.umich.edu switch (va) { 9493833Ssaidi@eecs.umich.edu case 0x0: 9504990Sgblack@eecs.umich.edu temp = tag_access; 9513833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9523833Ssaidi@eecs.umich.edu break; 9533906Ssaidi@eecs.umich.edu case 0x18: 9544990Sgblack@eecs.umich.edu pkt->set(sfsr); 9553906Ssaidi@eecs.umich.edu break; 9563906Ssaidi@eecs.umich.edu case 0x20: 9574990Sgblack@eecs.umich.edu pkt->set(sfar); 9583906Ssaidi@eecs.umich.edu break; 9593826Ssaidi@eecs.umich.edu case 0x30: 9604990Sgblack@eecs.umich.edu pkt->set(tag_access); 9613826Ssaidi@eecs.umich.edu break; 9623823Ssaidi@eecs.umich.edu case 0x80: 9634172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9643823Ssaidi@eecs.umich.edu break; 9653823Ssaidi@eecs.umich.edu default: 9663823Ssaidi@eecs.umich.edu goto doMmuReadError; 9673823Ssaidi@eecs.umich.edu } 9683823Ssaidi@eecs.umich.edu break; 9693833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9704070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9714990Sgblack@eecs.umich.edu tag_access, 9724990Sgblack@eecs.umich.edu c0_tsb_ps0, 9734990Sgblack@eecs.umich.edu c0_config, 9744990Sgblack@eecs.umich.edu cx_tsb_ps0, 9754990Sgblack@eecs.umich.edu cx_config)); 9763833Ssaidi@eecs.umich.edu break; 9773833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9784070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9794990Sgblack@eecs.umich.edu tag_access, 9804990Sgblack@eecs.umich.edu c0_tsb_ps1, 9814990Sgblack@eecs.umich.edu c0_config, 9824990Sgblack@eecs.umich.edu cx_tsb_ps1, 9834990Sgblack@eecs.umich.edu cx_config)); 9843833Ssaidi@eecs.umich.edu break; 9853899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9864070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9874990Sgblack@eecs.umich.edu itb->tag_access, 9884990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 9894990Sgblack@eecs.umich.edu itb->c0_config, 9904990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 9914990Sgblack@eecs.umich.edu itb->cx_config)); 9923899Ssaidi@eecs.umich.edu break; 9933899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 9944070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9954990Sgblack@eecs.umich.edu itb->tag_access, 9964990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 9974990Sgblack@eecs.umich.edu itb->c0_config, 9984990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 9994990Sgblack@eecs.umich.edu itb->cx_config)); 10003899Ssaidi@eecs.umich.edu break; 10014103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10025646Sgblack@eecs.umich.edu { 10035646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10045646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10055646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10065646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10075646Sgblack@eecs.umich.edu } 10084103Ssaidi@eecs.umich.edu break; 10094103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10105646Sgblack@eecs.umich.edu { 10115646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10125646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10135646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10145646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 10155704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 10165646Sgblack@eecs.umich.edu pkt->set(temp); 10175646Sgblack@eecs.umich.edu } 10184103Ssaidi@eecs.umich.edu break; 10193823Ssaidi@eecs.umich.edu default: 10203823Ssaidi@eecs.umich.edudoMmuReadError: 10213823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10223823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10233823Ssaidi@eecs.umich.edu } 10244870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10255100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 10263806Ssaidi@eecs.umich.edu} 10273806Ssaidi@eecs.umich.edu 10283806Ssaidi@eecs.umich.eduTick 10296022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10303806Ssaidi@eecs.umich.edu{ 10317518Sgblack@eecs.umich.edu uint64_t data = pkt->get<uint64_t>(); 10323823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10333823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10343823Ssaidi@eecs.umich.edu 10353826Ssaidi@eecs.umich.edu Addr ta_insert; 10363826Ssaidi@eecs.umich.edu Addr va_insert; 10373826Ssaidi@eecs.umich.edu Addr ct_insert; 10383826Ssaidi@eecs.umich.edu int part_insert; 10393826Ssaidi@eecs.umich.edu int entry_insert = -1; 10403826Ssaidi@eecs.umich.edu bool real_insert; 10413863Ssaidi@eecs.umich.edu bool ignore; 10423863Ssaidi@eecs.umich.edu int part_id; 10433863Ssaidi@eecs.umich.edu int ctx_id; 10443826Ssaidi@eecs.umich.edu PageTableEntry pte; 10453826Ssaidi@eecs.umich.edu 10463825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10473823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10483823Ssaidi@eecs.umich.edu 10496022Sgblack@eecs.umich.edu TLB *itb = tc->getITBPtr(); 10504990Sgblack@eecs.umich.edu 10513823Ssaidi@eecs.umich.edu switch (asi) { 10523823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10533823Ssaidi@eecs.umich.edu assert(va == 0); 10544172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10553823Ssaidi@eecs.umich.edu break; 10563823Ssaidi@eecs.umich.edu case ASI_MMU: 10573823Ssaidi@eecs.umich.edu switch (va) { 10583823Ssaidi@eecs.umich.edu case 0x8: 10594172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu case 0x10: 10624172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10633823Ssaidi@eecs.umich.edu break; 10643823Ssaidi@eecs.umich.edu default: 10653823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10663823Ssaidi@eecs.umich.edu } 10673823Ssaidi@eecs.umich.edu break; 10683824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10693825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10704172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10713824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10723824Ssaidi@eecs.umich.edu break; 10733823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10743823Ssaidi@eecs.umich.edu assert(va == 0); 10754990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10763823Ssaidi@eecs.umich.edu break; 10773823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10783823Ssaidi@eecs.umich.edu assert(va == 0); 10794990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10803823Ssaidi@eecs.umich.edu break; 10813823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10823823Ssaidi@eecs.umich.edu assert(va == 0); 10834990Sgblack@eecs.umich.edu c0_config = data; 10843823Ssaidi@eecs.umich.edu break; 10853823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10863823Ssaidi@eecs.umich.edu assert(va == 0); 10874990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 10883823Ssaidi@eecs.umich.edu break; 10893823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10903823Ssaidi@eecs.umich.edu assert(va == 0); 10914990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 10923823Ssaidi@eecs.umich.edu break; 10933823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10943823Ssaidi@eecs.umich.edu assert(va == 0); 10954990Sgblack@eecs.umich.edu itb->c0_config = data; 10963823Ssaidi@eecs.umich.edu break; 10973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10983823Ssaidi@eecs.umich.edu assert(va == 0); 10994990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11003823Ssaidi@eecs.umich.edu break; 11013823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11023823Ssaidi@eecs.umich.edu assert(va == 0); 11034990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11043823Ssaidi@eecs.umich.edu break; 11053823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11063823Ssaidi@eecs.umich.edu assert(va == 0); 11074990Sgblack@eecs.umich.edu cx_config = data; 11083823Ssaidi@eecs.umich.edu break; 11093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11103823Ssaidi@eecs.umich.edu assert(va == 0); 11114990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11123823Ssaidi@eecs.umich.edu break; 11133823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11143823Ssaidi@eecs.umich.edu assert(va == 0); 11154990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11163823Ssaidi@eecs.umich.edu break; 11173823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11183823Ssaidi@eecs.umich.edu assert(va == 0); 11194990Sgblack@eecs.umich.edu itb->cx_config = data; 11203823Ssaidi@eecs.umich.edu break; 11213825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11223825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11235823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11243825Ssaidi@eecs.umich.edu break; 11253823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11263823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11274172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11283823Ssaidi@eecs.umich.edu break; 11293826Ssaidi@eecs.umich.edu case ASI_IMMU: 11303826Ssaidi@eecs.umich.edu switch (va) { 11313906Ssaidi@eecs.umich.edu case 0x18: 11324990Sgblack@eecs.umich.edu itb->sfsr = data; 11333906Ssaidi@eecs.umich.edu break; 11343826Ssaidi@eecs.umich.edu case 0x30: 11353916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11364990Sgblack@eecs.umich.edu itb->tag_access = data; 11373826Ssaidi@eecs.umich.edu break; 11383826Ssaidi@eecs.umich.edu default: 11393826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11403826Ssaidi@eecs.umich.edu } 11413826Ssaidi@eecs.umich.edu break; 11423826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11433826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11443826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11453826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11464990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11473826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11483826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11494172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11503826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11513826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11523826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11533826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11543826Ssaidi@eecs.umich.edu pte, entry_insert); 11553826Ssaidi@eecs.umich.edu break; 11563826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11573826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11583826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11593826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11604990Sgblack@eecs.umich.edu ta_insert = tag_access; 11613826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11623826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11634172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11643826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11653826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11663826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11675555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11685555Snate@binkert.org entry_insert); 11693826Ssaidi@eecs.umich.edu break; 11703863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11713863Ssaidi@eecs.umich.edu ignore = false; 11723863Ssaidi@eecs.umich.edu ctx_id = -1; 11734172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11743863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11753863Ssaidi@eecs.umich.edu case 0: 11764172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11773863Ssaidi@eecs.umich.edu break; 11783863Ssaidi@eecs.umich.edu case 1: 11793863Ssaidi@eecs.umich.edu ignore = true; 11803863Ssaidi@eecs.umich.edu break; 11813863Ssaidi@eecs.umich.edu case 3: 11823863Ssaidi@eecs.umich.edu ctx_id = 0; 11833863Ssaidi@eecs.umich.edu break; 11843863Ssaidi@eecs.umich.edu default: 11853863Ssaidi@eecs.umich.edu ignore = true; 11863863Ssaidi@eecs.umich.edu } 11873863Ssaidi@eecs.umich.edu 11887741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 11893863Ssaidi@eecs.umich.edu case 0: // demap page 11903863Ssaidi@eecs.umich.edu if (!ignore) 11913863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11923863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11933863Ssaidi@eecs.umich.edu break; 11947741Sgblack@eecs.umich.edu case 1: // demap context 11953863Ssaidi@eecs.umich.edu if (!ignore) 11963863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11973863Ssaidi@eecs.umich.edu break; 11983863Ssaidi@eecs.umich.edu case 2: 11993863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12003863Ssaidi@eecs.umich.edu break; 12013863Ssaidi@eecs.umich.edu default: 12023863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12033863Ssaidi@eecs.umich.edu } 12043863Ssaidi@eecs.umich.edu break; 12053823Ssaidi@eecs.umich.edu case ASI_DMMU: 12063823Ssaidi@eecs.umich.edu switch (va) { 12073906Ssaidi@eecs.umich.edu case 0x18: 12084990Sgblack@eecs.umich.edu sfsr = data; 12093906Ssaidi@eecs.umich.edu break; 12103826Ssaidi@eecs.umich.edu case 0x30: 12113916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12124990Sgblack@eecs.umich.edu tag_access = data; 12133826Ssaidi@eecs.umich.edu break; 12143823Ssaidi@eecs.umich.edu case 0x80: 12154172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12163823Ssaidi@eecs.umich.edu break; 12173823Ssaidi@eecs.umich.edu default: 12183823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12193823Ssaidi@eecs.umich.edu } 12203823Ssaidi@eecs.umich.edu break; 12213863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12223863Ssaidi@eecs.umich.edu ignore = false; 12233863Ssaidi@eecs.umich.edu ctx_id = -1; 12244172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12253863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12263863Ssaidi@eecs.umich.edu case 0: 12274172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12283863Ssaidi@eecs.umich.edu break; 12293863Ssaidi@eecs.umich.edu case 1: 12304172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12313863Ssaidi@eecs.umich.edu break; 12323863Ssaidi@eecs.umich.edu case 3: 12333863Ssaidi@eecs.umich.edu ctx_id = 0; 12343863Ssaidi@eecs.umich.edu break; 12353863Ssaidi@eecs.umich.edu default: 12363863Ssaidi@eecs.umich.edu ignore = true; 12373863Ssaidi@eecs.umich.edu } 12383863Ssaidi@eecs.umich.edu 12397741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12403863Ssaidi@eecs.umich.edu case 0: // demap page 12413863Ssaidi@eecs.umich.edu if (!ignore) 12423863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12433863Ssaidi@eecs.umich.edu break; 12447741Sgblack@eecs.umich.edu case 1: // demap context 12453863Ssaidi@eecs.umich.edu if (!ignore) 12463863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12473863Ssaidi@eecs.umich.edu break; 12483863Ssaidi@eecs.umich.edu case 2: 12493863Ssaidi@eecs.umich.edu demapAll(part_id); 12503863Ssaidi@eecs.umich.edu break; 12513863Ssaidi@eecs.umich.edu default: 12523863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12533863Ssaidi@eecs.umich.edu } 12543863Ssaidi@eecs.umich.edu break; 12554103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12565646Sgblack@eecs.umich.edu { 12575646Sgblack@eecs.umich.edu int msb; 12585646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12595646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12605646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 12615646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 12625704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12635646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 12645704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 12655646Sgblack@eecs.umich.edu } 12664103Ssaidi@eecs.umich.edu } 12674103Ssaidi@eecs.umich.edu break; 12684103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12694103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12705704Snate@binkert.org postInterrupt(bits(data, 5, 0), 0); 12714103Ssaidi@eecs.umich.edu break; 12725555Snate@binkert.org default: 12733823Ssaidi@eecs.umich.edudoMmuWriteError: 12743823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12753823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12763823Ssaidi@eecs.umich.edu } 12774870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12785100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 12793806Ssaidi@eecs.umich.edu} 12803806Ssaidi@eecs.umich.edu 12814997Sgblack@eecs.umich.edu#endif 12824997Sgblack@eecs.umich.edu 12833804Ssaidi@eecs.umich.eduvoid 12846022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12854070Ssaidi@eecs.umich.edu{ 12864070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12876022Sgblack@eecs.umich.edu TLB * itb = tc->getITBPtr(); 12884070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12894990Sgblack@eecs.umich.edu c0_tsb_ps0, 12904990Sgblack@eecs.umich.edu c0_config, 12914990Sgblack@eecs.umich.edu cx_tsb_ps0, 12924990Sgblack@eecs.umich.edu cx_config); 12934070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12944990Sgblack@eecs.umich.edu c0_tsb_ps1, 12954990Sgblack@eecs.umich.edu c0_config, 12964990Sgblack@eecs.umich.edu cx_tsb_ps1, 12974990Sgblack@eecs.umich.edu cx_config); 12984070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 12994990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13004990Sgblack@eecs.umich.edu itb->c0_config, 13014990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13024990Sgblack@eecs.umich.edu itb->cx_config); 13034070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13044990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13054990Sgblack@eecs.umich.edu itb->c0_config, 13064990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13074990Sgblack@eecs.umich.edu itb->cx_config); 13084070Ssaidi@eecs.umich.edu} 13094070Ssaidi@eecs.umich.edu 13104070Ssaidi@eecs.umich.eduuint64_t 13116022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13124070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13134070Ssaidi@eecs.umich.edu{ 13144070Ssaidi@eecs.umich.edu uint64_t tsb; 13154070Ssaidi@eecs.umich.edu uint64_t config; 13164070Ssaidi@eecs.umich.edu 13174070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13184070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13194070Ssaidi@eecs.umich.edu config = c0_config; 13204070Ssaidi@eecs.umich.edu } else { 13214070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13224070Ssaidi@eecs.umich.edu config = cX_config; 13234070Ssaidi@eecs.umich.edu } 13244070Ssaidi@eecs.umich.edu 13254070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13264070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13274070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13284070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13294070Ssaidi@eecs.umich.edu 13304070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13314070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13324070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13334070Ssaidi@eecs.umich.edu 13344070Ssaidi@eecs.umich.edu return ptr; 13354070Ssaidi@eecs.umich.edu} 13364070Ssaidi@eecs.umich.edu 13374070Ssaidi@eecs.umich.eduvoid 13383804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13393804Ssaidi@eecs.umich.edu{ 13404000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13414000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13424000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13434000Ssaidi@eecs.umich.edu 13444000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13454000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13464000Ssaidi@eecs.umich.edu int cntr = 0; 13474000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13484000Ssaidi@eecs.umich.edu i = freeList.begin(); 13494000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13504000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13514000Ssaidi@eecs.umich.edu i++; 13524000Ssaidi@eecs.umich.edu } 13534000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13544000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13554000Ssaidi@eecs.umich.edu 13564990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13574990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13584990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13594990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13604990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13614990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13624990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13634990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13645276Ssaidi@eecs.umich.edu 13655276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13665276Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13675276Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13685276Ssaidi@eecs.umich.edu } 13696022Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 13703804Ssaidi@eecs.umich.edu} 13713804Ssaidi@eecs.umich.edu 13723804Ssaidi@eecs.umich.eduvoid 13733804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13743804Ssaidi@eecs.umich.edu{ 13754000Ssaidi@eecs.umich.edu int oldSize; 13764000Ssaidi@eecs.umich.edu 13774000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13784000Ssaidi@eecs.umich.edu if (oldSize != size) 13794000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13804000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13814000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13824000Ssaidi@eecs.umich.edu 13834000Ssaidi@eecs.umich.edu int cntr; 13844000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13854000Ssaidi@eecs.umich.edu 13864000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13874000Ssaidi@eecs.umich.edu freeList.clear(); 13884000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13894000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13904000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13914000Ssaidi@eecs.umich.edu 13924990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 13934990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 13944990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 13954990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 13964990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 13974990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 13984990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 13994990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14005276Ssaidi@eecs.umich.edu 14015276Ssaidi@eecs.umich.edu lookupTable.clear(); 14025276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14035276Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14045276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14055276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14065276Ssaidi@eecs.umich.edu 14075276Ssaidi@eecs.umich.edu } 14084990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14093804Ssaidi@eecs.umich.edu} 14103804Ssaidi@eecs.umich.edu 14117811Ssteve.reinhardt@amd.com} // namespace SparcISA 14124088Sbinkertn@umich.edu 14136022Sgblack@eecs.umich.eduSparcISA::TLB * 14146022Sgblack@eecs.umich.eduSparcTLBParams::create() 14153804Ssaidi@eecs.umich.edu{ 14166022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14173804Ssaidi@eecs.umich.edu} 1418