tlb.cc revision 5894
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 424103Ssaidi@eecs.umich.edu#include "sim/system.hh" 433569Sgblack@eecs.umich.edu 443804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 453804Ssaidi@eecs.umich.edu * */ 464088Sbinkertn@umich.edunamespace SparcISA { 473569Sgblack@eecs.umich.edu 485034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 495358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 503881Ssaidi@eecs.umich.edu cacheValid(false) 513804Ssaidi@eecs.umich.edu{ 523804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 533804Ssaidi@eecs.umich.edu if (size > 64) 545555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 553569Sgblack@eecs.umich.edu 563804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 573918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 603881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 614990Sgblack@eecs.umich.edu 624990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 634990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 644990Sgblack@eecs.umich.edu c0_config = 0; 654990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 664990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 674990Sgblack@eecs.umich.edu cx_config = 0; 684990Sgblack@eecs.umich.edu sfsr = 0; 694990Sgblack@eecs.umich.edu tag_access = 0; 703804Ssaidi@eecs.umich.edu} 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 743804Ssaidi@eecs.umich.edu{ 753804Ssaidi@eecs.umich.edu MapIter i; 763881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 773804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 783804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 793804Ssaidi@eecs.umich.edu t->used = false; 803804Ssaidi@eecs.umich.edu usedEntries--; 813804Ssaidi@eecs.umich.edu } 823804Ssaidi@eecs.umich.edu } 833804Ssaidi@eecs.umich.edu} 843569Sgblack@eecs.umich.edu 853569Sgblack@eecs.umich.edu 863804Ssaidi@eecs.umich.eduvoid 873804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 883826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 893804Ssaidi@eecs.umich.edu{ 903804Ssaidi@eecs.umich.edu MapIter i; 913826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 923907Ssaidi@eecs.umich.edu// TlbRange tr; 933826Ssaidi@eecs.umich.edu int x; 943811Ssaidi@eecs.umich.edu 953836Ssaidi@eecs.umich.edu cacheValid = false; 963915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 973907Ssaidi@eecs.umich.edu /* tr.va = va; 983881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 993881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1003881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1013881Ssaidi@eecs.umich.edu tr.real = real; 1023907Ssaidi@eecs.umich.edu*/ 1033881Ssaidi@eecs.umich.edu 1045555Snate@binkert.org DPRINTF(TLB, 1055555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1065555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1073881Ssaidi@eecs.umich.edu 1083881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1093907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1103907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1113907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1123907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1133907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1143907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1153907Ssaidi@eecs.umich.edu { 1163907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1173907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1183907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1193907Ssaidi@eecs.umich.edu 1203907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1213907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1223907Ssaidi@eecs.umich.edu tlb[x].used = false; 1233907Ssaidi@eecs.umich.edu usedEntries--; 1243907Ssaidi@eecs.umich.edu } 1253907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1263907Ssaidi@eecs.umich.edu } 1273907Ssaidi@eecs.umich.edu } 1283907Ssaidi@eecs.umich.edu } 1293907Ssaidi@eecs.umich.edu 1303907Ssaidi@eecs.umich.edu/* 1313881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1323881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1333881Ssaidi@eecs.umich.edu i->second->valid = false; 1343881Ssaidi@eecs.umich.edu if (i->second->used) { 1353881Ssaidi@eecs.umich.edu i->second->used = false; 1363881Ssaidi@eecs.umich.edu usedEntries--; 1373881Ssaidi@eecs.umich.edu } 1383881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1393881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1403881Ssaidi@eecs.umich.edu i->second); 1413881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1423881Ssaidi@eecs.umich.edu } 1433907Ssaidi@eecs.umich.edu*/ 1443811Ssaidi@eecs.umich.edu 1453826Ssaidi@eecs.umich.edu if (entry != -1) { 1463826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1473826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1483826Ssaidi@eecs.umich.edu } else { 1493881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1503881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1513881Ssaidi@eecs.umich.edu } else { 1523881Ssaidi@eecs.umich.edu x = lastReplaced; 1533881Ssaidi@eecs.umich.edu do { 1543881Ssaidi@eecs.umich.edu ++x; 1553881Ssaidi@eecs.umich.edu if (x == size) 1563881Ssaidi@eecs.umich.edu x = 0; 1573881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1583881Ssaidi@eecs.umich.edu goto insertAllLocked; 1593881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1603881Ssaidi@eecs.umich.edu lastReplaced = x; 1613881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1623881Ssaidi@eecs.umich.edu } 1633881Ssaidi@eecs.umich.edu /* 1643826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1653826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1663826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1673826Ssaidi@eecs.umich.edu break; 1683826Ssaidi@eecs.umich.edu } 1693881Ssaidi@eecs.umich.edu }*/ 1703569Sgblack@eecs.umich.edu } 1713569Sgblack@eecs.umich.edu 1723881Ssaidi@eecs.umich.eduinsertAllLocked: 1733804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1743881Ssaidi@eecs.umich.edu if (!new_entry) { 1753826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1763881Ssaidi@eecs.umich.edu } 1773881Ssaidi@eecs.umich.edu 1783881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1793907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1803907Ssaidi@eecs.umich.edu usedEntries--; 1813929Ssaidi@eecs.umich.edu if (new_entry->valid) 1823929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1833907Ssaidi@eecs.umich.edu 1843907Ssaidi@eecs.umich.edu 1853804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1863804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1873881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1883804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1893804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1903804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1913804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1923804Ssaidi@eecs.umich.edu new_entry->used = true;; 1933804Ssaidi@eecs.umich.edu new_entry->valid = true; 1943804Ssaidi@eecs.umich.edu usedEntries++; 1953569Sgblack@eecs.umich.edu 1963863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1973863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1983804Ssaidi@eecs.umich.edu 1995555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 2005555Snate@binkert.org // but the one we just inserted 2013804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2023804Ssaidi@eecs.umich.edu clearUsedBits(); 2033804Ssaidi@eecs.umich.edu new_entry->used = true; 2043804Ssaidi@eecs.umich.edu usedEntries++; 2053804Ssaidi@eecs.umich.edu } 2063569Sgblack@eecs.umich.edu} 2073804Ssaidi@eecs.umich.edu 2083804Ssaidi@eecs.umich.edu 2093804Ssaidi@eecs.umich.eduTlbEntry* 2105555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 2115555Snate@binkert.org bool update_used) 2123804Ssaidi@eecs.umich.edu{ 2133804Ssaidi@eecs.umich.edu MapIter i; 2143804Ssaidi@eecs.umich.edu TlbRange tr; 2153804Ssaidi@eecs.umich.edu TlbEntry *t; 2163804Ssaidi@eecs.umich.edu 2173811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2183811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2193804Ssaidi@eecs.umich.edu // Assemble full address structure 2203804Ssaidi@eecs.umich.edu tr.va = va; 2215312Sgblack@eecs.umich.edu tr.size = 1; 2223804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2233804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2243804Ssaidi@eecs.umich.edu tr.real = real; 2253804Ssaidi@eecs.umich.edu 2263804Ssaidi@eecs.umich.edu // Try to find the entry 2273804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2283804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2293811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2303804Ssaidi@eecs.umich.edu return NULL; 2313804Ssaidi@eecs.umich.edu } 2323804Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2343804Ssaidi@eecs.umich.edu t = i->second; 2353826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2363826Ssaidi@eecs.umich.edu t->pte.size()); 2374070Ssaidi@eecs.umich.edu 2385555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2395555Snate@binkert.org // one from virttophys() 2404070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2413804Ssaidi@eecs.umich.edu t->used = true; 2423804Ssaidi@eecs.umich.edu usedEntries++; 2433804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2443804Ssaidi@eecs.umich.edu clearUsedBits(); 2453804Ssaidi@eecs.umich.edu t->used = true; 2463804Ssaidi@eecs.umich.edu usedEntries++; 2473804Ssaidi@eecs.umich.edu } 2483804Ssaidi@eecs.umich.edu } 2493804Ssaidi@eecs.umich.edu 2503804Ssaidi@eecs.umich.edu return t; 2513804Ssaidi@eecs.umich.edu} 2523804Ssaidi@eecs.umich.edu 2533826Ssaidi@eecs.umich.eduvoid 2543826Ssaidi@eecs.umich.eduTLB::dumpAll() 2553826Ssaidi@eecs.umich.edu{ 2563863Ssaidi@eecs.umich.edu MapIter i; 2573826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2583826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2593826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2603826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2613826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2623826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2633826Ssaidi@eecs.umich.edu } 2643826Ssaidi@eecs.umich.edu } 2653826Ssaidi@eecs.umich.edu} 2663804Ssaidi@eecs.umich.edu 2673804Ssaidi@eecs.umich.eduvoid 2683804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2693804Ssaidi@eecs.umich.edu{ 2703804Ssaidi@eecs.umich.edu TlbRange tr; 2713804Ssaidi@eecs.umich.edu MapIter i; 2723804Ssaidi@eecs.umich.edu 2733863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2743863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2753863Ssaidi@eecs.umich.edu 2763836Ssaidi@eecs.umich.edu cacheValid = false; 2773836Ssaidi@eecs.umich.edu 2783804Ssaidi@eecs.umich.edu // Assemble full address structure 2793804Ssaidi@eecs.umich.edu tr.va = va; 2805312Sgblack@eecs.umich.edu tr.size = 1; 2813804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2823804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2833804Ssaidi@eecs.umich.edu tr.real = real; 2843804Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2863804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2873804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2883863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2893804Ssaidi@eecs.umich.edu i->second->valid = false; 2903804Ssaidi@eecs.umich.edu if (i->second->used) { 2913804Ssaidi@eecs.umich.edu i->second->used = false; 2923804Ssaidi@eecs.umich.edu usedEntries--; 2933804Ssaidi@eecs.umich.edu } 2943881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2953804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2963804Ssaidi@eecs.umich.edu } 2973804Ssaidi@eecs.umich.edu} 2983804Ssaidi@eecs.umich.edu 2993804Ssaidi@eecs.umich.eduvoid 3003804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 3013804Ssaidi@eecs.umich.edu{ 3023863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3033863Ssaidi@eecs.umich.edu partition_id, context_id); 3043836Ssaidi@eecs.umich.edu cacheValid = false; 3055555Snate@binkert.org for (int x = 0; x < size; x++) { 3063804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3073804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3083881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3093881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3103881Ssaidi@eecs.umich.edu } 3113804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3123804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3133804Ssaidi@eecs.umich.edu tlb[x].used = false; 3143804Ssaidi@eecs.umich.edu usedEntries--; 3153804Ssaidi@eecs.umich.edu } 3163804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3173804Ssaidi@eecs.umich.edu } 3183804Ssaidi@eecs.umich.edu } 3193804Ssaidi@eecs.umich.edu} 3203804Ssaidi@eecs.umich.edu 3213804Ssaidi@eecs.umich.eduvoid 3223804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3233804Ssaidi@eecs.umich.edu{ 3243863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3253836Ssaidi@eecs.umich.edu cacheValid = false; 3265555Snate@binkert.org for (int x = 0; x < size; x++) { 3275288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3285288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3295288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3303804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3313804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3323804Ssaidi@eecs.umich.edu tlb[x].used = false; 3333804Ssaidi@eecs.umich.edu usedEntries--; 3343804Ssaidi@eecs.umich.edu } 3353804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3363804Ssaidi@eecs.umich.edu } 3373804Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu} 3393804Ssaidi@eecs.umich.edu 3403804Ssaidi@eecs.umich.eduvoid 3413804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3423804Ssaidi@eecs.umich.edu{ 3433836Ssaidi@eecs.umich.edu cacheValid = false; 3445555Snate@binkert.org lookupTable.clear(); 3453836Ssaidi@eecs.umich.edu 3465555Snate@binkert.org for (int x = 0; x < size; x++) { 3473881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3483881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3493804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3503907Ssaidi@eecs.umich.edu tlb[x].used = false; 3513804Ssaidi@eecs.umich.edu } 3523804Ssaidi@eecs.umich.edu usedEntries = 0; 3533804Ssaidi@eecs.umich.edu} 3543804Ssaidi@eecs.umich.edu 3553804Ssaidi@eecs.umich.eduuint64_t 3565555Snate@binkert.orgTLB::TteRead(int entry) 3575555Snate@binkert.org{ 3583881Ssaidi@eecs.umich.edu if (entry >= size) 3593881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3603881Ssaidi@eecs.umich.edu 3613804Ssaidi@eecs.umich.edu assert(entry < size); 3623881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3633881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3643881Ssaidi@eecs.umich.edu else 3653881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3663804Ssaidi@eecs.umich.edu} 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.eduuint64_t 3695555Snate@binkert.orgTLB::TagRead(int entry) 3705555Snate@binkert.org{ 3713804Ssaidi@eecs.umich.edu assert(entry < size); 3723804Ssaidi@eecs.umich.edu uint64_t tag; 3733881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3743881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3753804Ssaidi@eecs.umich.edu 3763881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3773881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3783881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3793804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3803804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3813804Ssaidi@eecs.umich.edu return tag; 3823804Ssaidi@eecs.umich.edu} 3833804Ssaidi@eecs.umich.edu 3843804Ssaidi@eecs.umich.edubool 3853804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3863804Ssaidi@eecs.umich.edu{ 3873804Ssaidi@eecs.umich.edu if (am) 3883804Ssaidi@eecs.umich.edu return true; 3893804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3903804Ssaidi@eecs.umich.edu return false; 3913804Ssaidi@eecs.umich.edu return true; 3923804Ssaidi@eecs.umich.edu} 3933804Ssaidi@eecs.umich.edu 3943804Ssaidi@eecs.umich.eduvoid 3954990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3963804Ssaidi@eecs.umich.edu{ 3973804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3983804Ssaidi@eecs.umich.edu sfsr = 0x3; 3993804Ssaidi@eecs.umich.edu else 4003804Ssaidi@eecs.umich.edu sfsr = 1; 4013804Ssaidi@eecs.umich.edu 4023804Ssaidi@eecs.umich.edu if (write) 4033804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4043804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4053804Ssaidi@eecs.umich.edu if (se) 4063804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4073804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4083804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4093804Ssaidi@eecs.umich.edu} 4103804Ssaidi@eecs.umich.edu 4113826Ssaidi@eecs.umich.eduvoid 4124990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4133826Ssaidi@eecs.umich.edu{ 4143916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4153916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4163916Ssaidi@eecs.umich.edu 4174990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4183826Ssaidi@eecs.umich.edu} 4193804Ssaidi@eecs.umich.edu 4203804Ssaidi@eecs.umich.eduvoid 4214990Sgblack@eecs.umich.eduITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 4223804Ssaidi@eecs.umich.edu{ 4233811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4243811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4254990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4263804Ssaidi@eecs.umich.edu} 4273804Ssaidi@eecs.umich.edu 4283804Ssaidi@eecs.umich.eduvoid 4294990Sgblack@eecs.umich.eduDTB::writeSfsr(Addr a, bool write, ContextType ct, 4303804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4313804Ssaidi@eecs.umich.edu{ 4323811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4333811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4344990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4354990Sgblack@eecs.umich.edu sfar = a; 4363804Ssaidi@eecs.umich.edu} 4373804Ssaidi@eecs.umich.edu 4383804Ssaidi@eecs.umich.eduFault 4395894Sgblack@eecs.umich.eduITB::translateAtomic(RequestPtr req, ThreadContext *tc) 4403804Ssaidi@eecs.umich.edu{ 4414172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4423833Ssaidi@eecs.umich.edu 4433836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4443836Ssaidi@eecs.umich.edu TlbEntry *e; 4453836Ssaidi@eecs.umich.edu 4463836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4473836Ssaidi@eecs.umich.edu 4483836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4493836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4503836Ssaidi@eecs.umich.edu 4513836Ssaidi@eecs.umich.edu // Be fast if we can! 4523836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4533836Ssaidi@eecs.umich.edu if (cacheEntry) { 4543836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4553836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4565555Snate@binkert.org req->setPaddr(cacheEntry->pte.translate(vaddr)); 4575555Snate@binkert.org return NoFault; 4583836Ssaidi@eecs.umich.edu } 4593836Ssaidi@eecs.umich.edu } else { 4603836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4613836Ssaidi@eecs.umich.edu return NoFault; 4623836Ssaidi@eecs.umich.edu } 4633836Ssaidi@eecs.umich.edu } 4643836Ssaidi@eecs.umich.edu 4653833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4663833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4673833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4683833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4693833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4703833Ssaidi@eecs.umich.edu 4713833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4723833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4733833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4743804Ssaidi@eecs.umich.edu int context; 4753804Ssaidi@eecs.umich.edu ContextType ct; 4763804Ssaidi@eecs.umich.edu int asi; 4773804Ssaidi@eecs.umich.edu bool real = false; 4783804Ssaidi@eecs.umich.edu 4793833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4803833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4813811Ssaidi@eecs.umich.edu 4823804Ssaidi@eecs.umich.edu if (tl > 0) { 4833804Ssaidi@eecs.umich.edu asi = ASI_N; 4843804Ssaidi@eecs.umich.edu ct = Nucleus; 4853804Ssaidi@eecs.umich.edu context = 0; 4863804Ssaidi@eecs.umich.edu } else { 4873804Ssaidi@eecs.umich.edu asi = ASI_P; 4883804Ssaidi@eecs.umich.edu ct = Primary; 4893833Ssaidi@eecs.umich.edu context = pri_context; 4903804Ssaidi@eecs.umich.edu } 4913804Ssaidi@eecs.umich.edu 4923833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4933836Ssaidi@eecs.umich.edu cacheValid = true; 4943836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4953836Ssaidi@eecs.umich.edu cacheEntry = NULL; 4963836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4973804Ssaidi@eecs.umich.edu return NoFault; 4983804Ssaidi@eecs.umich.edu } 4993804Ssaidi@eecs.umich.edu 5003836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5013836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5024990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 5033804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5043804Ssaidi@eecs.umich.edu } 5053804Ssaidi@eecs.umich.edu 5063804Ssaidi@eecs.umich.edu if (addr_mask) 5073804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5083804Ssaidi@eecs.umich.edu 5093804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5104990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 5113804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5123804Ssaidi@eecs.umich.edu } 5133804Ssaidi@eecs.umich.edu 5143833Ssaidi@eecs.umich.edu if (!lsu_im) { 5153836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5163804Ssaidi@eecs.umich.edu real = true; 5173804Ssaidi@eecs.umich.edu context = 0; 5183804Ssaidi@eecs.umich.edu } else { 5193804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5203804Ssaidi@eecs.umich.edu } 5213804Ssaidi@eecs.umich.edu 5223804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5234990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5243804Ssaidi@eecs.umich.edu if (real) 5253804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5263804Ssaidi@eecs.umich.edu else 5274997Sgblack@eecs.umich.edu#if FULL_SYSTEM 5283804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5294997Sgblack@eecs.umich.edu#else 5304997Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5314997Sgblack@eecs.umich.edu#endif 5323804Ssaidi@eecs.umich.edu } 5333804Ssaidi@eecs.umich.edu 5343804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5353804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5364990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5374990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5383804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5393804Ssaidi@eecs.umich.edu } 5403804Ssaidi@eecs.umich.edu 5413836Ssaidi@eecs.umich.edu // cache translation date for next translation 5423836Ssaidi@eecs.umich.edu cacheValid = true; 5433836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5443836Ssaidi@eecs.umich.edu cacheEntry = e; 5453836Ssaidi@eecs.umich.edu 5465555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5473836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5483804Ssaidi@eecs.umich.edu return NoFault; 5493804Ssaidi@eecs.umich.edu} 5503804Ssaidi@eecs.umich.edu 5515894Sgblack@eecs.umich.eduvoid 5525894Sgblack@eecs.umich.eduITB::translateTiming(RequestPtr req, ThreadContext *tc, 5535894Sgblack@eecs.umich.edu Translation *translation) 5545894Sgblack@eecs.umich.edu{ 5555894Sgblack@eecs.umich.edu assert(translation); 5565894Sgblack@eecs.umich.edu translation->finish(translateAtomic(req, tc), req, tc, false); 5575894Sgblack@eecs.umich.edu} 5585894Sgblack@eecs.umich.edu 5593804Ssaidi@eecs.umich.eduFault 5605894Sgblack@eecs.umich.eduDTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) 5613804Ssaidi@eecs.umich.edu{ 5625555Snate@binkert.org /* 5635555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5645555Snate@binkert.org * it faster! 5655555Snate@binkert.org */ 5664172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5673836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5683836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5693836Ssaidi@eecs.umich.edu ASI asi; 5703836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5713836Ssaidi@eecs.umich.edu bool implicit = false; 5723836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5735570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5743833Ssaidi@eecs.umich.edu 5753836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5763836Ssaidi@eecs.umich.edu vaddr, size, asi); 5773836Ssaidi@eecs.umich.edu 5783929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5793929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5803929Ssaidi@eecs.umich.edu freeList.size()); 5813836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5823836Ssaidi@eecs.umich.edu implicit = true; 5833836Ssaidi@eecs.umich.edu 5844996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5854996Sgblack@eecs.umich.edu // trap later 5864996Sgblack@eecs.umich.edu if (!unaligned) { 5874996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5884996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5894996Sgblack@eecs.umich.edu return NoFault; 5904996Sgblack@eecs.umich.edu } 5914996Sgblack@eecs.umich.edu 5924996Sgblack@eecs.umich.edu // Be fast if we can! 5934996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5944996Sgblack@eecs.umich.edu 5954996Sgblack@eecs.umich.edu 5964996Sgblack@eecs.umich.edu 5974996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5984996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5994996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6004996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 6014996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6024996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6035555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 6045555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6055736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 6065555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6075555Snate@binkert.org return NoFault; 6084996Sgblack@eecs.umich.edu } // if matched 6094996Sgblack@eecs.umich.edu } // if cache entry valid 6104996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 6114996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 6124996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6134996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 6144996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6154996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6165555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 6175555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6185736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 6195555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6205555Snate@binkert.org return NoFault; 6214996Sgblack@eecs.umich.edu } // if matched 6224996Sgblack@eecs.umich.edu } // if cache entry valid 6234996Sgblack@eecs.umich.edu } 6243836Ssaidi@eecs.umich.edu } 6253836Ssaidi@eecs.umich.edu 6263833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6273833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6283833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6293833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6303833Ssaidi@eecs.umich.edu 6313833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6323833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6333833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6343916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6353833Ssaidi@eecs.umich.edu 6363804Ssaidi@eecs.umich.edu bool real = false; 6373832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6383832Ssaidi@eecs.umich.edu int context = 0; 6393804Ssaidi@eecs.umich.edu 6403804Ssaidi@eecs.umich.edu TlbEntry *e; 6413804Ssaidi@eecs.umich.edu 6423833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6435555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6443804Ssaidi@eecs.umich.edu 6453804Ssaidi@eecs.umich.edu if (implicit) { 6463804Ssaidi@eecs.umich.edu if (tl > 0) { 6473804Ssaidi@eecs.umich.edu asi = ASI_N; 6483804Ssaidi@eecs.umich.edu ct = Nucleus; 6493804Ssaidi@eecs.umich.edu context = 0; 6503804Ssaidi@eecs.umich.edu } else { 6513804Ssaidi@eecs.umich.edu asi = ASI_P; 6523804Ssaidi@eecs.umich.edu ct = Primary; 6533833Ssaidi@eecs.umich.edu context = pri_context; 6543804Ssaidi@eecs.umich.edu } 6553910Ssaidi@eecs.umich.edu } else { 6563804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6573910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6583804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6594990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6603804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6613804Ssaidi@eecs.umich.edu } 6623910Ssaidi@eecs.umich.edu 6633910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6644990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6653804Ssaidi@eecs.umich.edu return new DataAccessException; 6663804Ssaidi@eecs.umich.edu } 6673804Ssaidi@eecs.umich.edu 6683910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6693910Ssaidi@eecs.umich.edu context = pri_context; 6703910Ssaidi@eecs.umich.edu ct = Primary; 6713910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6723910Ssaidi@eecs.umich.edu context = sec_context; 6733910Ssaidi@eecs.umich.edu ct = Secondary; 6743910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6753910Ssaidi@eecs.umich.edu ct = Nucleus; 6763910Ssaidi@eecs.umich.edu context = 0; 6773910Ssaidi@eecs.umich.edu } else { // ???? 6783910Ssaidi@eecs.umich.edu ct = Primary; 6793910Ssaidi@eecs.umich.edu context = pri_context; 6803910Ssaidi@eecs.umich.edu } 6813902Ssaidi@eecs.umich.edu } 6823804Ssaidi@eecs.umich.edu 6833926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6843804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6853804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6864989Sgblack@eecs.umich.edu 6874989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6884989Sgblack@eecs.umich.edu //load differs from a regular one, other than what happens concerning 6894989Sgblack@eecs.umich.edu //nfo and e bits in the TTE 6904989Sgblack@eecs.umich.edu// if (AsiIsNoFault(asi)) 6914989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6923856Ssaidi@eecs.umich.edu 6933804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6943804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6954103Ssaidi@eecs.umich.edu 6964191Ssaidi@eecs.umich.edu if (AsiIsCmt(asi)) 6974191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6984191Ssaidi@eecs.umich.edu 6993824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 7004103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 7013804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 7023804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 7033804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 7043804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 7053824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 7063824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 7073825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 7083825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 7093823Ssaidi@eecs.umich.edu 7103926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 7114989Sgblack@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 7123823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7133804Ssaidi@eecs.umich.edu } 7143804Ssaidi@eecs.umich.edu 7153826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7164996Sgblack@eecs.umich.edu if (unaligned) { 7174990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 7183826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7193826Ssaidi@eecs.umich.edu } 7203826Ssaidi@eecs.umich.edu 7213826Ssaidi@eecs.umich.edu if (addr_mask) 7223826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7233826Ssaidi@eecs.umich.edu 7243826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7254990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 7263826Ssaidi@eecs.umich.edu return new DataAccessException; 7273826Ssaidi@eecs.umich.edu } 7283826Ssaidi@eecs.umich.edu 7293910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7303804Ssaidi@eecs.umich.edu real = true; 7313804Ssaidi@eecs.umich.edu context = 0; 7325555Snate@binkert.org } 7333804Ssaidi@eecs.umich.edu 7343804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7353836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7363804Ssaidi@eecs.umich.edu return NoFault; 7373804Ssaidi@eecs.umich.edu } 7383804Ssaidi@eecs.umich.edu 7393836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7403804Ssaidi@eecs.umich.edu 7413804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7424990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7433811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7443804Ssaidi@eecs.umich.edu if (real) 7453804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7463804Ssaidi@eecs.umich.edu else 7474997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7483804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7494997Sgblack@eecs.umich.edu#else 7504997Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7514997Sgblack@eecs.umich.edu#endif 7523804Ssaidi@eecs.umich.edu 7533804Ssaidi@eecs.umich.edu } 7543804Ssaidi@eecs.umich.edu 7553928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7564990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7574990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7583928Ssaidi@eecs.umich.edu return new DataAccessException; 7593928Ssaidi@eecs.umich.edu } 7603804Ssaidi@eecs.umich.edu 7613804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7624990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7634990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7643804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7653804Ssaidi@eecs.umich.edu } 7663804Ssaidi@eecs.umich.edu 7673804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7684990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7694990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7703804Ssaidi@eecs.umich.edu return new DataAccessException; 7713804Ssaidi@eecs.umich.edu } 7723804Ssaidi@eecs.umich.edu 7733928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7744990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7754990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7763928Ssaidi@eecs.umich.edu return new DataAccessException; 7773928Ssaidi@eecs.umich.edu } 7783928Ssaidi@eecs.umich.edu 7794090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7805736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 7813804Ssaidi@eecs.umich.edu 7823836Ssaidi@eecs.umich.edu // cache translation date for next translation 7833836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7843881Ssaidi@eecs.umich.edu if (!cacheValid) { 7853881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7863881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7873881Ssaidi@eecs.umich.edu } 7883881Ssaidi@eecs.umich.edu 7893836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7903836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7913836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7923836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7933836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7943836Ssaidi@eecs.umich.edu if (implicit) 7953836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7963836Ssaidi@eecs.umich.edu } 7973881Ssaidi@eecs.umich.edu cacheValid = true; 7985555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7993836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 8003804Ssaidi@eecs.umich.edu return NoFault; 8014103Ssaidi@eecs.umich.edu 8023806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 8034103Ssaidi@eecs.umich.eduhandleIntRegAccess: 8044103Ssaidi@eecs.umich.edu if (!hpriv) { 8054990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8064103Ssaidi@eecs.umich.edu if (priv) 8074103Ssaidi@eecs.umich.edu return new DataAccessException; 8084103Ssaidi@eecs.umich.edu else 8094103Ssaidi@eecs.umich.edu return new PrivilegedAction; 8104103Ssaidi@eecs.umich.edu } 8114103Ssaidi@eecs.umich.edu 8125570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 8135570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 8144990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8154103Ssaidi@eecs.umich.edu return new DataAccessException; 8164103Ssaidi@eecs.umich.edu } 8174103Ssaidi@eecs.umich.edu 8184103Ssaidi@eecs.umich.edu goto regAccessOk; 8194103Ssaidi@eecs.umich.edu 8203804Ssaidi@eecs.umich.edu 8213806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8223806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8234990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8243806Ssaidi@eecs.umich.edu return new DataAccessException; 8253806Ssaidi@eecs.umich.edu } 8263824Ssaidi@eecs.umich.edu goto regAccessOk; 8273824Ssaidi@eecs.umich.edu 8283824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8293824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8304990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8313824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8323824Ssaidi@eecs.umich.edu } 8335570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8344990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8353824Ssaidi@eecs.umich.edu return new DataAccessException; 8363824Ssaidi@eecs.umich.edu } 8373824Ssaidi@eecs.umich.edu goto regAccessOk; 8383824Ssaidi@eecs.umich.edu 8393825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8403825Ssaidi@eecs.umich.edu if (!hpriv) { 8414990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8424070Ssaidi@eecs.umich.edu if (priv) 8433825Ssaidi@eecs.umich.edu return new DataAccessException; 8444070Ssaidi@eecs.umich.edu else 8453825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8463825Ssaidi@eecs.umich.edu } 8473825Ssaidi@eecs.umich.edu goto regAccessOk; 8483825Ssaidi@eecs.umich.edu 8493825Ssaidi@eecs.umich.edu 8503824Ssaidi@eecs.umich.eduregAccessOk: 8513804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8523811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8533806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8543806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8553806Ssaidi@eecs.umich.edu return NoFault; 8563804Ssaidi@eecs.umich.edu}; 8573804Ssaidi@eecs.umich.edu 8585894Sgblack@eecs.umich.eduvoid 8595894Sgblack@eecs.umich.eduDTB::translateTiming(RequestPtr req, ThreadContext *tc, 8605894Sgblack@eecs.umich.edu Translation *translation, bool write) 8615894Sgblack@eecs.umich.edu{ 8625894Sgblack@eecs.umich.edu assert(translation); 8635894Sgblack@eecs.umich.edu translation->finish(translateAtomic(req, tc, write), req, tc, write); 8645894Sgblack@eecs.umich.edu} 8655894Sgblack@eecs.umich.edu 8664997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8674997Sgblack@eecs.umich.edu 8683806Ssaidi@eecs.umich.eduTick 8693806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8703806Ssaidi@eecs.umich.edu{ 8713823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8723823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8734070Ssaidi@eecs.umich.edu uint64_t temp; 8743823Ssaidi@eecs.umich.edu 8753823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8763823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8773823Ssaidi@eecs.umich.edu 8785555Snate@binkert.org ITB *itb = tc->getITBPtr(); 8794990Sgblack@eecs.umich.edu 8803823Ssaidi@eecs.umich.edu switch (asi) { 8813823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8823823Ssaidi@eecs.umich.edu assert(va == 0); 8834172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8843823Ssaidi@eecs.umich.edu break; 8853823Ssaidi@eecs.umich.edu case ASI_MMU: 8863823Ssaidi@eecs.umich.edu switch (va) { 8873823Ssaidi@eecs.umich.edu case 0x8: 8884172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8893823Ssaidi@eecs.umich.edu break; 8903823Ssaidi@eecs.umich.edu case 0x10: 8914172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8923823Ssaidi@eecs.umich.edu break; 8933823Ssaidi@eecs.umich.edu default: 8943823Ssaidi@eecs.umich.edu goto doMmuReadError; 8953823Ssaidi@eecs.umich.edu } 8963823Ssaidi@eecs.umich.edu break; 8973824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8984172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8993824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 9003824Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9034990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9074990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9114990Sgblack@eecs.umich.edu pkt->set(c0_config); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9154990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9194990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9234990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9274990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9314990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9323823Ssaidi@eecs.umich.edu break; 9333823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9343823Ssaidi@eecs.umich.edu assert(va == 0); 9354990Sgblack@eecs.umich.edu pkt->set(cx_config); 9363823Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9383823Ssaidi@eecs.umich.edu assert(va == 0); 9394990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9403823Ssaidi@eecs.umich.edu break; 9413823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9423823Ssaidi@eecs.umich.edu assert(va == 0); 9434990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9443823Ssaidi@eecs.umich.edu break; 9453823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9463823Ssaidi@eecs.umich.edu assert(va == 0); 9474990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9483823Ssaidi@eecs.umich.edu break; 9493826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9503912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9513826Ssaidi@eecs.umich.edu break; 9523823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9533823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9544172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9553823Ssaidi@eecs.umich.edu break; 9563826Ssaidi@eecs.umich.edu case ASI_IMMU: 9573826Ssaidi@eecs.umich.edu switch (va) { 9583833Ssaidi@eecs.umich.edu case 0x0: 9594990Sgblack@eecs.umich.edu temp = itb->tag_access; 9603833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9613833Ssaidi@eecs.umich.edu break; 9623906Ssaidi@eecs.umich.edu case 0x18: 9634990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9643906Ssaidi@eecs.umich.edu break; 9653826Ssaidi@eecs.umich.edu case 0x30: 9664990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9673826Ssaidi@eecs.umich.edu break; 9683826Ssaidi@eecs.umich.edu default: 9693826Ssaidi@eecs.umich.edu goto doMmuReadError; 9703826Ssaidi@eecs.umich.edu } 9713826Ssaidi@eecs.umich.edu break; 9723823Ssaidi@eecs.umich.edu case ASI_DMMU: 9733823Ssaidi@eecs.umich.edu switch (va) { 9743833Ssaidi@eecs.umich.edu case 0x0: 9754990Sgblack@eecs.umich.edu temp = tag_access; 9763833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9773833Ssaidi@eecs.umich.edu break; 9783906Ssaidi@eecs.umich.edu case 0x18: 9794990Sgblack@eecs.umich.edu pkt->set(sfsr); 9803906Ssaidi@eecs.umich.edu break; 9813906Ssaidi@eecs.umich.edu case 0x20: 9824990Sgblack@eecs.umich.edu pkt->set(sfar); 9833906Ssaidi@eecs.umich.edu break; 9843826Ssaidi@eecs.umich.edu case 0x30: 9854990Sgblack@eecs.umich.edu pkt->set(tag_access); 9863826Ssaidi@eecs.umich.edu break; 9873823Ssaidi@eecs.umich.edu case 0x80: 9884172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9893823Ssaidi@eecs.umich.edu break; 9903823Ssaidi@eecs.umich.edu default: 9913823Ssaidi@eecs.umich.edu goto doMmuReadError; 9923823Ssaidi@eecs.umich.edu } 9933823Ssaidi@eecs.umich.edu break; 9943833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9954070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9964990Sgblack@eecs.umich.edu tag_access, 9974990Sgblack@eecs.umich.edu c0_tsb_ps0, 9984990Sgblack@eecs.umich.edu c0_config, 9994990Sgblack@eecs.umich.edu cx_tsb_ps0, 10004990Sgblack@eecs.umich.edu cx_config)); 10013833Ssaidi@eecs.umich.edu break; 10023833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 10034070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10044990Sgblack@eecs.umich.edu tag_access, 10054990Sgblack@eecs.umich.edu c0_tsb_ps1, 10064990Sgblack@eecs.umich.edu c0_config, 10074990Sgblack@eecs.umich.edu cx_tsb_ps1, 10084990Sgblack@eecs.umich.edu cx_config)); 10093833Ssaidi@eecs.umich.edu break; 10103899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10114070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10124990Sgblack@eecs.umich.edu itb->tag_access, 10134990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10144990Sgblack@eecs.umich.edu itb->c0_config, 10154990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10164990Sgblack@eecs.umich.edu itb->cx_config)); 10173899Ssaidi@eecs.umich.edu break; 10183899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10194070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10204990Sgblack@eecs.umich.edu itb->tag_access, 10214990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10224990Sgblack@eecs.umich.edu itb->c0_config, 10234990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10244990Sgblack@eecs.umich.edu itb->cx_config)); 10253899Ssaidi@eecs.umich.edu break; 10264103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10275646Sgblack@eecs.umich.edu { 10285646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10295646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10305646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10315646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10325646Sgblack@eecs.umich.edu } 10334103Ssaidi@eecs.umich.edu break; 10344103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10355646Sgblack@eecs.umich.edu { 10365646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10375646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10385646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10395646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 10405704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 10415646Sgblack@eecs.umich.edu pkt->set(temp); 10425646Sgblack@eecs.umich.edu } 10434103Ssaidi@eecs.umich.edu break; 10443823Ssaidi@eecs.umich.edu default: 10453823Ssaidi@eecs.umich.edudoMmuReadError: 10463823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10473823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10483823Ssaidi@eecs.umich.edu } 10494870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10505100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 10513806Ssaidi@eecs.umich.edu} 10523806Ssaidi@eecs.umich.edu 10533806Ssaidi@eecs.umich.eduTick 10543806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10553806Ssaidi@eecs.umich.edu{ 10563823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10573823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10583823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10593823Ssaidi@eecs.umich.edu 10603826Ssaidi@eecs.umich.edu Addr ta_insert; 10613826Ssaidi@eecs.umich.edu Addr va_insert; 10623826Ssaidi@eecs.umich.edu Addr ct_insert; 10633826Ssaidi@eecs.umich.edu int part_insert; 10643826Ssaidi@eecs.umich.edu int entry_insert = -1; 10653826Ssaidi@eecs.umich.edu bool real_insert; 10663863Ssaidi@eecs.umich.edu bool ignore; 10673863Ssaidi@eecs.umich.edu int part_id; 10683863Ssaidi@eecs.umich.edu int ctx_id; 10693826Ssaidi@eecs.umich.edu PageTableEntry pte; 10703826Ssaidi@eecs.umich.edu 10713825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10723823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10733823Ssaidi@eecs.umich.edu 10745555Snate@binkert.org ITB *itb = tc->getITBPtr(); 10754990Sgblack@eecs.umich.edu 10763823Ssaidi@eecs.umich.edu switch (asi) { 10773823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10783823Ssaidi@eecs.umich.edu assert(va == 0); 10794172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10803823Ssaidi@eecs.umich.edu break; 10813823Ssaidi@eecs.umich.edu case ASI_MMU: 10823823Ssaidi@eecs.umich.edu switch (va) { 10833823Ssaidi@eecs.umich.edu case 0x8: 10844172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10853823Ssaidi@eecs.umich.edu break; 10863823Ssaidi@eecs.umich.edu case 0x10: 10874172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10883823Ssaidi@eecs.umich.edu break; 10893823Ssaidi@eecs.umich.edu default: 10903823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10913823Ssaidi@eecs.umich.edu } 10923823Ssaidi@eecs.umich.edu break; 10933824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10943825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10954172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10963824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10973824Ssaidi@eecs.umich.edu break; 10983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10993823Ssaidi@eecs.umich.edu assert(va == 0); 11004990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 11013823Ssaidi@eecs.umich.edu break; 11023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 11033823Ssaidi@eecs.umich.edu assert(va == 0); 11044990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 11053823Ssaidi@eecs.umich.edu break; 11063823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 11073823Ssaidi@eecs.umich.edu assert(va == 0); 11084990Sgblack@eecs.umich.edu c0_config = data; 11093823Ssaidi@eecs.umich.edu break; 11103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 11113823Ssaidi@eecs.umich.edu assert(va == 0); 11124990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 11133823Ssaidi@eecs.umich.edu break; 11143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11153823Ssaidi@eecs.umich.edu assert(va == 0); 11164990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11173823Ssaidi@eecs.umich.edu break; 11183823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11193823Ssaidi@eecs.umich.edu assert(va == 0); 11204990Sgblack@eecs.umich.edu itb->c0_config = data; 11213823Ssaidi@eecs.umich.edu break; 11223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11233823Ssaidi@eecs.umich.edu assert(va == 0); 11244990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11253823Ssaidi@eecs.umich.edu break; 11263823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11273823Ssaidi@eecs.umich.edu assert(va == 0); 11284990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11293823Ssaidi@eecs.umich.edu break; 11303823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11313823Ssaidi@eecs.umich.edu assert(va == 0); 11324990Sgblack@eecs.umich.edu cx_config = data; 11333823Ssaidi@eecs.umich.edu break; 11343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11353823Ssaidi@eecs.umich.edu assert(va == 0); 11364990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11373823Ssaidi@eecs.umich.edu break; 11383823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11393823Ssaidi@eecs.umich.edu assert(va == 0); 11404990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11413823Ssaidi@eecs.umich.edu break; 11423823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11433823Ssaidi@eecs.umich.edu assert(va == 0); 11444990Sgblack@eecs.umich.edu itb->cx_config = data; 11453823Ssaidi@eecs.umich.edu break; 11463825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11473825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11485823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11493825Ssaidi@eecs.umich.edu break; 11503823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11513823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11524172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11533823Ssaidi@eecs.umich.edu break; 11543826Ssaidi@eecs.umich.edu case ASI_IMMU: 11553826Ssaidi@eecs.umich.edu switch (va) { 11563906Ssaidi@eecs.umich.edu case 0x18: 11574990Sgblack@eecs.umich.edu itb->sfsr = data; 11583906Ssaidi@eecs.umich.edu break; 11593826Ssaidi@eecs.umich.edu case 0x30: 11603916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11614990Sgblack@eecs.umich.edu itb->tag_access = data; 11623826Ssaidi@eecs.umich.edu break; 11633826Ssaidi@eecs.umich.edu default: 11643826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11653826Ssaidi@eecs.umich.edu } 11663826Ssaidi@eecs.umich.edu break; 11673826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11683826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11693826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11703826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11714990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11723826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11733826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11744172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11753826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11763826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11773826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11783826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11793826Ssaidi@eecs.umich.edu pte, entry_insert); 11803826Ssaidi@eecs.umich.edu break; 11813826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11823826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11833826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11843826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11854990Sgblack@eecs.umich.edu ta_insert = tag_access; 11863826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11873826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11884172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11893826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11903826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11913826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11925555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11935555Snate@binkert.org entry_insert); 11943826Ssaidi@eecs.umich.edu break; 11953863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11963863Ssaidi@eecs.umich.edu ignore = false; 11973863Ssaidi@eecs.umich.edu ctx_id = -1; 11984172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11993863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12003863Ssaidi@eecs.umich.edu case 0: 12014172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12023863Ssaidi@eecs.umich.edu break; 12033863Ssaidi@eecs.umich.edu case 1: 12043863Ssaidi@eecs.umich.edu ignore = true; 12053863Ssaidi@eecs.umich.edu break; 12063863Ssaidi@eecs.umich.edu case 3: 12073863Ssaidi@eecs.umich.edu ctx_id = 0; 12083863Ssaidi@eecs.umich.edu break; 12093863Ssaidi@eecs.umich.edu default: 12103863Ssaidi@eecs.umich.edu ignore = true; 12113863Ssaidi@eecs.umich.edu } 12123863Ssaidi@eecs.umich.edu 12133863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12143863Ssaidi@eecs.umich.edu case 0: // demap page 12153863Ssaidi@eecs.umich.edu if (!ignore) 12163863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 12173863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 12183863Ssaidi@eecs.umich.edu break; 12193863Ssaidi@eecs.umich.edu case 1: //demap context 12203863Ssaidi@eecs.umich.edu if (!ignore) 12213863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 12223863Ssaidi@eecs.umich.edu break; 12233863Ssaidi@eecs.umich.edu case 2: 12243863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12253863Ssaidi@eecs.umich.edu break; 12263863Ssaidi@eecs.umich.edu default: 12273863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12283863Ssaidi@eecs.umich.edu } 12293863Ssaidi@eecs.umich.edu break; 12303823Ssaidi@eecs.umich.edu case ASI_DMMU: 12313823Ssaidi@eecs.umich.edu switch (va) { 12323906Ssaidi@eecs.umich.edu case 0x18: 12334990Sgblack@eecs.umich.edu sfsr = data; 12343906Ssaidi@eecs.umich.edu break; 12353826Ssaidi@eecs.umich.edu case 0x30: 12363916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12374990Sgblack@eecs.umich.edu tag_access = data; 12383826Ssaidi@eecs.umich.edu break; 12393823Ssaidi@eecs.umich.edu case 0x80: 12404172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12413823Ssaidi@eecs.umich.edu break; 12423823Ssaidi@eecs.umich.edu default: 12433823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12443823Ssaidi@eecs.umich.edu } 12453823Ssaidi@eecs.umich.edu break; 12463863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12473863Ssaidi@eecs.umich.edu ignore = false; 12483863Ssaidi@eecs.umich.edu ctx_id = -1; 12494172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12503863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12513863Ssaidi@eecs.umich.edu case 0: 12524172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12533863Ssaidi@eecs.umich.edu break; 12543863Ssaidi@eecs.umich.edu case 1: 12554172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12563863Ssaidi@eecs.umich.edu break; 12573863Ssaidi@eecs.umich.edu case 3: 12583863Ssaidi@eecs.umich.edu ctx_id = 0; 12593863Ssaidi@eecs.umich.edu break; 12603863Ssaidi@eecs.umich.edu default: 12613863Ssaidi@eecs.umich.edu ignore = true; 12623863Ssaidi@eecs.umich.edu } 12633863Ssaidi@eecs.umich.edu 12643863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12653863Ssaidi@eecs.umich.edu case 0: // demap page 12663863Ssaidi@eecs.umich.edu if (!ignore) 12673863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12683863Ssaidi@eecs.umich.edu break; 12693863Ssaidi@eecs.umich.edu case 1: //demap context 12703863Ssaidi@eecs.umich.edu if (!ignore) 12713863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12723863Ssaidi@eecs.umich.edu break; 12733863Ssaidi@eecs.umich.edu case 2: 12743863Ssaidi@eecs.umich.edu demapAll(part_id); 12753863Ssaidi@eecs.umich.edu break; 12763863Ssaidi@eecs.umich.edu default: 12773863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12783863Ssaidi@eecs.umich.edu } 12793863Ssaidi@eecs.umich.edu break; 12804103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12815646Sgblack@eecs.umich.edu { 12825646Sgblack@eecs.umich.edu int msb; 12835646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12845646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12855646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 12865646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 12875704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12885646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 12895704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 12905646Sgblack@eecs.umich.edu } 12914103Ssaidi@eecs.umich.edu } 12924103Ssaidi@eecs.umich.edu break; 12934103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12944103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12955704Snate@binkert.org postInterrupt(bits(data, 5, 0), 0); 12964103Ssaidi@eecs.umich.edu break; 12975555Snate@binkert.org default: 12983823Ssaidi@eecs.umich.edudoMmuWriteError: 12993823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 13003823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 13013823Ssaidi@eecs.umich.edu } 13024870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 13035100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 13043806Ssaidi@eecs.umich.edu} 13053806Ssaidi@eecs.umich.edu 13064997Sgblack@eecs.umich.edu#endif 13074997Sgblack@eecs.umich.edu 13083804Ssaidi@eecs.umich.eduvoid 13094070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 13104070Ssaidi@eecs.umich.edu{ 13114070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 13124990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 13134070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 13144990Sgblack@eecs.umich.edu c0_tsb_ps0, 13154990Sgblack@eecs.umich.edu c0_config, 13164990Sgblack@eecs.umich.edu cx_tsb_ps0, 13174990Sgblack@eecs.umich.edu cx_config); 13184070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13194990Sgblack@eecs.umich.edu c0_tsb_ps1, 13204990Sgblack@eecs.umich.edu c0_config, 13214990Sgblack@eecs.umich.edu cx_tsb_ps1, 13224990Sgblack@eecs.umich.edu cx_config); 13234070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13244990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13254990Sgblack@eecs.umich.edu itb->c0_config, 13264990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13274990Sgblack@eecs.umich.edu itb->cx_config); 13284070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13294990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13304990Sgblack@eecs.umich.edu itb->c0_config, 13314990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13324990Sgblack@eecs.umich.edu itb->cx_config); 13334070Ssaidi@eecs.umich.edu} 13344070Ssaidi@eecs.umich.edu 13354070Ssaidi@eecs.umich.eduuint64_t 13364070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13374070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13384070Ssaidi@eecs.umich.edu{ 13394070Ssaidi@eecs.umich.edu uint64_t tsb; 13404070Ssaidi@eecs.umich.edu uint64_t config; 13414070Ssaidi@eecs.umich.edu 13424070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13434070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13444070Ssaidi@eecs.umich.edu config = c0_config; 13454070Ssaidi@eecs.umich.edu } else { 13464070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13474070Ssaidi@eecs.umich.edu config = cX_config; 13484070Ssaidi@eecs.umich.edu } 13494070Ssaidi@eecs.umich.edu 13504070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13514070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13524070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13534070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13544070Ssaidi@eecs.umich.edu 13554070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13564070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13574070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13584070Ssaidi@eecs.umich.edu 13594070Ssaidi@eecs.umich.edu return ptr; 13604070Ssaidi@eecs.umich.edu} 13614070Ssaidi@eecs.umich.edu 13624070Ssaidi@eecs.umich.eduvoid 13633804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13643804Ssaidi@eecs.umich.edu{ 13654000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13664000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13674000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13684000Ssaidi@eecs.umich.edu 13694000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13704000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13714000Ssaidi@eecs.umich.edu int cntr = 0; 13724000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13734000Ssaidi@eecs.umich.edu i = freeList.begin(); 13744000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13754000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13764000Ssaidi@eecs.umich.edu i++; 13774000Ssaidi@eecs.umich.edu } 13784000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13794000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13804000Ssaidi@eecs.umich.edu 13814990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13824990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13834990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13844990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13854990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13864990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13874990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13884990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13895276Ssaidi@eecs.umich.edu 13905276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13915276Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13925276Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13935276Ssaidi@eecs.umich.edu } 13943804Ssaidi@eecs.umich.edu} 13953804Ssaidi@eecs.umich.edu 13963804Ssaidi@eecs.umich.eduvoid 13973804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13983804Ssaidi@eecs.umich.edu{ 13994000Ssaidi@eecs.umich.edu int oldSize; 14004000Ssaidi@eecs.umich.edu 14014000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 14024000Ssaidi@eecs.umich.edu if (oldSize != size) 14034000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 14044000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 14054000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 14064000Ssaidi@eecs.umich.edu 14074000Ssaidi@eecs.umich.edu int cntr; 14084000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 14094000Ssaidi@eecs.umich.edu 14104000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 14114000Ssaidi@eecs.umich.edu freeList.clear(); 14124000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 14134000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 14144000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 14154000Ssaidi@eecs.umich.edu 14164990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14174990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14184990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14194990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14204990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14214990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14224990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14234990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14245276Ssaidi@eecs.umich.edu 14255276Ssaidi@eecs.umich.edu lookupTable.clear(); 14265276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14275276Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14285276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14295276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14305276Ssaidi@eecs.umich.edu 14315276Ssaidi@eecs.umich.edu } 14324990Sgblack@eecs.umich.edu} 14334990Sgblack@eecs.umich.edu 14344990Sgblack@eecs.umich.eduvoid 14354990Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 14364990Sgblack@eecs.umich.edu{ 14374990Sgblack@eecs.umich.edu TLB::serialize(os); 14384990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 14394990Sgblack@eecs.umich.edu} 14404990Sgblack@eecs.umich.edu 14414990Sgblack@eecs.umich.eduvoid 14424990Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 14434990Sgblack@eecs.umich.edu{ 14444990Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 14454990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14463804Ssaidi@eecs.umich.edu} 14473804Ssaidi@eecs.umich.edu 14484088Sbinkertn@umich.edu/* end namespace SparcISA */ } 14494088Sbinkertn@umich.edu 14504762Snate@binkert.orgSparcISA::ITB * 14514762Snate@binkert.orgSparcITBParams::create() 14523804Ssaidi@eecs.umich.edu{ 14535034Smilesck@eecs.umich.edu return new SparcISA::ITB(this); 14543804Ssaidi@eecs.umich.edu} 14553804Ssaidi@eecs.umich.edu 14564762Snate@binkert.orgSparcISA::DTB * 14574762Snate@binkert.orgSparcDTBParams::create() 14583804Ssaidi@eecs.umich.edu{ 14595034Smilesck@eecs.umich.edu return new SparcISA::DTB(this); 14603804Ssaidi@eecs.umich.edu} 1461