tlb.cc revision 5704
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 424103Ssaidi@eecs.umich.edu#include "sim/system.hh" 433569Sgblack@eecs.umich.edu 443804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 453804Ssaidi@eecs.umich.edu * */ 464088Sbinkertn@umich.edunamespace SparcISA { 473569Sgblack@eecs.umich.edu 485034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 495358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 503881Ssaidi@eecs.umich.edu cacheValid(false) 513804Ssaidi@eecs.umich.edu{ 523804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 533804Ssaidi@eecs.umich.edu if (size > 64) 545555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 553569Sgblack@eecs.umich.edu 563804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 573918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 603881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 614990Sgblack@eecs.umich.edu 624990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 634990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 644990Sgblack@eecs.umich.edu c0_config = 0; 654990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 664990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 674990Sgblack@eecs.umich.edu cx_config = 0; 684990Sgblack@eecs.umich.edu sfsr = 0; 694990Sgblack@eecs.umich.edu tag_access = 0; 703804Ssaidi@eecs.umich.edu} 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 743804Ssaidi@eecs.umich.edu{ 753804Ssaidi@eecs.umich.edu MapIter i; 763881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 773804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 783804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 793804Ssaidi@eecs.umich.edu t->used = false; 803804Ssaidi@eecs.umich.edu usedEntries--; 813804Ssaidi@eecs.umich.edu } 823804Ssaidi@eecs.umich.edu } 833804Ssaidi@eecs.umich.edu} 843569Sgblack@eecs.umich.edu 853569Sgblack@eecs.umich.edu 863804Ssaidi@eecs.umich.eduvoid 873804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 883826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 893804Ssaidi@eecs.umich.edu{ 903804Ssaidi@eecs.umich.edu MapIter i; 913826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 923907Ssaidi@eecs.umich.edu// TlbRange tr; 933826Ssaidi@eecs.umich.edu int x; 943811Ssaidi@eecs.umich.edu 953836Ssaidi@eecs.umich.edu cacheValid = false; 963915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 973907Ssaidi@eecs.umich.edu /* tr.va = va; 983881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 993881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1003881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1013881Ssaidi@eecs.umich.edu tr.real = real; 1023907Ssaidi@eecs.umich.edu*/ 1033881Ssaidi@eecs.umich.edu 1045555Snate@binkert.org DPRINTF(TLB, 1055555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1065555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1073881Ssaidi@eecs.umich.edu 1083881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1093907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1103907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1113907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1123907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1133907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1143907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1153907Ssaidi@eecs.umich.edu { 1163907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1173907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1183907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1193907Ssaidi@eecs.umich.edu 1203907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1213907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1223907Ssaidi@eecs.umich.edu tlb[x].used = false; 1233907Ssaidi@eecs.umich.edu usedEntries--; 1243907Ssaidi@eecs.umich.edu } 1253907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1263907Ssaidi@eecs.umich.edu } 1273907Ssaidi@eecs.umich.edu } 1283907Ssaidi@eecs.umich.edu } 1293907Ssaidi@eecs.umich.edu 1303907Ssaidi@eecs.umich.edu/* 1313881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1323881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1333881Ssaidi@eecs.umich.edu i->second->valid = false; 1343881Ssaidi@eecs.umich.edu if (i->second->used) { 1353881Ssaidi@eecs.umich.edu i->second->used = false; 1363881Ssaidi@eecs.umich.edu usedEntries--; 1373881Ssaidi@eecs.umich.edu } 1383881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1393881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1403881Ssaidi@eecs.umich.edu i->second); 1413881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1423881Ssaidi@eecs.umich.edu } 1433907Ssaidi@eecs.umich.edu*/ 1443811Ssaidi@eecs.umich.edu 1453826Ssaidi@eecs.umich.edu if (entry != -1) { 1463826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1473826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1483826Ssaidi@eecs.umich.edu } else { 1493881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1503881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1513881Ssaidi@eecs.umich.edu } else { 1523881Ssaidi@eecs.umich.edu x = lastReplaced; 1533881Ssaidi@eecs.umich.edu do { 1543881Ssaidi@eecs.umich.edu ++x; 1553881Ssaidi@eecs.umich.edu if (x == size) 1563881Ssaidi@eecs.umich.edu x = 0; 1573881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1583881Ssaidi@eecs.umich.edu goto insertAllLocked; 1593881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1603881Ssaidi@eecs.umich.edu lastReplaced = x; 1613881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1623881Ssaidi@eecs.umich.edu } 1633881Ssaidi@eecs.umich.edu /* 1643826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1653826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1663826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1673826Ssaidi@eecs.umich.edu break; 1683826Ssaidi@eecs.umich.edu } 1693881Ssaidi@eecs.umich.edu }*/ 1703569Sgblack@eecs.umich.edu } 1713569Sgblack@eecs.umich.edu 1723881Ssaidi@eecs.umich.eduinsertAllLocked: 1733804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1743881Ssaidi@eecs.umich.edu if (!new_entry) { 1753826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1763881Ssaidi@eecs.umich.edu } 1773881Ssaidi@eecs.umich.edu 1783881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1793907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1803907Ssaidi@eecs.umich.edu usedEntries--; 1813929Ssaidi@eecs.umich.edu if (new_entry->valid) 1823929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1833907Ssaidi@eecs.umich.edu 1843907Ssaidi@eecs.umich.edu 1853804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1863804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1873881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1883804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1893804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1903804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1913804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1923804Ssaidi@eecs.umich.edu new_entry->used = true;; 1933804Ssaidi@eecs.umich.edu new_entry->valid = true; 1943804Ssaidi@eecs.umich.edu usedEntries++; 1953569Sgblack@eecs.umich.edu 1963863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1973863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1983804Ssaidi@eecs.umich.edu 1995555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 2005555Snate@binkert.org // but the one we just inserted 2013804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2023804Ssaidi@eecs.umich.edu clearUsedBits(); 2033804Ssaidi@eecs.umich.edu new_entry->used = true; 2043804Ssaidi@eecs.umich.edu usedEntries++; 2053804Ssaidi@eecs.umich.edu } 2063569Sgblack@eecs.umich.edu} 2073804Ssaidi@eecs.umich.edu 2083804Ssaidi@eecs.umich.edu 2093804Ssaidi@eecs.umich.eduTlbEntry* 2105555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 2115555Snate@binkert.org bool update_used) 2123804Ssaidi@eecs.umich.edu{ 2133804Ssaidi@eecs.umich.edu MapIter i; 2143804Ssaidi@eecs.umich.edu TlbRange tr; 2153804Ssaidi@eecs.umich.edu TlbEntry *t; 2163804Ssaidi@eecs.umich.edu 2173811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2183811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2193804Ssaidi@eecs.umich.edu // Assemble full address structure 2203804Ssaidi@eecs.umich.edu tr.va = va; 2215312Sgblack@eecs.umich.edu tr.size = 1; 2223804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2233804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2243804Ssaidi@eecs.umich.edu tr.real = real; 2253804Ssaidi@eecs.umich.edu 2263804Ssaidi@eecs.umich.edu // Try to find the entry 2273804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2283804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2293811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2303804Ssaidi@eecs.umich.edu return NULL; 2313804Ssaidi@eecs.umich.edu } 2323804Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2343804Ssaidi@eecs.umich.edu t = i->second; 2353826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2363826Ssaidi@eecs.umich.edu t->pte.size()); 2374070Ssaidi@eecs.umich.edu 2385555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2395555Snate@binkert.org // one from virttophys() 2404070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2413804Ssaidi@eecs.umich.edu t->used = true; 2423804Ssaidi@eecs.umich.edu usedEntries++; 2433804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2443804Ssaidi@eecs.umich.edu clearUsedBits(); 2453804Ssaidi@eecs.umich.edu t->used = true; 2463804Ssaidi@eecs.umich.edu usedEntries++; 2473804Ssaidi@eecs.umich.edu } 2483804Ssaidi@eecs.umich.edu } 2493804Ssaidi@eecs.umich.edu 2503804Ssaidi@eecs.umich.edu return t; 2513804Ssaidi@eecs.umich.edu} 2523804Ssaidi@eecs.umich.edu 2533826Ssaidi@eecs.umich.eduvoid 2543826Ssaidi@eecs.umich.eduTLB::dumpAll() 2553826Ssaidi@eecs.umich.edu{ 2563863Ssaidi@eecs.umich.edu MapIter i; 2573826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2583826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2593826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2603826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2613826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2623826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2633826Ssaidi@eecs.umich.edu } 2643826Ssaidi@eecs.umich.edu } 2653826Ssaidi@eecs.umich.edu} 2663804Ssaidi@eecs.umich.edu 2673804Ssaidi@eecs.umich.eduvoid 2683804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2693804Ssaidi@eecs.umich.edu{ 2703804Ssaidi@eecs.umich.edu TlbRange tr; 2713804Ssaidi@eecs.umich.edu MapIter i; 2723804Ssaidi@eecs.umich.edu 2733863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2743863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2753863Ssaidi@eecs.umich.edu 2763836Ssaidi@eecs.umich.edu cacheValid = false; 2773836Ssaidi@eecs.umich.edu 2783804Ssaidi@eecs.umich.edu // Assemble full address structure 2793804Ssaidi@eecs.umich.edu tr.va = va; 2805312Sgblack@eecs.umich.edu tr.size = 1; 2813804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2823804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2833804Ssaidi@eecs.umich.edu tr.real = real; 2843804Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2863804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2873804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2883863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2893804Ssaidi@eecs.umich.edu i->second->valid = false; 2903804Ssaidi@eecs.umich.edu if (i->second->used) { 2913804Ssaidi@eecs.umich.edu i->second->used = false; 2923804Ssaidi@eecs.umich.edu usedEntries--; 2933804Ssaidi@eecs.umich.edu } 2943881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2953804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2963804Ssaidi@eecs.umich.edu } 2973804Ssaidi@eecs.umich.edu} 2983804Ssaidi@eecs.umich.edu 2993804Ssaidi@eecs.umich.eduvoid 3003804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 3013804Ssaidi@eecs.umich.edu{ 3023863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3033863Ssaidi@eecs.umich.edu partition_id, context_id); 3043836Ssaidi@eecs.umich.edu cacheValid = false; 3055555Snate@binkert.org for (int x = 0; x < size; x++) { 3063804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3073804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3083881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3093881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3103881Ssaidi@eecs.umich.edu } 3113804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3123804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3133804Ssaidi@eecs.umich.edu tlb[x].used = false; 3143804Ssaidi@eecs.umich.edu usedEntries--; 3153804Ssaidi@eecs.umich.edu } 3163804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3173804Ssaidi@eecs.umich.edu } 3183804Ssaidi@eecs.umich.edu } 3193804Ssaidi@eecs.umich.edu} 3203804Ssaidi@eecs.umich.edu 3213804Ssaidi@eecs.umich.eduvoid 3223804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3233804Ssaidi@eecs.umich.edu{ 3243863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3253836Ssaidi@eecs.umich.edu cacheValid = false; 3265555Snate@binkert.org for (int x = 0; x < size; x++) { 3275288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3285288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3295288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3303804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3313804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3323804Ssaidi@eecs.umich.edu tlb[x].used = false; 3333804Ssaidi@eecs.umich.edu usedEntries--; 3343804Ssaidi@eecs.umich.edu } 3353804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3363804Ssaidi@eecs.umich.edu } 3373804Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu} 3393804Ssaidi@eecs.umich.edu 3403804Ssaidi@eecs.umich.eduvoid 3413804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3423804Ssaidi@eecs.umich.edu{ 3433836Ssaidi@eecs.umich.edu cacheValid = false; 3445555Snate@binkert.org lookupTable.clear(); 3453836Ssaidi@eecs.umich.edu 3465555Snate@binkert.org for (int x = 0; x < size; x++) { 3473881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3483881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3493804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3503907Ssaidi@eecs.umich.edu tlb[x].used = false; 3513804Ssaidi@eecs.umich.edu } 3523804Ssaidi@eecs.umich.edu usedEntries = 0; 3533804Ssaidi@eecs.umich.edu} 3543804Ssaidi@eecs.umich.edu 3553804Ssaidi@eecs.umich.eduuint64_t 3565555Snate@binkert.orgTLB::TteRead(int entry) 3575555Snate@binkert.org{ 3583881Ssaidi@eecs.umich.edu if (entry >= size) 3593881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3603881Ssaidi@eecs.umich.edu 3613804Ssaidi@eecs.umich.edu assert(entry < size); 3623881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3633881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3643881Ssaidi@eecs.umich.edu else 3653881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3663804Ssaidi@eecs.umich.edu} 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.eduuint64_t 3695555Snate@binkert.orgTLB::TagRead(int entry) 3705555Snate@binkert.org{ 3713804Ssaidi@eecs.umich.edu assert(entry < size); 3723804Ssaidi@eecs.umich.edu uint64_t tag; 3733881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3743881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3753804Ssaidi@eecs.umich.edu 3763881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3773881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3783881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3793804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3803804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3813804Ssaidi@eecs.umich.edu return tag; 3823804Ssaidi@eecs.umich.edu} 3833804Ssaidi@eecs.umich.edu 3843804Ssaidi@eecs.umich.edubool 3853804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3863804Ssaidi@eecs.umich.edu{ 3873804Ssaidi@eecs.umich.edu if (am) 3883804Ssaidi@eecs.umich.edu return true; 3893804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3903804Ssaidi@eecs.umich.edu return false; 3913804Ssaidi@eecs.umich.edu return true; 3923804Ssaidi@eecs.umich.edu} 3933804Ssaidi@eecs.umich.edu 3943804Ssaidi@eecs.umich.eduvoid 3954990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3963804Ssaidi@eecs.umich.edu{ 3973804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3983804Ssaidi@eecs.umich.edu sfsr = 0x3; 3993804Ssaidi@eecs.umich.edu else 4003804Ssaidi@eecs.umich.edu sfsr = 1; 4013804Ssaidi@eecs.umich.edu 4023804Ssaidi@eecs.umich.edu if (write) 4033804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4043804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4053804Ssaidi@eecs.umich.edu if (se) 4063804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4073804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4083804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4093804Ssaidi@eecs.umich.edu} 4103804Ssaidi@eecs.umich.edu 4113826Ssaidi@eecs.umich.eduvoid 4124990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4133826Ssaidi@eecs.umich.edu{ 4143916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4153916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4163916Ssaidi@eecs.umich.edu 4174990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4183826Ssaidi@eecs.umich.edu} 4193804Ssaidi@eecs.umich.edu 4203804Ssaidi@eecs.umich.eduvoid 4214990Sgblack@eecs.umich.eduITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 4223804Ssaidi@eecs.umich.edu{ 4233811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4243811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4254990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4263804Ssaidi@eecs.umich.edu} 4273804Ssaidi@eecs.umich.edu 4283804Ssaidi@eecs.umich.eduvoid 4294990Sgblack@eecs.umich.eduDTB::writeSfsr(Addr a, bool write, ContextType ct, 4303804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4313804Ssaidi@eecs.umich.edu{ 4323811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4333811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4344990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4354990Sgblack@eecs.umich.edu sfar = a; 4363804Ssaidi@eecs.umich.edu} 4373804Ssaidi@eecs.umich.edu 4383804Ssaidi@eecs.umich.eduFault 4393804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4403804Ssaidi@eecs.umich.edu{ 4414172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4423833Ssaidi@eecs.umich.edu 4433836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4443836Ssaidi@eecs.umich.edu TlbEntry *e; 4453836Ssaidi@eecs.umich.edu 4463836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4473836Ssaidi@eecs.umich.edu 4483836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4493836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4503836Ssaidi@eecs.umich.edu 4513836Ssaidi@eecs.umich.edu // Be fast if we can! 4523836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4533836Ssaidi@eecs.umich.edu if (cacheEntry) { 4543836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4553836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4565555Snate@binkert.org req->setPaddr(cacheEntry->pte.translate(vaddr)); 4575555Snate@binkert.org return NoFault; 4583836Ssaidi@eecs.umich.edu } 4593836Ssaidi@eecs.umich.edu } else { 4603836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4613836Ssaidi@eecs.umich.edu return NoFault; 4623836Ssaidi@eecs.umich.edu } 4633836Ssaidi@eecs.umich.edu } 4643836Ssaidi@eecs.umich.edu 4653833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4663833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4673833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4683833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4693833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4703833Ssaidi@eecs.umich.edu 4713833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4723833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4733833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4743804Ssaidi@eecs.umich.edu int context; 4753804Ssaidi@eecs.umich.edu ContextType ct; 4763804Ssaidi@eecs.umich.edu int asi; 4773804Ssaidi@eecs.umich.edu bool real = false; 4783804Ssaidi@eecs.umich.edu 4793833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4803833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4813811Ssaidi@eecs.umich.edu 4823804Ssaidi@eecs.umich.edu if (tl > 0) { 4833804Ssaidi@eecs.umich.edu asi = ASI_N; 4843804Ssaidi@eecs.umich.edu ct = Nucleus; 4853804Ssaidi@eecs.umich.edu context = 0; 4863804Ssaidi@eecs.umich.edu } else { 4873804Ssaidi@eecs.umich.edu asi = ASI_P; 4883804Ssaidi@eecs.umich.edu ct = Primary; 4893833Ssaidi@eecs.umich.edu context = pri_context; 4903804Ssaidi@eecs.umich.edu } 4913804Ssaidi@eecs.umich.edu 4923833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4933836Ssaidi@eecs.umich.edu cacheValid = true; 4943836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4953836Ssaidi@eecs.umich.edu cacheEntry = NULL; 4963836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4973804Ssaidi@eecs.umich.edu return NoFault; 4983804Ssaidi@eecs.umich.edu } 4993804Ssaidi@eecs.umich.edu 5003836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5013836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5024990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 5033804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5043804Ssaidi@eecs.umich.edu } 5053804Ssaidi@eecs.umich.edu 5063804Ssaidi@eecs.umich.edu if (addr_mask) 5073804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5083804Ssaidi@eecs.umich.edu 5093804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5104990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 5113804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5123804Ssaidi@eecs.umich.edu } 5133804Ssaidi@eecs.umich.edu 5143833Ssaidi@eecs.umich.edu if (!lsu_im) { 5153836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5163804Ssaidi@eecs.umich.edu real = true; 5173804Ssaidi@eecs.umich.edu context = 0; 5183804Ssaidi@eecs.umich.edu } else { 5193804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5203804Ssaidi@eecs.umich.edu } 5213804Ssaidi@eecs.umich.edu 5223804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5234990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5243804Ssaidi@eecs.umich.edu if (real) 5253804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5263804Ssaidi@eecs.umich.edu else 5274997Sgblack@eecs.umich.edu#if FULL_SYSTEM 5283804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5294997Sgblack@eecs.umich.edu#else 5304997Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5314997Sgblack@eecs.umich.edu#endif 5323804Ssaidi@eecs.umich.edu } 5333804Ssaidi@eecs.umich.edu 5343804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5353804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5364990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5374990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5383804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5393804Ssaidi@eecs.umich.edu } 5403804Ssaidi@eecs.umich.edu 5413836Ssaidi@eecs.umich.edu // cache translation date for next translation 5423836Ssaidi@eecs.umich.edu cacheValid = true; 5433836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5443836Ssaidi@eecs.umich.edu cacheEntry = e; 5453836Ssaidi@eecs.umich.edu 5465555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5473836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5483804Ssaidi@eecs.umich.edu return NoFault; 5493804Ssaidi@eecs.umich.edu} 5503804Ssaidi@eecs.umich.edu 5513804Ssaidi@eecs.umich.eduFault 5523804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5533804Ssaidi@eecs.umich.edu{ 5545555Snate@binkert.org /* 5555555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5565555Snate@binkert.org * it faster! 5575555Snate@binkert.org */ 5584172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5593836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5603836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5613836Ssaidi@eecs.umich.edu ASI asi; 5623836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5633836Ssaidi@eecs.umich.edu bool implicit = false; 5643836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5655570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5663833Ssaidi@eecs.umich.edu 5673836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5683836Ssaidi@eecs.umich.edu vaddr, size, asi); 5693836Ssaidi@eecs.umich.edu 5703929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5713929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5723929Ssaidi@eecs.umich.edu freeList.size()); 5733836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5743836Ssaidi@eecs.umich.edu implicit = true; 5753836Ssaidi@eecs.umich.edu 5764996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5774996Sgblack@eecs.umich.edu // trap later 5784996Sgblack@eecs.umich.edu if (!unaligned) { 5794996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5804996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5814996Sgblack@eecs.umich.edu return NoFault; 5824996Sgblack@eecs.umich.edu } 5834996Sgblack@eecs.umich.edu 5844996Sgblack@eecs.umich.edu // Be fast if we can! 5854996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5864996Sgblack@eecs.umich.edu 5874996Sgblack@eecs.umich.edu 5884996Sgblack@eecs.umich.edu 5894996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5904996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5914996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5924996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5934996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5944996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5955555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 5965555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 5975555Snate@binkert.org req->setFlags(req->getFlags() | UNCACHEABLE); 5985555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5995555Snate@binkert.org return NoFault; 6004996Sgblack@eecs.umich.edu } // if matched 6014996Sgblack@eecs.umich.edu } // if cache entry valid 6024996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 6034996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 6044996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6054996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 6064996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6074996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6085555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 6095555Snate@binkert.org if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6105555Snate@binkert.org req->setFlags(req->getFlags() | UNCACHEABLE); 6115555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6125555Snate@binkert.org return NoFault; 6134996Sgblack@eecs.umich.edu } // if matched 6144996Sgblack@eecs.umich.edu } // if cache entry valid 6154996Sgblack@eecs.umich.edu } 6163836Ssaidi@eecs.umich.edu } 6173836Ssaidi@eecs.umich.edu 6183833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6193833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6203833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6213833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6223833Ssaidi@eecs.umich.edu 6233833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6243833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6253833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6263916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6273833Ssaidi@eecs.umich.edu 6283804Ssaidi@eecs.umich.edu bool real = false; 6293832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6303832Ssaidi@eecs.umich.edu int context = 0; 6313804Ssaidi@eecs.umich.edu 6323804Ssaidi@eecs.umich.edu TlbEntry *e; 6333804Ssaidi@eecs.umich.edu 6343833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6355555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6363804Ssaidi@eecs.umich.edu 6373804Ssaidi@eecs.umich.edu if (implicit) { 6383804Ssaidi@eecs.umich.edu if (tl > 0) { 6393804Ssaidi@eecs.umich.edu asi = ASI_N; 6403804Ssaidi@eecs.umich.edu ct = Nucleus; 6413804Ssaidi@eecs.umich.edu context = 0; 6423804Ssaidi@eecs.umich.edu } else { 6433804Ssaidi@eecs.umich.edu asi = ASI_P; 6443804Ssaidi@eecs.umich.edu ct = Primary; 6453833Ssaidi@eecs.umich.edu context = pri_context; 6463804Ssaidi@eecs.umich.edu } 6473910Ssaidi@eecs.umich.edu } else { 6483804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6493910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6503804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6514990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6523804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6533804Ssaidi@eecs.umich.edu } 6543910Ssaidi@eecs.umich.edu 6553910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6564990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6573804Ssaidi@eecs.umich.edu return new DataAccessException; 6583804Ssaidi@eecs.umich.edu } 6593804Ssaidi@eecs.umich.edu 6603910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6613910Ssaidi@eecs.umich.edu context = pri_context; 6623910Ssaidi@eecs.umich.edu ct = Primary; 6633910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6643910Ssaidi@eecs.umich.edu context = sec_context; 6653910Ssaidi@eecs.umich.edu ct = Secondary; 6663910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6673910Ssaidi@eecs.umich.edu ct = Nucleus; 6683910Ssaidi@eecs.umich.edu context = 0; 6693910Ssaidi@eecs.umich.edu } else { // ???? 6703910Ssaidi@eecs.umich.edu ct = Primary; 6713910Ssaidi@eecs.umich.edu context = pri_context; 6723910Ssaidi@eecs.umich.edu } 6733902Ssaidi@eecs.umich.edu } 6743804Ssaidi@eecs.umich.edu 6753926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6763804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6773804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6784989Sgblack@eecs.umich.edu 6794989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6804989Sgblack@eecs.umich.edu //load differs from a regular one, other than what happens concerning 6814989Sgblack@eecs.umich.edu //nfo and e bits in the TTE 6824989Sgblack@eecs.umich.edu// if (AsiIsNoFault(asi)) 6834989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6843856Ssaidi@eecs.umich.edu 6853804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6863804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6874103Ssaidi@eecs.umich.edu 6884191Ssaidi@eecs.umich.edu if (AsiIsCmt(asi)) 6894191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6904191Ssaidi@eecs.umich.edu 6913824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6924103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6933804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6943804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6953804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6963804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6973824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6983824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6993825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 7003825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 7013823Ssaidi@eecs.umich.edu 7023926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 7034989Sgblack@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 7043823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7053804Ssaidi@eecs.umich.edu } 7063804Ssaidi@eecs.umich.edu 7073826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7084996Sgblack@eecs.umich.edu if (unaligned) { 7094990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 7103826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7113826Ssaidi@eecs.umich.edu } 7123826Ssaidi@eecs.umich.edu 7133826Ssaidi@eecs.umich.edu if (addr_mask) 7143826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7153826Ssaidi@eecs.umich.edu 7163826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7174990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 7183826Ssaidi@eecs.umich.edu return new DataAccessException; 7193826Ssaidi@eecs.umich.edu } 7203826Ssaidi@eecs.umich.edu 7213910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7223804Ssaidi@eecs.umich.edu real = true; 7233804Ssaidi@eecs.umich.edu context = 0; 7245555Snate@binkert.org } 7253804Ssaidi@eecs.umich.edu 7263804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7273836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7283804Ssaidi@eecs.umich.edu return NoFault; 7293804Ssaidi@eecs.umich.edu } 7303804Ssaidi@eecs.umich.edu 7313836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7323804Ssaidi@eecs.umich.edu 7333804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7344990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7353811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7363804Ssaidi@eecs.umich.edu if (real) 7373804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7383804Ssaidi@eecs.umich.edu else 7394997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7403804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7414997Sgblack@eecs.umich.edu#else 7424997Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7434997Sgblack@eecs.umich.edu#endif 7443804Ssaidi@eecs.umich.edu 7453804Ssaidi@eecs.umich.edu } 7463804Ssaidi@eecs.umich.edu 7473928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7484990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7494990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7503928Ssaidi@eecs.umich.edu return new DataAccessException; 7513928Ssaidi@eecs.umich.edu } 7523804Ssaidi@eecs.umich.edu 7533804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7544990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7554990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7563804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7573804Ssaidi@eecs.umich.edu } 7583804Ssaidi@eecs.umich.edu 7593804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7604990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7614990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7623804Ssaidi@eecs.umich.edu return new DataAccessException; 7633804Ssaidi@eecs.umich.edu } 7643804Ssaidi@eecs.umich.edu 7653928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7664990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7674990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7683928Ssaidi@eecs.umich.edu return new DataAccessException; 7693928Ssaidi@eecs.umich.edu } 7703928Ssaidi@eecs.umich.edu 7714090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7723804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7733804Ssaidi@eecs.umich.edu 7743836Ssaidi@eecs.umich.edu // cache translation date for next translation 7753836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7763881Ssaidi@eecs.umich.edu if (!cacheValid) { 7773881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7783881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7793881Ssaidi@eecs.umich.edu } 7803881Ssaidi@eecs.umich.edu 7813836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7823836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7833836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7843836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7853836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7863836Ssaidi@eecs.umich.edu if (implicit) 7873836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7883836Ssaidi@eecs.umich.edu } 7893881Ssaidi@eecs.umich.edu cacheValid = true; 7905555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7913836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7923804Ssaidi@eecs.umich.edu return NoFault; 7934103Ssaidi@eecs.umich.edu 7943806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7954103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7964103Ssaidi@eecs.umich.edu if (!hpriv) { 7974990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7984103Ssaidi@eecs.umich.edu if (priv) 7994103Ssaidi@eecs.umich.edu return new DataAccessException; 8004103Ssaidi@eecs.umich.edu else 8014103Ssaidi@eecs.umich.edu return new PrivilegedAction; 8024103Ssaidi@eecs.umich.edu } 8034103Ssaidi@eecs.umich.edu 8045570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 8055570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 8064990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8074103Ssaidi@eecs.umich.edu return new DataAccessException; 8084103Ssaidi@eecs.umich.edu } 8094103Ssaidi@eecs.umich.edu 8104103Ssaidi@eecs.umich.edu goto regAccessOk; 8114103Ssaidi@eecs.umich.edu 8123804Ssaidi@eecs.umich.edu 8133806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8143806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8154990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8163806Ssaidi@eecs.umich.edu return new DataAccessException; 8173806Ssaidi@eecs.umich.edu } 8183824Ssaidi@eecs.umich.edu goto regAccessOk; 8193824Ssaidi@eecs.umich.edu 8203824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8213824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8224990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8233824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8243824Ssaidi@eecs.umich.edu } 8255570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8264990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8273824Ssaidi@eecs.umich.edu return new DataAccessException; 8283824Ssaidi@eecs.umich.edu } 8293824Ssaidi@eecs.umich.edu goto regAccessOk; 8303824Ssaidi@eecs.umich.edu 8313825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8323825Ssaidi@eecs.umich.edu if (!hpriv) { 8334990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8344070Ssaidi@eecs.umich.edu if (priv) 8353825Ssaidi@eecs.umich.edu return new DataAccessException; 8364070Ssaidi@eecs.umich.edu else 8373825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8383825Ssaidi@eecs.umich.edu } 8393825Ssaidi@eecs.umich.edu goto regAccessOk; 8403825Ssaidi@eecs.umich.edu 8413825Ssaidi@eecs.umich.edu 8423824Ssaidi@eecs.umich.eduregAccessOk: 8433804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8443811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8453806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8463806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8473806Ssaidi@eecs.umich.edu return NoFault; 8483804Ssaidi@eecs.umich.edu}; 8493804Ssaidi@eecs.umich.edu 8504997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8514997Sgblack@eecs.umich.edu 8523806Ssaidi@eecs.umich.eduTick 8533806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8543806Ssaidi@eecs.umich.edu{ 8553823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8563823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8574070Ssaidi@eecs.umich.edu uint64_t temp; 8583823Ssaidi@eecs.umich.edu 8593823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8603823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8613823Ssaidi@eecs.umich.edu 8625555Snate@binkert.org ITB *itb = tc->getITBPtr(); 8634990Sgblack@eecs.umich.edu 8643823Ssaidi@eecs.umich.edu switch (asi) { 8653823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8663823Ssaidi@eecs.umich.edu assert(va == 0); 8674172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8683823Ssaidi@eecs.umich.edu break; 8693823Ssaidi@eecs.umich.edu case ASI_MMU: 8703823Ssaidi@eecs.umich.edu switch (va) { 8713823Ssaidi@eecs.umich.edu case 0x8: 8724172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8733823Ssaidi@eecs.umich.edu break; 8743823Ssaidi@eecs.umich.edu case 0x10: 8754172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8763823Ssaidi@eecs.umich.edu break; 8773823Ssaidi@eecs.umich.edu default: 8783823Ssaidi@eecs.umich.edu goto doMmuReadError; 8793823Ssaidi@eecs.umich.edu } 8803823Ssaidi@eecs.umich.edu break; 8813824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8824172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8833824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8843824Ssaidi@eecs.umich.edu break; 8853823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8863823Ssaidi@eecs.umich.edu assert(va == 0); 8874990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8883823Ssaidi@eecs.umich.edu break; 8893823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8903823Ssaidi@eecs.umich.edu assert(va == 0); 8914990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8923823Ssaidi@eecs.umich.edu break; 8933823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8943823Ssaidi@eecs.umich.edu assert(va == 0); 8954990Sgblack@eecs.umich.edu pkt->set(c0_config); 8963823Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 8994990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9034990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9074990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9114990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9154990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9194990Sgblack@eecs.umich.edu pkt->set(cx_config); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9234990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9274990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9314990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9323823Ssaidi@eecs.umich.edu break; 9333826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9343912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9353826Ssaidi@eecs.umich.edu break; 9363823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9373823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9384172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9393823Ssaidi@eecs.umich.edu break; 9403826Ssaidi@eecs.umich.edu case ASI_IMMU: 9413826Ssaidi@eecs.umich.edu switch (va) { 9423833Ssaidi@eecs.umich.edu case 0x0: 9434990Sgblack@eecs.umich.edu temp = itb->tag_access; 9443833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9453833Ssaidi@eecs.umich.edu break; 9463906Ssaidi@eecs.umich.edu case 0x18: 9474990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9483906Ssaidi@eecs.umich.edu break; 9493826Ssaidi@eecs.umich.edu case 0x30: 9504990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9513826Ssaidi@eecs.umich.edu break; 9523826Ssaidi@eecs.umich.edu default: 9533826Ssaidi@eecs.umich.edu goto doMmuReadError; 9543826Ssaidi@eecs.umich.edu } 9553826Ssaidi@eecs.umich.edu break; 9563823Ssaidi@eecs.umich.edu case ASI_DMMU: 9573823Ssaidi@eecs.umich.edu switch (va) { 9583833Ssaidi@eecs.umich.edu case 0x0: 9594990Sgblack@eecs.umich.edu temp = tag_access; 9603833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9613833Ssaidi@eecs.umich.edu break; 9623906Ssaidi@eecs.umich.edu case 0x18: 9634990Sgblack@eecs.umich.edu pkt->set(sfsr); 9643906Ssaidi@eecs.umich.edu break; 9653906Ssaidi@eecs.umich.edu case 0x20: 9664990Sgblack@eecs.umich.edu pkt->set(sfar); 9673906Ssaidi@eecs.umich.edu break; 9683826Ssaidi@eecs.umich.edu case 0x30: 9694990Sgblack@eecs.umich.edu pkt->set(tag_access); 9703826Ssaidi@eecs.umich.edu break; 9713823Ssaidi@eecs.umich.edu case 0x80: 9724172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9733823Ssaidi@eecs.umich.edu break; 9743823Ssaidi@eecs.umich.edu default: 9753823Ssaidi@eecs.umich.edu goto doMmuReadError; 9763823Ssaidi@eecs.umich.edu } 9773823Ssaidi@eecs.umich.edu break; 9783833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9794070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9804990Sgblack@eecs.umich.edu tag_access, 9814990Sgblack@eecs.umich.edu c0_tsb_ps0, 9824990Sgblack@eecs.umich.edu c0_config, 9834990Sgblack@eecs.umich.edu cx_tsb_ps0, 9844990Sgblack@eecs.umich.edu cx_config)); 9853833Ssaidi@eecs.umich.edu break; 9863833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9874070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9884990Sgblack@eecs.umich.edu tag_access, 9894990Sgblack@eecs.umich.edu c0_tsb_ps1, 9904990Sgblack@eecs.umich.edu c0_config, 9914990Sgblack@eecs.umich.edu cx_tsb_ps1, 9924990Sgblack@eecs.umich.edu cx_config)); 9933833Ssaidi@eecs.umich.edu break; 9943899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9954070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9964990Sgblack@eecs.umich.edu itb->tag_access, 9974990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 9984990Sgblack@eecs.umich.edu itb->c0_config, 9994990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10004990Sgblack@eecs.umich.edu itb->cx_config)); 10013899Ssaidi@eecs.umich.edu break; 10023899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10034070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10044990Sgblack@eecs.umich.edu itb->tag_access, 10054990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10064990Sgblack@eecs.umich.edu itb->c0_config, 10074990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10084990Sgblack@eecs.umich.edu itb->cx_config)); 10093899Ssaidi@eecs.umich.edu break; 10104103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10115646Sgblack@eecs.umich.edu { 10125646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10135646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10145646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10155646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10165646Sgblack@eecs.umich.edu } 10174103Ssaidi@eecs.umich.edu break; 10184103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10195646Sgblack@eecs.umich.edu { 10205646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10215646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 10225646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 10235646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 10245704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); 10255646Sgblack@eecs.umich.edu pkt->set(temp); 10265646Sgblack@eecs.umich.edu } 10274103Ssaidi@eecs.umich.edu break; 10283823Ssaidi@eecs.umich.edu default: 10293823Ssaidi@eecs.umich.edudoMmuReadError: 10303823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10313823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10323823Ssaidi@eecs.umich.edu } 10334870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10345100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 10353806Ssaidi@eecs.umich.edu} 10363806Ssaidi@eecs.umich.edu 10373806Ssaidi@eecs.umich.eduTick 10383806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10393806Ssaidi@eecs.umich.edu{ 10403823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10413823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10423823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10433823Ssaidi@eecs.umich.edu 10443826Ssaidi@eecs.umich.edu Addr ta_insert; 10453826Ssaidi@eecs.umich.edu Addr va_insert; 10463826Ssaidi@eecs.umich.edu Addr ct_insert; 10473826Ssaidi@eecs.umich.edu int part_insert; 10483826Ssaidi@eecs.umich.edu int entry_insert = -1; 10493826Ssaidi@eecs.umich.edu bool real_insert; 10503863Ssaidi@eecs.umich.edu bool ignore; 10513863Ssaidi@eecs.umich.edu int part_id; 10523863Ssaidi@eecs.umich.edu int ctx_id; 10533826Ssaidi@eecs.umich.edu PageTableEntry pte; 10543826Ssaidi@eecs.umich.edu 10553825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10563823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10573823Ssaidi@eecs.umich.edu 10585555Snate@binkert.org ITB *itb = tc->getITBPtr(); 10594990Sgblack@eecs.umich.edu 10603823Ssaidi@eecs.umich.edu switch (asi) { 10613823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10623823Ssaidi@eecs.umich.edu assert(va == 0); 10634172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10643823Ssaidi@eecs.umich.edu break; 10653823Ssaidi@eecs.umich.edu case ASI_MMU: 10663823Ssaidi@eecs.umich.edu switch (va) { 10673823Ssaidi@eecs.umich.edu case 0x8: 10684172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10693823Ssaidi@eecs.umich.edu break; 10703823Ssaidi@eecs.umich.edu case 0x10: 10714172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10723823Ssaidi@eecs.umich.edu break; 10733823Ssaidi@eecs.umich.edu default: 10743823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10753823Ssaidi@eecs.umich.edu } 10763823Ssaidi@eecs.umich.edu break; 10773824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10783825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10794172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10803824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10813824Ssaidi@eecs.umich.edu break; 10823823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10833823Ssaidi@eecs.umich.edu assert(va == 0); 10844990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10853823Ssaidi@eecs.umich.edu break; 10863823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10873823Ssaidi@eecs.umich.edu assert(va == 0); 10884990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10893823Ssaidi@eecs.umich.edu break; 10903823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10913823Ssaidi@eecs.umich.edu assert(va == 0); 10924990Sgblack@eecs.umich.edu c0_config = data; 10933823Ssaidi@eecs.umich.edu break; 10943823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10953823Ssaidi@eecs.umich.edu assert(va == 0); 10964990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 10973823Ssaidi@eecs.umich.edu break; 10983823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10993823Ssaidi@eecs.umich.edu assert(va == 0); 11004990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11013823Ssaidi@eecs.umich.edu break; 11023823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11033823Ssaidi@eecs.umich.edu assert(va == 0); 11044990Sgblack@eecs.umich.edu itb->c0_config = data; 11053823Ssaidi@eecs.umich.edu break; 11063823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11073823Ssaidi@eecs.umich.edu assert(va == 0); 11084990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11093823Ssaidi@eecs.umich.edu break; 11103823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11113823Ssaidi@eecs.umich.edu assert(va == 0); 11124990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11133823Ssaidi@eecs.umich.edu break; 11143823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11153823Ssaidi@eecs.umich.edu assert(va == 0); 11164990Sgblack@eecs.umich.edu cx_config = data; 11173823Ssaidi@eecs.umich.edu break; 11183823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11193823Ssaidi@eecs.umich.edu assert(va == 0); 11204990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11213823Ssaidi@eecs.umich.edu break; 11223823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11233823Ssaidi@eecs.umich.edu assert(va == 0); 11244990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11253823Ssaidi@eecs.umich.edu break; 11263823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11273823Ssaidi@eecs.umich.edu assert(va == 0); 11284990Sgblack@eecs.umich.edu itb->cx_config = data; 11293823Ssaidi@eecs.umich.edu break; 11303825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11313825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11323825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11333825Ssaidi@eecs.umich.edu break; 11343823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11353823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11364172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11373823Ssaidi@eecs.umich.edu break; 11383826Ssaidi@eecs.umich.edu case ASI_IMMU: 11393826Ssaidi@eecs.umich.edu switch (va) { 11403906Ssaidi@eecs.umich.edu case 0x18: 11414990Sgblack@eecs.umich.edu itb->sfsr = data; 11423906Ssaidi@eecs.umich.edu break; 11433826Ssaidi@eecs.umich.edu case 0x30: 11443916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11454990Sgblack@eecs.umich.edu itb->tag_access = data; 11463826Ssaidi@eecs.umich.edu break; 11473826Ssaidi@eecs.umich.edu default: 11483826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11493826Ssaidi@eecs.umich.edu } 11503826Ssaidi@eecs.umich.edu break; 11513826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11523826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11533826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11543826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11554990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11563826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11573826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11584172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11593826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11603826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11613826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11623826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11633826Ssaidi@eecs.umich.edu pte, entry_insert); 11643826Ssaidi@eecs.umich.edu break; 11653826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11663826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11673826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11683826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11694990Sgblack@eecs.umich.edu ta_insert = tag_access; 11703826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11713826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11724172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11733826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11743826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11753826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11765555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11775555Snate@binkert.org entry_insert); 11783826Ssaidi@eecs.umich.edu break; 11793863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11803863Ssaidi@eecs.umich.edu ignore = false; 11813863Ssaidi@eecs.umich.edu ctx_id = -1; 11824172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11833863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11843863Ssaidi@eecs.umich.edu case 0: 11854172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11863863Ssaidi@eecs.umich.edu break; 11873863Ssaidi@eecs.umich.edu case 1: 11883863Ssaidi@eecs.umich.edu ignore = true; 11893863Ssaidi@eecs.umich.edu break; 11903863Ssaidi@eecs.umich.edu case 3: 11913863Ssaidi@eecs.umich.edu ctx_id = 0; 11923863Ssaidi@eecs.umich.edu break; 11933863Ssaidi@eecs.umich.edu default: 11943863Ssaidi@eecs.umich.edu ignore = true; 11953863Ssaidi@eecs.umich.edu } 11963863Ssaidi@eecs.umich.edu 11973863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11983863Ssaidi@eecs.umich.edu case 0: // demap page 11993863Ssaidi@eecs.umich.edu if (!ignore) 12003863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 12013863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 12023863Ssaidi@eecs.umich.edu break; 12033863Ssaidi@eecs.umich.edu case 1: //demap context 12043863Ssaidi@eecs.umich.edu if (!ignore) 12053863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 12063863Ssaidi@eecs.umich.edu break; 12073863Ssaidi@eecs.umich.edu case 2: 12083863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12093863Ssaidi@eecs.umich.edu break; 12103863Ssaidi@eecs.umich.edu default: 12113863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12123863Ssaidi@eecs.umich.edu } 12133863Ssaidi@eecs.umich.edu break; 12143823Ssaidi@eecs.umich.edu case ASI_DMMU: 12153823Ssaidi@eecs.umich.edu switch (va) { 12163906Ssaidi@eecs.umich.edu case 0x18: 12174990Sgblack@eecs.umich.edu sfsr = data; 12183906Ssaidi@eecs.umich.edu break; 12193826Ssaidi@eecs.umich.edu case 0x30: 12203916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12214990Sgblack@eecs.umich.edu tag_access = data; 12223826Ssaidi@eecs.umich.edu break; 12233823Ssaidi@eecs.umich.edu case 0x80: 12244172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12253823Ssaidi@eecs.umich.edu break; 12263823Ssaidi@eecs.umich.edu default: 12273823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12283823Ssaidi@eecs.umich.edu } 12293823Ssaidi@eecs.umich.edu break; 12303863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12313863Ssaidi@eecs.umich.edu ignore = false; 12323863Ssaidi@eecs.umich.edu ctx_id = -1; 12334172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12343863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12353863Ssaidi@eecs.umich.edu case 0: 12364172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12373863Ssaidi@eecs.umich.edu break; 12383863Ssaidi@eecs.umich.edu case 1: 12394172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12403863Ssaidi@eecs.umich.edu break; 12413863Ssaidi@eecs.umich.edu case 3: 12423863Ssaidi@eecs.umich.edu ctx_id = 0; 12433863Ssaidi@eecs.umich.edu break; 12443863Ssaidi@eecs.umich.edu default: 12453863Ssaidi@eecs.umich.edu ignore = true; 12463863Ssaidi@eecs.umich.edu } 12473863Ssaidi@eecs.umich.edu 12483863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12493863Ssaidi@eecs.umich.edu case 0: // demap page 12503863Ssaidi@eecs.umich.edu if (!ignore) 12513863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12523863Ssaidi@eecs.umich.edu break; 12533863Ssaidi@eecs.umich.edu case 1: //demap context 12543863Ssaidi@eecs.umich.edu if (!ignore) 12553863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12563863Ssaidi@eecs.umich.edu break; 12573863Ssaidi@eecs.umich.edu case 2: 12583863Ssaidi@eecs.umich.edu demapAll(part_id); 12593863Ssaidi@eecs.umich.edu break; 12603863Ssaidi@eecs.umich.edu default: 12613863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12623863Ssaidi@eecs.umich.edu } 12633863Ssaidi@eecs.umich.edu break; 12644103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12655646Sgblack@eecs.umich.edu { 12665646Sgblack@eecs.umich.edu int msb; 12675646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12685646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12695646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 12705646Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 12715704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12725646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 12735704Snate@binkert.org tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); 12745646Sgblack@eecs.umich.edu } 12754103Ssaidi@eecs.umich.edu } 12764103Ssaidi@eecs.umich.edu break; 12774103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12784103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12795704Snate@binkert.org postInterrupt(bits(data, 5, 0), 0); 12804103Ssaidi@eecs.umich.edu break; 12815555Snate@binkert.org default: 12823823Ssaidi@eecs.umich.edudoMmuWriteError: 12833823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12843823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12853823Ssaidi@eecs.umich.edu } 12864870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12875100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 12883806Ssaidi@eecs.umich.edu} 12893806Ssaidi@eecs.umich.edu 12904997Sgblack@eecs.umich.edu#endif 12914997Sgblack@eecs.umich.edu 12923804Ssaidi@eecs.umich.eduvoid 12934070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12944070Ssaidi@eecs.umich.edu{ 12954070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12964990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 12974070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12984990Sgblack@eecs.umich.edu c0_tsb_ps0, 12994990Sgblack@eecs.umich.edu c0_config, 13004990Sgblack@eecs.umich.edu cx_tsb_ps0, 13014990Sgblack@eecs.umich.edu cx_config); 13024070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13034990Sgblack@eecs.umich.edu c0_tsb_ps1, 13044990Sgblack@eecs.umich.edu c0_config, 13054990Sgblack@eecs.umich.edu cx_tsb_ps1, 13064990Sgblack@eecs.umich.edu cx_config); 13074070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13084990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13094990Sgblack@eecs.umich.edu itb->c0_config, 13104990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13114990Sgblack@eecs.umich.edu itb->cx_config); 13124070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13134990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13144990Sgblack@eecs.umich.edu itb->c0_config, 13154990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13164990Sgblack@eecs.umich.edu itb->cx_config); 13174070Ssaidi@eecs.umich.edu} 13184070Ssaidi@eecs.umich.edu 13194070Ssaidi@eecs.umich.eduuint64_t 13204070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13214070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13224070Ssaidi@eecs.umich.edu{ 13234070Ssaidi@eecs.umich.edu uint64_t tsb; 13244070Ssaidi@eecs.umich.edu uint64_t config; 13254070Ssaidi@eecs.umich.edu 13264070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13274070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13284070Ssaidi@eecs.umich.edu config = c0_config; 13294070Ssaidi@eecs.umich.edu } else { 13304070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13314070Ssaidi@eecs.umich.edu config = cX_config; 13324070Ssaidi@eecs.umich.edu } 13334070Ssaidi@eecs.umich.edu 13344070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13354070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13364070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13374070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13384070Ssaidi@eecs.umich.edu 13394070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13404070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13414070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13424070Ssaidi@eecs.umich.edu 13434070Ssaidi@eecs.umich.edu return ptr; 13444070Ssaidi@eecs.umich.edu} 13454070Ssaidi@eecs.umich.edu 13464070Ssaidi@eecs.umich.eduvoid 13473804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13483804Ssaidi@eecs.umich.edu{ 13494000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13504000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13514000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13524000Ssaidi@eecs.umich.edu 13534000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13544000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13554000Ssaidi@eecs.umich.edu int cntr = 0; 13564000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13574000Ssaidi@eecs.umich.edu i = freeList.begin(); 13584000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13594000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13604000Ssaidi@eecs.umich.edu i++; 13614000Ssaidi@eecs.umich.edu } 13624000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13634000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13644000Ssaidi@eecs.umich.edu 13654990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13664990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13674990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13684990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13694990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13704990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13714990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13724990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13735276Ssaidi@eecs.umich.edu 13745276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13755276Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13765276Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13775276Ssaidi@eecs.umich.edu } 13783804Ssaidi@eecs.umich.edu} 13793804Ssaidi@eecs.umich.edu 13803804Ssaidi@eecs.umich.eduvoid 13813804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13823804Ssaidi@eecs.umich.edu{ 13834000Ssaidi@eecs.umich.edu int oldSize; 13844000Ssaidi@eecs.umich.edu 13854000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13864000Ssaidi@eecs.umich.edu if (oldSize != size) 13874000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13884000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13894000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13904000Ssaidi@eecs.umich.edu 13914000Ssaidi@eecs.umich.edu int cntr; 13924000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13934000Ssaidi@eecs.umich.edu 13944000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13954000Ssaidi@eecs.umich.edu freeList.clear(); 13964000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13974000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13984000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13994000Ssaidi@eecs.umich.edu 14004990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14014990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14024990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14034990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14044990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14054990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14064990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14074990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14085276Ssaidi@eecs.umich.edu 14095276Ssaidi@eecs.umich.edu lookupTable.clear(); 14105276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14115276Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14125276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14135276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14145276Ssaidi@eecs.umich.edu 14155276Ssaidi@eecs.umich.edu } 14164990Sgblack@eecs.umich.edu} 14174990Sgblack@eecs.umich.edu 14184990Sgblack@eecs.umich.eduvoid 14194990Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 14204990Sgblack@eecs.umich.edu{ 14214990Sgblack@eecs.umich.edu TLB::serialize(os); 14224990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 14234990Sgblack@eecs.umich.edu} 14244990Sgblack@eecs.umich.edu 14254990Sgblack@eecs.umich.eduvoid 14264990Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 14274990Sgblack@eecs.umich.edu{ 14284990Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 14294990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14303804Ssaidi@eecs.umich.edu} 14313804Ssaidi@eecs.umich.edu 14324088Sbinkertn@umich.edu/* end namespace SparcISA */ } 14334088Sbinkertn@umich.edu 14344762Snate@binkert.orgSparcISA::ITB * 14354762Snate@binkert.orgSparcITBParams::create() 14363804Ssaidi@eecs.umich.edu{ 14375034Smilesck@eecs.umich.edu return new SparcISA::ITB(this); 14383804Ssaidi@eecs.umich.edu} 14393804Ssaidi@eecs.umich.edu 14404762Snate@binkert.orgSparcISA::DTB * 14414762Snate@binkert.orgSparcDTBParams::create() 14423804Ssaidi@eecs.umich.edu{ 14435034Smilesck@eecs.umich.edu return new SparcISA::DTB(this); 14443804Ssaidi@eecs.umich.edu} 1445