tlb.cc revision 5100
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 424103Ssaidi@eecs.umich.edu#include "sim/system.hh" 433569Sgblack@eecs.umich.edu 443804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 453804Ssaidi@eecs.umich.edu * */ 464088Sbinkertn@umich.edunamespace SparcISA { 473569Sgblack@eecs.umich.edu 485034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 495034Smilesck@eecs.umich.edu : SimObject(p), size(p->size), usedEntries(0), lastReplaced(0), 503881Ssaidi@eecs.umich.edu cacheValid(false) 513804Ssaidi@eecs.umich.edu{ 523804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 533804Ssaidi@eecs.umich.edu if (size > 64) 543804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 553569Sgblack@eecs.umich.edu 563804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 573918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 603881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 614990Sgblack@eecs.umich.edu 624990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 634990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 644990Sgblack@eecs.umich.edu c0_config = 0; 654990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 664990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 674990Sgblack@eecs.umich.edu cx_config = 0; 684990Sgblack@eecs.umich.edu sfsr = 0; 694990Sgblack@eecs.umich.edu tag_access = 0; 703804Ssaidi@eecs.umich.edu} 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 743804Ssaidi@eecs.umich.edu{ 753804Ssaidi@eecs.umich.edu MapIter i; 763881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 773804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 783804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 793804Ssaidi@eecs.umich.edu t->used = false; 803804Ssaidi@eecs.umich.edu usedEntries--; 813804Ssaidi@eecs.umich.edu } 823804Ssaidi@eecs.umich.edu } 833804Ssaidi@eecs.umich.edu} 843569Sgblack@eecs.umich.edu 853569Sgblack@eecs.umich.edu 863804Ssaidi@eecs.umich.eduvoid 873804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 883826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 893804Ssaidi@eecs.umich.edu{ 903569Sgblack@eecs.umich.edu 913569Sgblack@eecs.umich.edu 923804Ssaidi@eecs.umich.edu MapIter i; 933826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 943907Ssaidi@eecs.umich.edu// TlbRange tr; 953826Ssaidi@eecs.umich.edu int x; 963811Ssaidi@eecs.umich.edu 973836Ssaidi@eecs.umich.edu cacheValid = false; 983915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 993907Ssaidi@eecs.umich.edu /* tr.va = va; 1003881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1013881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1023881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1033881Ssaidi@eecs.umich.edu tr.real = real; 1043907Ssaidi@eecs.umich.edu*/ 1053881Ssaidi@eecs.umich.edu 1063881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1073881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1083881Ssaidi@eecs.umich.edu 1093881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1103907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1113907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1123907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1133907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1143907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1153907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1163907Ssaidi@eecs.umich.edu { 1173907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1183907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1193907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1203907Ssaidi@eecs.umich.edu 1213907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1223907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1233907Ssaidi@eecs.umich.edu tlb[x].used = false; 1243907Ssaidi@eecs.umich.edu usedEntries--; 1253907Ssaidi@eecs.umich.edu } 1263907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1273907Ssaidi@eecs.umich.edu } 1283907Ssaidi@eecs.umich.edu } 1293907Ssaidi@eecs.umich.edu } 1303907Ssaidi@eecs.umich.edu 1313907Ssaidi@eecs.umich.edu 1323907Ssaidi@eecs.umich.edu/* 1333881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1343881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1353881Ssaidi@eecs.umich.edu i->second->valid = false; 1363881Ssaidi@eecs.umich.edu if (i->second->used) { 1373881Ssaidi@eecs.umich.edu i->second->used = false; 1383881Ssaidi@eecs.umich.edu usedEntries--; 1393881Ssaidi@eecs.umich.edu } 1403881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1413881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1423881Ssaidi@eecs.umich.edu i->second); 1433881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1443881Ssaidi@eecs.umich.edu } 1453907Ssaidi@eecs.umich.edu*/ 1463811Ssaidi@eecs.umich.edu 1473826Ssaidi@eecs.umich.edu if (entry != -1) { 1483826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1493826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1503826Ssaidi@eecs.umich.edu } else { 1513881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1523881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1533881Ssaidi@eecs.umich.edu } else { 1543881Ssaidi@eecs.umich.edu x = lastReplaced; 1553881Ssaidi@eecs.umich.edu do { 1563881Ssaidi@eecs.umich.edu ++x; 1573881Ssaidi@eecs.umich.edu if (x == size) 1583881Ssaidi@eecs.umich.edu x = 0; 1593881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1603881Ssaidi@eecs.umich.edu goto insertAllLocked; 1613881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1623881Ssaidi@eecs.umich.edu lastReplaced = x; 1633881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1643881Ssaidi@eecs.umich.edu } 1653881Ssaidi@eecs.umich.edu /* 1663826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1673826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1683826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1693826Ssaidi@eecs.umich.edu break; 1703826Ssaidi@eecs.umich.edu } 1713881Ssaidi@eecs.umich.edu }*/ 1723569Sgblack@eecs.umich.edu } 1733569Sgblack@eecs.umich.edu 1743881Ssaidi@eecs.umich.eduinsertAllLocked: 1753804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1763881Ssaidi@eecs.umich.edu if (!new_entry) { 1773826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1783881Ssaidi@eecs.umich.edu } 1793881Ssaidi@eecs.umich.edu 1803881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1813907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1823907Ssaidi@eecs.umich.edu usedEntries--; 1833929Ssaidi@eecs.umich.edu if (new_entry->valid) 1843929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1853907Ssaidi@eecs.umich.edu 1863907Ssaidi@eecs.umich.edu 1873804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1883804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1893881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1903804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1913804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1923804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1933804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1943804Ssaidi@eecs.umich.edu new_entry->used = true;; 1953804Ssaidi@eecs.umich.edu new_entry->valid = true; 1963804Ssaidi@eecs.umich.edu usedEntries++; 1973569Sgblack@eecs.umich.edu 1983569Sgblack@eecs.umich.edu 1993569Sgblack@eecs.umich.edu 2003863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 2013863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 2023804Ssaidi@eecs.umich.edu 2033804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 2043804Ssaidi@eecs.umich.edu // one we just inserted 2053804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2063804Ssaidi@eecs.umich.edu clearUsedBits(); 2073804Ssaidi@eecs.umich.edu new_entry->used = true; 2083804Ssaidi@eecs.umich.edu usedEntries++; 2093804Ssaidi@eecs.umich.edu } 2103804Ssaidi@eecs.umich.edu 2113569Sgblack@eecs.umich.edu} 2123804Ssaidi@eecs.umich.edu 2133804Ssaidi@eecs.umich.edu 2143804Ssaidi@eecs.umich.eduTlbEntry* 2154070Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 2164070Ssaidi@eecs.umich.edu update_used) 2173804Ssaidi@eecs.umich.edu{ 2183804Ssaidi@eecs.umich.edu MapIter i; 2193804Ssaidi@eecs.umich.edu TlbRange tr; 2203804Ssaidi@eecs.umich.edu TlbEntry *t; 2213804Ssaidi@eecs.umich.edu 2223811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2233811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2243804Ssaidi@eecs.umich.edu // Assemble full address structure 2253804Ssaidi@eecs.umich.edu tr.va = va; 2263863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2273804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2283804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2293804Ssaidi@eecs.umich.edu tr.real = real; 2303804Ssaidi@eecs.umich.edu 2313804Ssaidi@eecs.umich.edu // Try to find the entry 2323804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2333804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2343811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2353804Ssaidi@eecs.umich.edu return NULL; 2363804Ssaidi@eecs.umich.edu } 2373804Ssaidi@eecs.umich.edu 2383804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2393804Ssaidi@eecs.umich.edu t = i->second; 2403826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2413826Ssaidi@eecs.umich.edu t->pte.size()); 2424070Ssaidi@eecs.umich.edu 2434070Ssaidi@eecs.umich.edu // Update the used bits only if this is a real access (not a fake one from 2444070Ssaidi@eecs.umich.edu // virttophys() 2454070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2463804Ssaidi@eecs.umich.edu t->used = true; 2473804Ssaidi@eecs.umich.edu usedEntries++; 2483804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2493804Ssaidi@eecs.umich.edu clearUsedBits(); 2503804Ssaidi@eecs.umich.edu t->used = true; 2513804Ssaidi@eecs.umich.edu usedEntries++; 2523804Ssaidi@eecs.umich.edu } 2533804Ssaidi@eecs.umich.edu } 2543804Ssaidi@eecs.umich.edu 2553804Ssaidi@eecs.umich.edu return t; 2563804Ssaidi@eecs.umich.edu} 2573804Ssaidi@eecs.umich.edu 2583826Ssaidi@eecs.umich.eduvoid 2593826Ssaidi@eecs.umich.eduTLB::dumpAll() 2603826Ssaidi@eecs.umich.edu{ 2613863Ssaidi@eecs.umich.edu MapIter i; 2623826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2633826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2643826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2653826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2663826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2673826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2683826Ssaidi@eecs.umich.edu } 2693826Ssaidi@eecs.umich.edu } 2703826Ssaidi@eecs.umich.edu} 2713804Ssaidi@eecs.umich.edu 2723804Ssaidi@eecs.umich.eduvoid 2733804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2743804Ssaidi@eecs.umich.edu{ 2753804Ssaidi@eecs.umich.edu TlbRange tr; 2763804Ssaidi@eecs.umich.edu MapIter i; 2773804Ssaidi@eecs.umich.edu 2783863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2793863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2803863Ssaidi@eecs.umich.edu 2813836Ssaidi@eecs.umich.edu cacheValid = false; 2823836Ssaidi@eecs.umich.edu 2833804Ssaidi@eecs.umich.edu // Assemble full address structure 2843804Ssaidi@eecs.umich.edu tr.va = va; 2853863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2863804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2873804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2883804Ssaidi@eecs.umich.edu tr.real = real; 2893804Ssaidi@eecs.umich.edu 2903804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2913804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2923804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2933863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2943804Ssaidi@eecs.umich.edu i->second->valid = false; 2953804Ssaidi@eecs.umich.edu if (i->second->used) { 2963804Ssaidi@eecs.umich.edu i->second->used = false; 2973804Ssaidi@eecs.umich.edu usedEntries--; 2983804Ssaidi@eecs.umich.edu } 2993881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 3003804Ssaidi@eecs.umich.edu lookupTable.erase(i); 3013804Ssaidi@eecs.umich.edu } 3023804Ssaidi@eecs.umich.edu} 3033804Ssaidi@eecs.umich.edu 3043804Ssaidi@eecs.umich.eduvoid 3053804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 3063804Ssaidi@eecs.umich.edu{ 3073804Ssaidi@eecs.umich.edu int x; 3083863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3093863Ssaidi@eecs.umich.edu partition_id, context_id); 3103836Ssaidi@eecs.umich.edu cacheValid = false; 3113804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3123804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3133804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3143881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3153881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3163881Ssaidi@eecs.umich.edu } 3173804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3183804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3193804Ssaidi@eecs.umich.edu tlb[x].used = false; 3203804Ssaidi@eecs.umich.edu usedEntries--; 3213804Ssaidi@eecs.umich.edu } 3223804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3233804Ssaidi@eecs.umich.edu } 3243804Ssaidi@eecs.umich.edu } 3253804Ssaidi@eecs.umich.edu} 3263804Ssaidi@eecs.umich.edu 3273804Ssaidi@eecs.umich.eduvoid 3283804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3293804Ssaidi@eecs.umich.edu{ 3303804Ssaidi@eecs.umich.edu int x; 3313863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3323836Ssaidi@eecs.umich.edu cacheValid = false; 3333804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3343804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3353881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3363881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3373881Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3393804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3403804Ssaidi@eecs.umich.edu tlb[x].used = false; 3413804Ssaidi@eecs.umich.edu usedEntries--; 3423804Ssaidi@eecs.umich.edu } 3433804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3443804Ssaidi@eecs.umich.edu } 3453804Ssaidi@eecs.umich.edu } 3463804Ssaidi@eecs.umich.edu} 3473804Ssaidi@eecs.umich.edu 3483804Ssaidi@eecs.umich.eduvoid 3493804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3503804Ssaidi@eecs.umich.edu{ 3513804Ssaidi@eecs.umich.edu int x; 3523836Ssaidi@eecs.umich.edu cacheValid = false; 3533836Ssaidi@eecs.umich.edu 3543881Ssaidi@eecs.umich.edu freeList.clear(); 3553907Ssaidi@eecs.umich.edu lookupTable.clear(); 3563804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3573881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3583881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3593804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3603907Ssaidi@eecs.umich.edu tlb[x].used = false; 3613804Ssaidi@eecs.umich.edu } 3623804Ssaidi@eecs.umich.edu usedEntries = 0; 3633804Ssaidi@eecs.umich.edu} 3643804Ssaidi@eecs.umich.edu 3653804Ssaidi@eecs.umich.eduuint64_t 3663804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3673881Ssaidi@eecs.umich.edu if (entry >= size) 3683881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3693881Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu assert(entry < size); 3713881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3723881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3733881Ssaidi@eecs.umich.edu else 3743881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3753804Ssaidi@eecs.umich.edu} 3763804Ssaidi@eecs.umich.edu 3773804Ssaidi@eecs.umich.eduuint64_t 3783804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3793804Ssaidi@eecs.umich.edu assert(entry < size); 3803804Ssaidi@eecs.umich.edu uint64_t tag; 3813881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3823881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3833804Ssaidi@eecs.umich.edu 3843881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3853881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3863881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3873804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3883804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3893804Ssaidi@eecs.umich.edu return tag; 3903804Ssaidi@eecs.umich.edu} 3913804Ssaidi@eecs.umich.edu 3923804Ssaidi@eecs.umich.edubool 3933804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3943804Ssaidi@eecs.umich.edu{ 3953804Ssaidi@eecs.umich.edu if (am) 3963804Ssaidi@eecs.umich.edu return true; 3973804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3983804Ssaidi@eecs.umich.edu return false; 3993804Ssaidi@eecs.umich.edu return true; 4003804Ssaidi@eecs.umich.edu} 4013804Ssaidi@eecs.umich.edu 4023804Ssaidi@eecs.umich.eduvoid 4034990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 4043804Ssaidi@eecs.umich.edu{ 4053804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4063804Ssaidi@eecs.umich.edu sfsr = 0x3; 4073804Ssaidi@eecs.umich.edu else 4083804Ssaidi@eecs.umich.edu sfsr = 1; 4093804Ssaidi@eecs.umich.edu 4103804Ssaidi@eecs.umich.edu if (write) 4113804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4123804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4133804Ssaidi@eecs.umich.edu if (se) 4143804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4153804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4163804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4173804Ssaidi@eecs.umich.edu} 4183804Ssaidi@eecs.umich.edu 4193826Ssaidi@eecs.umich.eduvoid 4204990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4213826Ssaidi@eecs.umich.edu{ 4223916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4233916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4243916Ssaidi@eecs.umich.edu 4254990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4263826Ssaidi@eecs.umich.edu} 4273804Ssaidi@eecs.umich.edu 4283804Ssaidi@eecs.umich.eduvoid 4294990Sgblack@eecs.umich.eduITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 4303804Ssaidi@eecs.umich.edu{ 4313811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4323811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4334990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4343804Ssaidi@eecs.umich.edu} 4353804Ssaidi@eecs.umich.edu 4363804Ssaidi@eecs.umich.eduvoid 4374990Sgblack@eecs.umich.eduDTB::writeSfsr(Addr a, bool write, ContextType ct, 4383804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4393804Ssaidi@eecs.umich.edu{ 4403811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4413811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4424990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4434990Sgblack@eecs.umich.edu sfar = a; 4443804Ssaidi@eecs.umich.edu} 4453804Ssaidi@eecs.umich.edu 4463804Ssaidi@eecs.umich.eduFault 4473804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4483804Ssaidi@eecs.umich.edu{ 4494172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4503833Ssaidi@eecs.umich.edu 4513836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4523836Ssaidi@eecs.umich.edu TlbEntry *e; 4533836Ssaidi@eecs.umich.edu 4543836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4553836Ssaidi@eecs.umich.edu 4563836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4573836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4583836Ssaidi@eecs.umich.edu 4593836Ssaidi@eecs.umich.edu // Be fast if we can! 4603836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4613836Ssaidi@eecs.umich.edu if (cacheEntry) { 4623836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4633836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4643836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4653836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4663836Ssaidi@eecs.umich.edu return NoFault; 4673836Ssaidi@eecs.umich.edu } 4683836Ssaidi@eecs.umich.edu } else { 4693836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4703836Ssaidi@eecs.umich.edu return NoFault; 4713836Ssaidi@eecs.umich.edu } 4723836Ssaidi@eecs.umich.edu } 4733836Ssaidi@eecs.umich.edu 4743833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4753833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4763833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4773833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4783833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4793833Ssaidi@eecs.umich.edu 4803833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4813833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4823833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4833804Ssaidi@eecs.umich.edu int context; 4843804Ssaidi@eecs.umich.edu ContextType ct; 4853804Ssaidi@eecs.umich.edu int asi; 4863804Ssaidi@eecs.umich.edu bool real = false; 4873804Ssaidi@eecs.umich.edu 4883833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4893833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4903811Ssaidi@eecs.umich.edu 4913804Ssaidi@eecs.umich.edu if (tl > 0) { 4923804Ssaidi@eecs.umich.edu asi = ASI_N; 4933804Ssaidi@eecs.umich.edu ct = Nucleus; 4943804Ssaidi@eecs.umich.edu context = 0; 4953804Ssaidi@eecs.umich.edu } else { 4963804Ssaidi@eecs.umich.edu asi = ASI_P; 4973804Ssaidi@eecs.umich.edu ct = Primary; 4983833Ssaidi@eecs.umich.edu context = pri_context; 4993804Ssaidi@eecs.umich.edu } 5003804Ssaidi@eecs.umich.edu 5013833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5023836Ssaidi@eecs.umich.edu cacheValid = true; 5033836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5043836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5053836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5063804Ssaidi@eecs.umich.edu return NoFault; 5073804Ssaidi@eecs.umich.edu } 5083804Ssaidi@eecs.umich.edu 5093836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5103836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5114990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 5123804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5133804Ssaidi@eecs.umich.edu } 5143804Ssaidi@eecs.umich.edu 5153804Ssaidi@eecs.umich.edu if (addr_mask) 5163804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5173804Ssaidi@eecs.umich.edu 5183804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5194990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 5203804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5213804Ssaidi@eecs.umich.edu } 5223804Ssaidi@eecs.umich.edu 5233833Ssaidi@eecs.umich.edu if (!lsu_im) { 5243836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5253804Ssaidi@eecs.umich.edu real = true; 5263804Ssaidi@eecs.umich.edu context = 0; 5273804Ssaidi@eecs.umich.edu } else { 5283804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5293804Ssaidi@eecs.umich.edu } 5303804Ssaidi@eecs.umich.edu 5313804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5324990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5333804Ssaidi@eecs.umich.edu if (real) 5343804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5353804Ssaidi@eecs.umich.edu else 5364997Sgblack@eecs.umich.edu#if FULL_SYSTEM 5373804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5384997Sgblack@eecs.umich.edu#else 5394997Sgblack@eecs.umich.edu return new FastInstructionAccessMMUMiss(req->getVaddr()); 5404997Sgblack@eecs.umich.edu#endif 5413804Ssaidi@eecs.umich.edu } 5423804Ssaidi@eecs.umich.edu 5433804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5443804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5454990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5464990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 5473804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5483804Ssaidi@eecs.umich.edu } 5493804Ssaidi@eecs.umich.edu 5503836Ssaidi@eecs.umich.edu // cache translation date for next translation 5513836Ssaidi@eecs.umich.edu cacheValid = true; 5523836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5533836Ssaidi@eecs.umich.edu cacheEntry = e; 5543836Ssaidi@eecs.umich.edu 5553826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5563836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5573836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5583804Ssaidi@eecs.umich.edu return NoFault; 5593804Ssaidi@eecs.umich.edu} 5603804Ssaidi@eecs.umich.edu 5613804Ssaidi@eecs.umich.edu 5623804Ssaidi@eecs.umich.edu 5633804Ssaidi@eecs.umich.eduFault 5643804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5653804Ssaidi@eecs.umich.edu{ 5663804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5674172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5683836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5693836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5703836Ssaidi@eecs.umich.edu ASI asi; 5713836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5723836Ssaidi@eecs.umich.edu bool implicit = false; 5733836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5744996Sgblack@eecs.umich.edu bool unaligned = (vaddr & size-1); 5753833Ssaidi@eecs.umich.edu 5763836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5773836Ssaidi@eecs.umich.edu vaddr, size, asi); 5783836Ssaidi@eecs.umich.edu 5793929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5803929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5813929Ssaidi@eecs.umich.edu freeList.size()); 5823836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5833836Ssaidi@eecs.umich.edu implicit = true; 5843836Ssaidi@eecs.umich.edu 5854996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5864996Sgblack@eecs.umich.edu // trap later 5874996Sgblack@eecs.umich.edu if (!unaligned) { 5884996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5894996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5904996Sgblack@eecs.umich.edu return NoFault; 5914996Sgblack@eecs.umich.edu } 5924996Sgblack@eecs.umich.edu 5934996Sgblack@eecs.umich.edu // Be fast if we can! 5944996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5954996Sgblack@eecs.umich.edu 5964996Sgblack@eecs.umich.edu 5974996Sgblack@eecs.umich.edu 5984996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5994996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 6004996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6014996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 6024996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6034996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6044996Sgblack@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6054996Sgblack@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6064996Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6074996Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6084996Sgblack@eecs.umich.edu return NoFault; 6094996Sgblack@eecs.umich.edu } // if matched 6104996Sgblack@eecs.umich.edu } // if cache entry valid 6114996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 6124996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 6134996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6144996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 6154996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6164996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 6174996Sgblack@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6184996Sgblack@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6194996Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6204996Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6214996Sgblack@eecs.umich.edu return NoFault; 6224996Sgblack@eecs.umich.edu } // if matched 6234996Sgblack@eecs.umich.edu } // if cache entry valid 6244996Sgblack@eecs.umich.edu } 6253836Ssaidi@eecs.umich.edu } 6263836Ssaidi@eecs.umich.edu 6273833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6283833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6293833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6303833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6313833Ssaidi@eecs.umich.edu 6323833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6333833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6343833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6353916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6363833Ssaidi@eecs.umich.edu 6373804Ssaidi@eecs.umich.edu bool real = false; 6383832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6393832Ssaidi@eecs.umich.edu int context = 0; 6403804Ssaidi@eecs.umich.edu 6413804Ssaidi@eecs.umich.edu TlbEntry *e; 6423804Ssaidi@eecs.umich.edu 6433833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6443833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6453804Ssaidi@eecs.umich.edu 6463804Ssaidi@eecs.umich.edu if (implicit) { 6473804Ssaidi@eecs.umich.edu if (tl > 0) { 6483804Ssaidi@eecs.umich.edu asi = ASI_N; 6493804Ssaidi@eecs.umich.edu ct = Nucleus; 6503804Ssaidi@eecs.umich.edu context = 0; 6513804Ssaidi@eecs.umich.edu } else { 6523804Ssaidi@eecs.umich.edu asi = ASI_P; 6533804Ssaidi@eecs.umich.edu ct = Primary; 6543833Ssaidi@eecs.umich.edu context = pri_context; 6553804Ssaidi@eecs.umich.edu } 6563910Ssaidi@eecs.umich.edu } else { 6573804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6583910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6593804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6604990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6613804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6623804Ssaidi@eecs.umich.edu } 6633910Ssaidi@eecs.umich.edu 6643910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6654990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 6663804Ssaidi@eecs.umich.edu return new DataAccessException; 6673804Ssaidi@eecs.umich.edu } 6683804Ssaidi@eecs.umich.edu 6693910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6703910Ssaidi@eecs.umich.edu context = pri_context; 6713910Ssaidi@eecs.umich.edu ct = Primary; 6723910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6733910Ssaidi@eecs.umich.edu context = sec_context; 6743910Ssaidi@eecs.umich.edu ct = Secondary; 6753910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6763910Ssaidi@eecs.umich.edu ct = Nucleus; 6773910Ssaidi@eecs.umich.edu context = 0; 6783910Ssaidi@eecs.umich.edu } else { // ???? 6793910Ssaidi@eecs.umich.edu ct = Primary; 6803910Ssaidi@eecs.umich.edu context = pri_context; 6813910Ssaidi@eecs.umich.edu } 6823902Ssaidi@eecs.umich.edu } 6833804Ssaidi@eecs.umich.edu 6843926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6853804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6863804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6874989Sgblack@eecs.umich.edu 6884989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6894989Sgblack@eecs.umich.edu //load differs from a regular one, other than what happens concerning 6904989Sgblack@eecs.umich.edu //nfo and e bits in the TTE 6914989Sgblack@eecs.umich.edu// if (AsiIsNoFault(asi)) 6924989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6933856Ssaidi@eecs.umich.edu 6943804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6953804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6964103Ssaidi@eecs.umich.edu 6974191Ssaidi@eecs.umich.edu if (AsiIsCmt(asi)) 6984191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6994191Ssaidi@eecs.umich.edu 7003824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 7014103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 7023804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 7033804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 7043804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 7053804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 7063824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 7073824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 7083825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 7093825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 7103823Ssaidi@eecs.umich.edu 7113926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 7124989Sgblack@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 7133823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7143804Ssaidi@eecs.umich.edu } 7153804Ssaidi@eecs.umich.edu 7163826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7174996Sgblack@eecs.umich.edu if (unaligned) { 7184990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 7193826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7203826Ssaidi@eecs.umich.edu } 7213826Ssaidi@eecs.umich.edu 7223826Ssaidi@eecs.umich.edu if (addr_mask) 7233826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7243826Ssaidi@eecs.umich.edu 7253826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7264990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 7273826Ssaidi@eecs.umich.edu return new DataAccessException; 7283826Ssaidi@eecs.umich.edu } 7293826Ssaidi@eecs.umich.edu 7303826Ssaidi@eecs.umich.edu 7313910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7323804Ssaidi@eecs.umich.edu real = true; 7333804Ssaidi@eecs.umich.edu context = 0; 7343804Ssaidi@eecs.umich.edu }; 7353804Ssaidi@eecs.umich.edu 7363804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7373836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7383804Ssaidi@eecs.umich.edu return NoFault; 7393804Ssaidi@eecs.umich.edu } 7403804Ssaidi@eecs.umich.edu 7413836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7423804Ssaidi@eecs.umich.edu 7433804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7444990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7453811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7463804Ssaidi@eecs.umich.edu if (real) 7473804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7483804Ssaidi@eecs.umich.edu else 7494997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7503804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7514997Sgblack@eecs.umich.edu#else 7524997Sgblack@eecs.umich.edu return new FastDataAccessMMUMiss(req->getVaddr()); 7534997Sgblack@eecs.umich.edu#endif 7543804Ssaidi@eecs.umich.edu 7553804Ssaidi@eecs.umich.edu } 7563804Ssaidi@eecs.umich.edu 7573928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7584990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7594990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7603928Ssaidi@eecs.umich.edu return new DataAccessException; 7613928Ssaidi@eecs.umich.edu } 7623804Ssaidi@eecs.umich.edu 7633804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7644990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7654990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7663804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7673804Ssaidi@eecs.umich.edu } 7683804Ssaidi@eecs.umich.edu 7693804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7704990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7714990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7723804Ssaidi@eecs.umich.edu return new DataAccessException; 7733804Ssaidi@eecs.umich.edu } 7743804Ssaidi@eecs.umich.edu 7753928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7764990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7774990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7783928Ssaidi@eecs.umich.edu return new DataAccessException; 7793928Ssaidi@eecs.umich.edu } 7803928Ssaidi@eecs.umich.edu 7813928Ssaidi@eecs.umich.edu 7824090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7833804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7843804Ssaidi@eecs.umich.edu 7853836Ssaidi@eecs.umich.edu // cache translation date for next translation 7863836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7873881Ssaidi@eecs.umich.edu if (!cacheValid) { 7883881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7893881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7903881Ssaidi@eecs.umich.edu } 7913881Ssaidi@eecs.umich.edu 7923836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7933836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7943836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7953836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7963836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7973836Ssaidi@eecs.umich.edu if (implicit) 7983836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7993836Ssaidi@eecs.umich.edu } 8003881Ssaidi@eecs.umich.edu cacheValid = true; 8013826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 8023836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 8033836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 8043804Ssaidi@eecs.umich.edu return NoFault; 8054103Ssaidi@eecs.umich.edu 8063806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 8074103Ssaidi@eecs.umich.eduhandleIntRegAccess: 8084103Ssaidi@eecs.umich.edu if (!hpriv) { 8094990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8104103Ssaidi@eecs.umich.edu if (priv) 8114103Ssaidi@eecs.umich.edu return new DataAccessException; 8124103Ssaidi@eecs.umich.edu else 8134103Ssaidi@eecs.umich.edu return new PrivilegedAction; 8144103Ssaidi@eecs.umich.edu } 8154103Ssaidi@eecs.umich.edu 8164103Ssaidi@eecs.umich.edu if (asi == ASI_SWVR_UDB_INTR_W && !write || 8174103Ssaidi@eecs.umich.edu asi == ASI_SWVR_UDB_INTR_R && write) { 8184990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8194103Ssaidi@eecs.umich.edu return new DataAccessException; 8204103Ssaidi@eecs.umich.edu } 8214103Ssaidi@eecs.umich.edu 8224103Ssaidi@eecs.umich.edu goto regAccessOk; 8234103Ssaidi@eecs.umich.edu 8243804Ssaidi@eecs.umich.edu 8253806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8263806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8274990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8283806Ssaidi@eecs.umich.edu return new DataAccessException; 8293806Ssaidi@eecs.umich.edu } 8303824Ssaidi@eecs.umich.edu goto regAccessOk; 8313824Ssaidi@eecs.umich.edu 8323824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8333824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8344990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8353824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8363824Ssaidi@eecs.umich.edu } 8373881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 8384990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8393824Ssaidi@eecs.umich.edu return new DataAccessException; 8403824Ssaidi@eecs.umich.edu } 8413824Ssaidi@eecs.umich.edu goto regAccessOk; 8423824Ssaidi@eecs.umich.edu 8433825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8443825Ssaidi@eecs.umich.edu if (!hpriv) { 8454990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8464070Ssaidi@eecs.umich.edu if (priv) 8473825Ssaidi@eecs.umich.edu return new DataAccessException; 8484070Ssaidi@eecs.umich.edu else 8493825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8503825Ssaidi@eecs.umich.edu } 8513825Ssaidi@eecs.umich.edu goto regAccessOk; 8523825Ssaidi@eecs.umich.edu 8533825Ssaidi@eecs.umich.edu 8543824Ssaidi@eecs.umich.eduregAccessOk: 8553804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8563811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8573806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8583806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8593806Ssaidi@eecs.umich.edu return NoFault; 8603804Ssaidi@eecs.umich.edu}; 8613804Ssaidi@eecs.umich.edu 8624997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8634997Sgblack@eecs.umich.edu 8643806Ssaidi@eecs.umich.eduTick 8653806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8663806Ssaidi@eecs.umich.edu{ 8673823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8683823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8694070Ssaidi@eecs.umich.edu uint64_t temp; 8703823Ssaidi@eecs.umich.edu 8713823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8723823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8733823Ssaidi@eecs.umich.edu 8744990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 8754990Sgblack@eecs.umich.edu 8763823Ssaidi@eecs.umich.edu switch (asi) { 8773823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8783823Ssaidi@eecs.umich.edu assert(va == 0); 8794172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8803823Ssaidi@eecs.umich.edu break; 8813823Ssaidi@eecs.umich.edu case ASI_MMU: 8823823Ssaidi@eecs.umich.edu switch (va) { 8833823Ssaidi@eecs.umich.edu case 0x8: 8844172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8853823Ssaidi@eecs.umich.edu break; 8863823Ssaidi@eecs.umich.edu case 0x10: 8874172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8883823Ssaidi@eecs.umich.edu break; 8893823Ssaidi@eecs.umich.edu default: 8903823Ssaidi@eecs.umich.edu goto doMmuReadError; 8913823Ssaidi@eecs.umich.edu } 8923823Ssaidi@eecs.umich.edu break; 8933824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8944172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8953824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8963824Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 8994990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9034990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9074990Sgblack@eecs.umich.edu pkt->set(c0_config); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9114990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9154990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9194990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9234990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9274990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9314990Sgblack@eecs.umich.edu pkt->set(cx_config); 9323823Ssaidi@eecs.umich.edu break; 9333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9343823Ssaidi@eecs.umich.edu assert(va == 0); 9354990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9363823Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9383823Ssaidi@eecs.umich.edu assert(va == 0); 9394990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9403823Ssaidi@eecs.umich.edu break; 9413823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9423823Ssaidi@eecs.umich.edu assert(va == 0); 9434990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9443823Ssaidi@eecs.umich.edu break; 9453826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9463912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9473826Ssaidi@eecs.umich.edu break; 9483823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9493823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9504172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9513823Ssaidi@eecs.umich.edu break; 9523826Ssaidi@eecs.umich.edu case ASI_IMMU: 9533826Ssaidi@eecs.umich.edu switch (va) { 9543833Ssaidi@eecs.umich.edu case 0x0: 9554990Sgblack@eecs.umich.edu temp = itb->tag_access; 9563833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9573833Ssaidi@eecs.umich.edu break; 9583906Ssaidi@eecs.umich.edu case 0x18: 9594990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9603906Ssaidi@eecs.umich.edu break; 9613826Ssaidi@eecs.umich.edu case 0x30: 9624990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9633826Ssaidi@eecs.umich.edu break; 9643826Ssaidi@eecs.umich.edu default: 9653826Ssaidi@eecs.umich.edu goto doMmuReadError; 9663826Ssaidi@eecs.umich.edu } 9673826Ssaidi@eecs.umich.edu break; 9683823Ssaidi@eecs.umich.edu case ASI_DMMU: 9693823Ssaidi@eecs.umich.edu switch (va) { 9703833Ssaidi@eecs.umich.edu case 0x0: 9714990Sgblack@eecs.umich.edu temp = tag_access; 9723833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9733833Ssaidi@eecs.umich.edu break; 9743906Ssaidi@eecs.umich.edu case 0x18: 9754990Sgblack@eecs.umich.edu pkt->set(sfsr); 9763906Ssaidi@eecs.umich.edu break; 9773906Ssaidi@eecs.umich.edu case 0x20: 9784990Sgblack@eecs.umich.edu pkt->set(sfar); 9793906Ssaidi@eecs.umich.edu break; 9803826Ssaidi@eecs.umich.edu case 0x30: 9814990Sgblack@eecs.umich.edu pkt->set(tag_access); 9823826Ssaidi@eecs.umich.edu break; 9833823Ssaidi@eecs.umich.edu case 0x80: 9844172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9853823Ssaidi@eecs.umich.edu break; 9863823Ssaidi@eecs.umich.edu default: 9873823Ssaidi@eecs.umich.edu goto doMmuReadError; 9883823Ssaidi@eecs.umich.edu } 9893823Ssaidi@eecs.umich.edu break; 9903833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9914070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9924990Sgblack@eecs.umich.edu tag_access, 9934990Sgblack@eecs.umich.edu c0_tsb_ps0, 9944990Sgblack@eecs.umich.edu c0_config, 9954990Sgblack@eecs.umich.edu cx_tsb_ps0, 9964990Sgblack@eecs.umich.edu cx_config)); 9973833Ssaidi@eecs.umich.edu break; 9983833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9994070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10004990Sgblack@eecs.umich.edu tag_access, 10014990Sgblack@eecs.umich.edu c0_tsb_ps1, 10024990Sgblack@eecs.umich.edu c0_config, 10034990Sgblack@eecs.umich.edu cx_tsb_ps1, 10044990Sgblack@eecs.umich.edu cx_config)); 10053833Ssaidi@eecs.umich.edu break; 10063899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10074070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10084990Sgblack@eecs.umich.edu itb->tag_access, 10094990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10104990Sgblack@eecs.umich.edu itb->c0_config, 10114990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10124990Sgblack@eecs.umich.edu itb->cx_config)); 10133899Ssaidi@eecs.umich.edu break; 10143899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10154070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10164990Sgblack@eecs.umich.edu itb->tag_access, 10174990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10184990Sgblack@eecs.umich.edu itb->c0_config, 10194990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10204990Sgblack@eecs.umich.edu itb->cx_config)); 10213899Ssaidi@eecs.umich.edu break; 10224103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10234103Ssaidi@eecs.umich.edu pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10244103Ssaidi@eecs.umich.edu break; 10254103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10264103Ssaidi@eecs.umich.edu temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10274103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 10284103Ssaidi@eecs.umich.edu pkt->set(temp); 10294103Ssaidi@eecs.umich.edu break; 10303823Ssaidi@eecs.umich.edu default: 10313823Ssaidi@eecs.umich.edudoMmuReadError: 10323823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10333823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10343823Ssaidi@eecs.umich.edu } 10354870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10365100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 10373806Ssaidi@eecs.umich.edu} 10383806Ssaidi@eecs.umich.edu 10393806Ssaidi@eecs.umich.eduTick 10403806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10413806Ssaidi@eecs.umich.edu{ 10423823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10433823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10443823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10453823Ssaidi@eecs.umich.edu 10463826Ssaidi@eecs.umich.edu Addr ta_insert; 10473826Ssaidi@eecs.umich.edu Addr va_insert; 10483826Ssaidi@eecs.umich.edu Addr ct_insert; 10493826Ssaidi@eecs.umich.edu int part_insert; 10503826Ssaidi@eecs.umich.edu int entry_insert = -1; 10513826Ssaidi@eecs.umich.edu bool real_insert; 10523863Ssaidi@eecs.umich.edu bool ignore; 10533863Ssaidi@eecs.umich.edu int part_id; 10543863Ssaidi@eecs.umich.edu int ctx_id; 10553826Ssaidi@eecs.umich.edu PageTableEntry pte; 10563826Ssaidi@eecs.umich.edu 10573825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10583823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10593823Ssaidi@eecs.umich.edu 10604990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 10614990Sgblack@eecs.umich.edu 10623823Ssaidi@eecs.umich.edu switch (asi) { 10633823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10643823Ssaidi@eecs.umich.edu assert(va == 0); 10654172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10663823Ssaidi@eecs.umich.edu break; 10673823Ssaidi@eecs.umich.edu case ASI_MMU: 10683823Ssaidi@eecs.umich.edu switch (va) { 10693823Ssaidi@eecs.umich.edu case 0x8: 10704172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10713823Ssaidi@eecs.umich.edu break; 10723823Ssaidi@eecs.umich.edu case 0x10: 10734172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10743823Ssaidi@eecs.umich.edu break; 10753823Ssaidi@eecs.umich.edu default: 10763823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10773823Ssaidi@eecs.umich.edu } 10783823Ssaidi@eecs.umich.edu break; 10793824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10803825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10814172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10823824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10833824Ssaidi@eecs.umich.edu break; 10843823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10853823Ssaidi@eecs.umich.edu assert(va == 0); 10864990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10873823Ssaidi@eecs.umich.edu break; 10883823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10893823Ssaidi@eecs.umich.edu assert(va == 0); 10904990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10913823Ssaidi@eecs.umich.edu break; 10923823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10933823Ssaidi@eecs.umich.edu assert(va == 0); 10944990Sgblack@eecs.umich.edu c0_config = data; 10953823Ssaidi@eecs.umich.edu break; 10963823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10973823Ssaidi@eecs.umich.edu assert(va == 0); 10984990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 10993823Ssaidi@eecs.umich.edu break; 11003823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11013823Ssaidi@eecs.umich.edu assert(va == 0); 11024990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11033823Ssaidi@eecs.umich.edu break; 11043823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11053823Ssaidi@eecs.umich.edu assert(va == 0); 11064990Sgblack@eecs.umich.edu itb->c0_config = data; 11073823Ssaidi@eecs.umich.edu break; 11083823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11093823Ssaidi@eecs.umich.edu assert(va == 0); 11104990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11113823Ssaidi@eecs.umich.edu break; 11123823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11133823Ssaidi@eecs.umich.edu assert(va == 0); 11144990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11153823Ssaidi@eecs.umich.edu break; 11163823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11173823Ssaidi@eecs.umich.edu assert(va == 0); 11184990Sgblack@eecs.umich.edu cx_config = data; 11193823Ssaidi@eecs.umich.edu break; 11203823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11213823Ssaidi@eecs.umich.edu assert(va == 0); 11224990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11233823Ssaidi@eecs.umich.edu break; 11243823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11253823Ssaidi@eecs.umich.edu assert(va == 0); 11264990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11273823Ssaidi@eecs.umich.edu break; 11283823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11293823Ssaidi@eecs.umich.edu assert(va == 0); 11304990Sgblack@eecs.umich.edu itb->cx_config = data; 11313823Ssaidi@eecs.umich.edu break; 11323825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11333825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11343825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11353825Ssaidi@eecs.umich.edu break; 11363823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11373823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11384172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11393823Ssaidi@eecs.umich.edu break; 11403826Ssaidi@eecs.umich.edu case ASI_IMMU: 11413826Ssaidi@eecs.umich.edu switch (va) { 11423906Ssaidi@eecs.umich.edu case 0x18: 11434990Sgblack@eecs.umich.edu itb->sfsr = data; 11443906Ssaidi@eecs.umich.edu break; 11453826Ssaidi@eecs.umich.edu case 0x30: 11463916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11474990Sgblack@eecs.umich.edu itb->tag_access = data; 11483826Ssaidi@eecs.umich.edu break; 11493826Ssaidi@eecs.umich.edu default: 11503826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11513826Ssaidi@eecs.umich.edu } 11523826Ssaidi@eecs.umich.edu break; 11533826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11543826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11553826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11563826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11574990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11583826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11593826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11604172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11613826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11623826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11633826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11643826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11653826Ssaidi@eecs.umich.edu pte, entry_insert); 11663826Ssaidi@eecs.umich.edu break; 11673826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11683826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11693826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11703826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11714990Sgblack@eecs.umich.edu ta_insert = tag_access; 11723826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11733826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11744172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11753826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11763826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11773826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11783826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11793826Ssaidi@eecs.umich.edu break; 11803863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11813863Ssaidi@eecs.umich.edu ignore = false; 11823863Ssaidi@eecs.umich.edu ctx_id = -1; 11834172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11843863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11853863Ssaidi@eecs.umich.edu case 0: 11864172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11873863Ssaidi@eecs.umich.edu break; 11883863Ssaidi@eecs.umich.edu case 1: 11893863Ssaidi@eecs.umich.edu ignore = true; 11903863Ssaidi@eecs.umich.edu break; 11913863Ssaidi@eecs.umich.edu case 3: 11923863Ssaidi@eecs.umich.edu ctx_id = 0; 11933863Ssaidi@eecs.umich.edu break; 11943863Ssaidi@eecs.umich.edu default: 11953863Ssaidi@eecs.umich.edu ignore = true; 11963863Ssaidi@eecs.umich.edu } 11973863Ssaidi@eecs.umich.edu 11983863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11993863Ssaidi@eecs.umich.edu case 0: // demap page 12003863Ssaidi@eecs.umich.edu if (!ignore) 12013863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 12023863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 12033863Ssaidi@eecs.umich.edu break; 12043863Ssaidi@eecs.umich.edu case 1: //demap context 12053863Ssaidi@eecs.umich.edu if (!ignore) 12063863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 12073863Ssaidi@eecs.umich.edu break; 12083863Ssaidi@eecs.umich.edu case 2: 12093863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12103863Ssaidi@eecs.umich.edu break; 12113863Ssaidi@eecs.umich.edu default: 12123863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12133863Ssaidi@eecs.umich.edu } 12143863Ssaidi@eecs.umich.edu break; 12153823Ssaidi@eecs.umich.edu case ASI_DMMU: 12163823Ssaidi@eecs.umich.edu switch (va) { 12173906Ssaidi@eecs.umich.edu case 0x18: 12184990Sgblack@eecs.umich.edu sfsr = data; 12193906Ssaidi@eecs.umich.edu break; 12203826Ssaidi@eecs.umich.edu case 0x30: 12213916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12224990Sgblack@eecs.umich.edu tag_access = data; 12233826Ssaidi@eecs.umich.edu break; 12243823Ssaidi@eecs.umich.edu case 0x80: 12254172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12263823Ssaidi@eecs.umich.edu break; 12273823Ssaidi@eecs.umich.edu default: 12283823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12293823Ssaidi@eecs.umich.edu } 12303823Ssaidi@eecs.umich.edu break; 12313863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12323863Ssaidi@eecs.umich.edu ignore = false; 12333863Ssaidi@eecs.umich.edu ctx_id = -1; 12344172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12353863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12363863Ssaidi@eecs.umich.edu case 0: 12374172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12383863Ssaidi@eecs.umich.edu break; 12393863Ssaidi@eecs.umich.edu case 1: 12404172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12413863Ssaidi@eecs.umich.edu break; 12423863Ssaidi@eecs.umich.edu case 3: 12433863Ssaidi@eecs.umich.edu ctx_id = 0; 12443863Ssaidi@eecs.umich.edu break; 12453863Ssaidi@eecs.umich.edu default: 12463863Ssaidi@eecs.umich.edu ignore = true; 12473863Ssaidi@eecs.umich.edu } 12483863Ssaidi@eecs.umich.edu 12493863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12503863Ssaidi@eecs.umich.edu case 0: // demap page 12513863Ssaidi@eecs.umich.edu if (!ignore) 12523863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12533863Ssaidi@eecs.umich.edu break; 12543863Ssaidi@eecs.umich.edu case 1: //demap context 12553863Ssaidi@eecs.umich.edu if (!ignore) 12563863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12573863Ssaidi@eecs.umich.edu break; 12583863Ssaidi@eecs.umich.edu case 2: 12593863Ssaidi@eecs.umich.edu demapAll(part_id); 12603863Ssaidi@eecs.umich.edu break; 12613863Ssaidi@eecs.umich.edu default: 12623863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12633863Ssaidi@eecs.umich.edu } 12643863Ssaidi@eecs.umich.edu break; 12654103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12664103Ssaidi@eecs.umich.edu int msb; 12674103Ssaidi@eecs.umich.edu // clear all the interrupts that aren't set in the write 12684103Ssaidi@eecs.umich.edu while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) { 12694103Ssaidi@eecs.umich.edu msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data); 12704103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); 12714103Ssaidi@eecs.umich.edu } 12724103Ssaidi@eecs.umich.edu break; 12734103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12744103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12754103Ssaidi@eecs.umich.edu post_interrupt(bits(data,5,0),0); 12764103Ssaidi@eecs.umich.edu break; 12774103Ssaidi@eecs.umich.edu default: 12783823Ssaidi@eecs.umich.edudoMmuWriteError: 12793823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12803823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12813823Ssaidi@eecs.umich.edu } 12824870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12835100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 12843806Ssaidi@eecs.umich.edu} 12853806Ssaidi@eecs.umich.edu 12864997Sgblack@eecs.umich.edu#endif 12874997Sgblack@eecs.umich.edu 12883804Ssaidi@eecs.umich.eduvoid 12894070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12904070Ssaidi@eecs.umich.edu{ 12914070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12924990Sgblack@eecs.umich.edu ITB * itb = tc->getITBPtr(); 12934070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12944990Sgblack@eecs.umich.edu c0_tsb_ps0, 12954990Sgblack@eecs.umich.edu c0_config, 12964990Sgblack@eecs.umich.edu cx_tsb_ps0, 12974990Sgblack@eecs.umich.edu cx_config); 12984070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12994990Sgblack@eecs.umich.edu c0_tsb_ps1, 13004990Sgblack@eecs.umich.edu c0_config, 13014990Sgblack@eecs.umich.edu cx_tsb_ps1, 13024990Sgblack@eecs.umich.edu cx_config); 13034070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13044990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13054990Sgblack@eecs.umich.edu itb->c0_config, 13064990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13074990Sgblack@eecs.umich.edu itb->cx_config); 13084070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13094990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13104990Sgblack@eecs.umich.edu itb->c0_config, 13114990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13124990Sgblack@eecs.umich.edu itb->cx_config); 13134070Ssaidi@eecs.umich.edu} 13144070Ssaidi@eecs.umich.edu 13154070Ssaidi@eecs.umich.edu 13164070Ssaidi@eecs.umich.edu 13174070Ssaidi@eecs.umich.edu 13184070Ssaidi@eecs.umich.edu 13194070Ssaidi@eecs.umich.eduuint64_t 13204070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13214070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13224070Ssaidi@eecs.umich.edu{ 13234070Ssaidi@eecs.umich.edu uint64_t tsb; 13244070Ssaidi@eecs.umich.edu uint64_t config; 13254070Ssaidi@eecs.umich.edu 13264070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13274070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13284070Ssaidi@eecs.umich.edu config = c0_config; 13294070Ssaidi@eecs.umich.edu } else { 13304070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13314070Ssaidi@eecs.umich.edu config = cX_config; 13324070Ssaidi@eecs.umich.edu } 13334070Ssaidi@eecs.umich.edu 13344070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13354070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13364070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13374070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13384070Ssaidi@eecs.umich.edu 13394070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13404070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13414070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13424070Ssaidi@eecs.umich.edu 13434070Ssaidi@eecs.umich.edu return ptr; 13444070Ssaidi@eecs.umich.edu} 13454070Ssaidi@eecs.umich.edu 13464070Ssaidi@eecs.umich.edu 13474070Ssaidi@eecs.umich.eduvoid 13483804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13493804Ssaidi@eecs.umich.edu{ 13504000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13514000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13524000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13534000Ssaidi@eecs.umich.edu 13544000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13554000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13564000Ssaidi@eecs.umich.edu int cntr = 0; 13574000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13584000Ssaidi@eecs.umich.edu i = freeList.begin(); 13594000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13604000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13614000Ssaidi@eecs.umich.edu i++; 13624000Ssaidi@eecs.umich.edu } 13634000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13644000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13654000Ssaidi@eecs.umich.edu 13664000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13674000Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13684000Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13694000Ssaidi@eecs.umich.edu } 13704990Sgblack@eecs.umich.edu 13714990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13724990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13734990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13744990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13754990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13764990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13774990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13784990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 13793804Ssaidi@eecs.umich.edu} 13803804Ssaidi@eecs.umich.edu 13813804Ssaidi@eecs.umich.eduvoid 13823804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13833804Ssaidi@eecs.umich.edu{ 13844000Ssaidi@eecs.umich.edu int oldSize; 13854000Ssaidi@eecs.umich.edu 13864000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13874000Ssaidi@eecs.umich.edu if (oldSize != size) 13884000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13894000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13904000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13914000Ssaidi@eecs.umich.edu 13924000Ssaidi@eecs.umich.edu int cntr; 13934000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13944000Ssaidi@eecs.umich.edu 13954000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13964000Ssaidi@eecs.umich.edu freeList.clear(); 13974000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13984000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13994000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 14004000Ssaidi@eecs.umich.edu 14014000Ssaidi@eecs.umich.edu lookupTable.clear(); 14024000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 14034000Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 14044000Ssaidi@eecs.umich.edu if (tlb[x].valid) 14054000Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14064000Ssaidi@eecs.umich.edu 14074000Ssaidi@eecs.umich.edu } 14084990Sgblack@eecs.umich.edu 14094990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14104990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14114990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14124990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14134990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14144990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14154990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14164990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14174990Sgblack@eecs.umich.edu} 14184990Sgblack@eecs.umich.edu 14194990Sgblack@eecs.umich.eduvoid 14204990Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 14214990Sgblack@eecs.umich.edu{ 14224990Sgblack@eecs.umich.edu TLB::serialize(os); 14234990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfar); 14244990Sgblack@eecs.umich.edu} 14254990Sgblack@eecs.umich.edu 14264990Sgblack@eecs.umich.eduvoid 14274990Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 14284990Sgblack@eecs.umich.edu{ 14294990Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 14304990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14313804Ssaidi@eecs.umich.edu} 14323804Ssaidi@eecs.umich.edu 14334088Sbinkertn@umich.edu/* end namespace SparcISA */ } 14344088Sbinkertn@umich.edu 14354762Snate@binkert.orgSparcISA::ITB * 14364762Snate@binkert.orgSparcITBParams::create() 14373804Ssaidi@eecs.umich.edu{ 14385034Smilesck@eecs.umich.edu return new SparcISA::ITB(this); 14393804Ssaidi@eecs.umich.edu} 14403804Ssaidi@eecs.umich.edu 14414762Snate@binkert.orgSparcISA::DTB * 14424762Snate@binkert.orgSparcDTBParams::create() 14433804Ssaidi@eecs.umich.edu{ 14445034Smilesck@eecs.umich.edu return new SparcISA::DTB(this); 14453804Ssaidi@eecs.umich.edu} 1446