tlb.cc revision 4989
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 424762Snate@binkert.org#include "params/SparcDTB.hh" 434762Snate@binkert.org#include "params/SparcITB.hh" 444103Ssaidi@eecs.umich.edu#include "sim/system.hh" 453569Sgblack@eecs.umich.edu 463804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 473804Ssaidi@eecs.umich.edu * */ 484088Sbinkertn@umich.edunamespace SparcISA { 493569Sgblack@eecs.umich.edu 503804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 513881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 523881Ssaidi@eecs.umich.edu cacheValid(false) 533804Ssaidi@eecs.umich.edu{ 543804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 553804Ssaidi@eecs.umich.edu if (size > 64) 563804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 573569Sgblack@eecs.umich.edu 583804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 593918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 603881Ssaidi@eecs.umich.edu 613881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 623881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 633804Ssaidi@eecs.umich.edu} 643569Sgblack@eecs.umich.edu 653804Ssaidi@eecs.umich.eduvoid 663804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 673804Ssaidi@eecs.umich.edu{ 683804Ssaidi@eecs.umich.edu MapIter i; 693881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 703804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 713804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 723804Ssaidi@eecs.umich.edu t->used = false; 733804Ssaidi@eecs.umich.edu usedEntries--; 743804Ssaidi@eecs.umich.edu } 753804Ssaidi@eecs.umich.edu } 763804Ssaidi@eecs.umich.edu} 773569Sgblack@eecs.umich.edu 783569Sgblack@eecs.umich.edu 793804Ssaidi@eecs.umich.eduvoid 803804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 813826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 823804Ssaidi@eecs.umich.edu{ 833569Sgblack@eecs.umich.edu 843569Sgblack@eecs.umich.edu 853804Ssaidi@eecs.umich.edu MapIter i; 863826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 873907Ssaidi@eecs.umich.edu// TlbRange tr; 883826Ssaidi@eecs.umich.edu int x; 893811Ssaidi@eecs.umich.edu 903836Ssaidi@eecs.umich.edu cacheValid = false; 913915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 923907Ssaidi@eecs.umich.edu /* tr.va = va; 933881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 943881Ssaidi@eecs.umich.edu tr.contextId = context_id; 953881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 963881Ssaidi@eecs.umich.edu tr.real = real; 973907Ssaidi@eecs.umich.edu*/ 983881Ssaidi@eecs.umich.edu 993881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1003881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1013881Ssaidi@eecs.umich.edu 1023881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1033907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1043907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1053907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1063907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1073907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1083907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1093907Ssaidi@eecs.umich.edu { 1103907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1113907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1123907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1133907Ssaidi@eecs.umich.edu 1143907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1153907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1163907Ssaidi@eecs.umich.edu tlb[x].used = false; 1173907Ssaidi@eecs.umich.edu usedEntries--; 1183907Ssaidi@eecs.umich.edu } 1193907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1203907Ssaidi@eecs.umich.edu } 1213907Ssaidi@eecs.umich.edu } 1223907Ssaidi@eecs.umich.edu } 1233907Ssaidi@eecs.umich.edu 1243907Ssaidi@eecs.umich.edu 1253907Ssaidi@eecs.umich.edu/* 1263881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1273881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1283881Ssaidi@eecs.umich.edu i->second->valid = false; 1293881Ssaidi@eecs.umich.edu if (i->second->used) { 1303881Ssaidi@eecs.umich.edu i->second->used = false; 1313881Ssaidi@eecs.umich.edu usedEntries--; 1323881Ssaidi@eecs.umich.edu } 1333881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1343881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1353881Ssaidi@eecs.umich.edu i->second); 1363881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1373881Ssaidi@eecs.umich.edu } 1383907Ssaidi@eecs.umich.edu*/ 1393811Ssaidi@eecs.umich.edu 1403826Ssaidi@eecs.umich.edu if (entry != -1) { 1413826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1423826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1433826Ssaidi@eecs.umich.edu } else { 1443881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1453881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1463881Ssaidi@eecs.umich.edu } else { 1473881Ssaidi@eecs.umich.edu x = lastReplaced; 1483881Ssaidi@eecs.umich.edu do { 1493881Ssaidi@eecs.umich.edu ++x; 1503881Ssaidi@eecs.umich.edu if (x == size) 1513881Ssaidi@eecs.umich.edu x = 0; 1523881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1533881Ssaidi@eecs.umich.edu goto insertAllLocked; 1543881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1553881Ssaidi@eecs.umich.edu lastReplaced = x; 1563881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1573881Ssaidi@eecs.umich.edu } 1583881Ssaidi@eecs.umich.edu /* 1593826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1603826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1613826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1623826Ssaidi@eecs.umich.edu break; 1633826Ssaidi@eecs.umich.edu } 1643881Ssaidi@eecs.umich.edu }*/ 1653569Sgblack@eecs.umich.edu } 1663569Sgblack@eecs.umich.edu 1673881Ssaidi@eecs.umich.eduinsertAllLocked: 1683804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1693881Ssaidi@eecs.umich.edu if (!new_entry) { 1703826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1713881Ssaidi@eecs.umich.edu } 1723881Ssaidi@eecs.umich.edu 1733881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1743907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1753907Ssaidi@eecs.umich.edu usedEntries--; 1763929Ssaidi@eecs.umich.edu if (new_entry->valid) 1773929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1783907Ssaidi@eecs.umich.edu 1793907Ssaidi@eecs.umich.edu 1803804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1813804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1823881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1833804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1843804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1853804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1863804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1873804Ssaidi@eecs.umich.edu new_entry->used = true;; 1883804Ssaidi@eecs.umich.edu new_entry->valid = true; 1893804Ssaidi@eecs.umich.edu usedEntries++; 1903569Sgblack@eecs.umich.edu 1913569Sgblack@eecs.umich.edu 1923569Sgblack@eecs.umich.edu 1933863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1943863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1953804Ssaidi@eecs.umich.edu 1963804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1973804Ssaidi@eecs.umich.edu // one we just inserted 1983804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1993804Ssaidi@eecs.umich.edu clearUsedBits(); 2003804Ssaidi@eecs.umich.edu new_entry->used = true; 2013804Ssaidi@eecs.umich.edu usedEntries++; 2023804Ssaidi@eecs.umich.edu } 2033804Ssaidi@eecs.umich.edu 2043569Sgblack@eecs.umich.edu} 2053804Ssaidi@eecs.umich.edu 2063804Ssaidi@eecs.umich.edu 2073804Ssaidi@eecs.umich.eduTlbEntry* 2084070Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id, bool 2094070Ssaidi@eecs.umich.edu update_used) 2103804Ssaidi@eecs.umich.edu{ 2113804Ssaidi@eecs.umich.edu MapIter i; 2123804Ssaidi@eecs.umich.edu TlbRange tr; 2133804Ssaidi@eecs.umich.edu TlbEntry *t; 2143804Ssaidi@eecs.umich.edu 2153811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2163811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2173804Ssaidi@eecs.umich.edu // Assemble full address structure 2183804Ssaidi@eecs.umich.edu tr.va = va; 2193863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2203804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2213804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2223804Ssaidi@eecs.umich.edu tr.real = real; 2233804Ssaidi@eecs.umich.edu 2243804Ssaidi@eecs.umich.edu // Try to find the entry 2253804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2263804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2273811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2283804Ssaidi@eecs.umich.edu return NULL; 2293804Ssaidi@eecs.umich.edu } 2303804Ssaidi@eecs.umich.edu 2313804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2323804Ssaidi@eecs.umich.edu t = i->second; 2333826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2343826Ssaidi@eecs.umich.edu t->pte.size()); 2354070Ssaidi@eecs.umich.edu 2364070Ssaidi@eecs.umich.edu // Update the used bits only if this is a real access (not a fake one from 2374070Ssaidi@eecs.umich.edu // virttophys() 2384070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2393804Ssaidi@eecs.umich.edu t->used = true; 2403804Ssaidi@eecs.umich.edu usedEntries++; 2413804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2423804Ssaidi@eecs.umich.edu clearUsedBits(); 2433804Ssaidi@eecs.umich.edu t->used = true; 2443804Ssaidi@eecs.umich.edu usedEntries++; 2453804Ssaidi@eecs.umich.edu } 2463804Ssaidi@eecs.umich.edu } 2473804Ssaidi@eecs.umich.edu 2483804Ssaidi@eecs.umich.edu return t; 2493804Ssaidi@eecs.umich.edu} 2503804Ssaidi@eecs.umich.edu 2513826Ssaidi@eecs.umich.eduvoid 2523826Ssaidi@eecs.umich.eduTLB::dumpAll() 2533826Ssaidi@eecs.umich.edu{ 2543863Ssaidi@eecs.umich.edu MapIter i; 2553826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2563826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2573826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2583826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2593826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2603826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2613826Ssaidi@eecs.umich.edu } 2623826Ssaidi@eecs.umich.edu } 2633826Ssaidi@eecs.umich.edu} 2643804Ssaidi@eecs.umich.edu 2653804Ssaidi@eecs.umich.eduvoid 2663804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2673804Ssaidi@eecs.umich.edu{ 2683804Ssaidi@eecs.umich.edu TlbRange tr; 2693804Ssaidi@eecs.umich.edu MapIter i; 2703804Ssaidi@eecs.umich.edu 2713863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2723863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2733863Ssaidi@eecs.umich.edu 2743836Ssaidi@eecs.umich.edu cacheValid = false; 2753836Ssaidi@eecs.umich.edu 2763804Ssaidi@eecs.umich.edu // Assemble full address structure 2773804Ssaidi@eecs.umich.edu tr.va = va; 2783863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2793804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2803804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2813804Ssaidi@eecs.umich.edu tr.real = real; 2823804Ssaidi@eecs.umich.edu 2833804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2843804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2853804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2863863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2873804Ssaidi@eecs.umich.edu i->second->valid = false; 2883804Ssaidi@eecs.umich.edu if (i->second->used) { 2893804Ssaidi@eecs.umich.edu i->second->used = false; 2903804Ssaidi@eecs.umich.edu usedEntries--; 2913804Ssaidi@eecs.umich.edu } 2923881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2933804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2943804Ssaidi@eecs.umich.edu } 2953804Ssaidi@eecs.umich.edu} 2963804Ssaidi@eecs.umich.edu 2973804Ssaidi@eecs.umich.eduvoid 2983804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2993804Ssaidi@eecs.umich.edu{ 3003804Ssaidi@eecs.umich.edu int x; 3013863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 3023863Ssaidi@eecs.umich.edu partition_id, context_id); 3033836Ssaidi@eecs.umich.edu cacheValid = false; 3043804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3053804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3063804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3073881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3083881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3093881Ssaidi@eecs.umich.edu } 3103804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3113804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3123804Ssaidi@eecs.umich.edu tlb[x].used = false; 3133804Ssaidi@eecs.umich.edu usedEntries--; 3143804Ssaidi@eecs.umich.edu } 3153804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3163804Ssaidi@eecs.umich.edu } 3173804Ssaidi@eecs.umich.edu } 3183804Ssaidi@eecs.umich.edu} 3193804Ssaidi@eecs.umich.edu 3203804Ssaidi@eecs.umich.eduvoid 3213804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3223804Ssaidi@eecs.umich.edu{ 3233804Ssaidi@eecs.umich.edu int x; 3243863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3253836Ssaidi@eecs.umich.edu cacheValid = false; 3263804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3273804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3283881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3293881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3303881Ssaidi@eecs.umich.edu } 3313804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3323804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3333804Ssaidi@eecs.umich.edu tlb[x].used = false; 3343804Ssaidi@eecs.umich.edu usedEntries--; 3353804Ssaidi@eecs.umich.edu } 3363804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3373804Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu } 3393804Ssaidi@eecs.umich.edu} 3403804Ssaidi@eecs.umich.edu 3413804Ssaidi@eecs.umich.eduvoid 3423804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3433804Ssaidi@eecs.umich.edu{ 3443804Ssaidi@eecs.umich.edu int x; 3453836Ssaidi@eecs.umich.edu cacheValid = false; 3463836Ssaidi@eecs.umich.edu 3473881Ssaidi@eecs.umich.edu freeList.clear(); 3483907Ssaidi@eecs.umich.edu lookupTable.clear(); 3493804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3503881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3513881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3523804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3533907Ssaidi@eecs.umich.edu tlb[x].used = false; 3543804Ssaidi@eecs.umich.edu } 3553804Ssaidi@eecs.umich.edu usedEntries = 0; 3563804Ssaidi@eecs.umich.edu} 3573804Ssaidi@eecs.umich.edu 3583804Ssaidi@eecs.umich.eduuint64_t 3593804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3603881Ssaidi@eecs.umich.edu if (entry >= size) 3613881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3623881Ssaidi@eecs.umich.edu 3633804Ssaidi@eecs.umich.edu assert(entry < size); 3643881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3653881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3663881Ssaidi@eecs.umich.edu else 3673881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3683804Ssaidi@eecs.umich.edu} 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.eduuint64_t 3713804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3723804Ssaidi@eecs.umich.edu assert(entry < size); 3733804Ssaidi@eecs.umich.edu uint64_t tag; 3743881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3753881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3763804Ssaidi@eecs.umich.edu 3773881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3783881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3793881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3803804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3813804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3823804Ssaidi@eecs.umich.edu return tag; 3833804Ssaidi@eecs.umich.edu} 3843804Ssaidi@eecs.umich.edu 3853804Ssaidi@eecs.umich.edubool 3863804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3873804Ssaidi@eecs.umich.edu{ 3883804Ssaidi@eecs.umich.edu if (am) 3893804Ssaidi@eecs.umich.edu return true; 3903804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3913804Ssaidi@eecs.umich.edu return false; 3923804Ssaidi@eecs.umich.edu return true; 3933804Ssaidi@eecs.umich.edu} 3943804Ssaidi@eecs.umich.edu 3953804Ssaidi@eecs.umich.eduvoid 3963804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3973804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3983804Ssaidi@eecs.umich.edu{ 3993804Ssaidi@eecs.umich.edu uint64_t sfsr; 4004172Ssaidi@eecs.umich.edu sfsr = tc->readMiscRegNoEffect(reg); 4013804Ssaidi@eecs.umich.edu 4023804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4033804Ssaidi@eecs.umich.edu sfsr = 0x3; 4043804Ssaidi@eecs.umich.edu else 4053804Ssaidi@eecs.umich.edu sfsr = 1; 4063804Ssaidi@eecs.umich.edu 4073804Ssaidi@eecs.umich.edu if (write) 4083804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4093804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4103804Ssaidi@eecs.umich.edu if (se) 4113804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4123804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4133804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4144172Ssaidi@eecs.umich.edu tc->setMiscReg(reg, sfsr); 4153804Ssaidi@eecs.umich.edu} 4163804Ssaidi@eecs.umich.edu 4173826Ssaidi@eecs.umich.eduvoid 4183826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 4193826Ssaidi@eecs.umich.edu{ 4203916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4213916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4223916Ssaidi@eecs.umich.edu 4234172Ssaidi@eecs.umich.edu tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0)); 4243826Ssaidi@eecs.umich.edu} 4253804Ssaidi@eecs.umich.edu 4263804Ssaidi@eecs.umich.eduvoid 4273804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 4283804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4293804Ssaidi@eecs.umich.edu{ 4303811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4313811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4323804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 4333804Ssaidi@eecs.umich.edu} 4343804Ssaidi@eecs.umich.edu 4353804Ssaidi@eecs.umich.eduvoid 4363826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4373826Ssaidi@eecs.umich.edu{ 4383826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4393826Ssaidi@eecs.umich.edu} 4403826Ssaidi@eecs.umich.edu 4413826Ssaidi@eecs.umich.eduvoid 4423804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4433804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4443804Ssaidi@eecs.umich.edu{ 4453811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4463811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4473804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4484172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); 4493804Ssaidi@eecs.umich.edu} 4503804Ssaidi@eecs.umich.edu 4513836Ssaidi@eecs.umich.eduvoid 4523826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4533826Ssaidi@eecs.umich.edu{ 4543826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4553826Ssaidi@eecs.umich.edu} 4563826Ssaidi@eecs.umich.edu 4573826Ssaidi@eecs.umich.edu 4583804Ssaidi@eecs.umich.edu 4593804Ssaidi@eecs.umich.eduFault 4603804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4613804Ssaidi@eecs.umich.edu{ 4624172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4633833Ssaidi@eecs.umich.edu 4643836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4653836Ssaidi@eecs.umich.edu TlbEntry *e; 4663836Ssaidi@eecs.umich.edu 4673836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4683836Ssaidi@eecs.umich.edu 4693836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4703836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4713836Ssaidi@eecs.umich.edu 4723836Ssaidi@eecs.umich.edu // Be fast if we can! 4733836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4743836Ssaidi@eecs.umich.edu if (cacheEntry) { 4753836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4763836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4773836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4783836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4793836Ssaidi@eecs.umich.edu return NoFault; 4803836Ssaidi@eecs.umich.edu } 4813836Ssaidi@eecs.umich.edu } else { 4823836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4833836Ssaidi@eecs.umich.edu return NoFault; 4843836Ssaidi@eecs.umich.edu } 4853836Ssaidi@eecs.umich.edu } 4863836Ssaidi@eecs.umich.edu 4873833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4883833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4893833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4903833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4913833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4923833Ssaidi@eecs.umich.edu 4933833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4943833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4953833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4963804Ssaidi@eecs.umich.edu int context; 4973804Ssaidi@eecs.umich.edu ContextType ct; 4983804Ssaidi@eecs.umich.edu int asi; 4993804Ssaidi@eecs.umich.edu bool real = false; 5003804Ssaidi@eecs.umich.edu 5013833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 5023833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 5033811Ssaidi@eecs.umich.edu 5043804Ssaidi@eecs.umich.edu if (tl > 0) { 5053804Ssaidi@eecs.umich.edu asi = ASI_N; 5063804Ssaidi@eecs.umich.edu ct = Nucleus; 5073804Ssaidi@eecs.umich.edu context = 0; 5083804Ssaidi@eecs.umich.edu } else { 5093804Ssaidi@eecs.umich.edu asi = ASI_P; 5103804Ssaidi@eecs.umich.edu ct = Primary; 5113833Ssaidi@eecs.umich.edu context = pri_context; 5123804Ssaidi@eecs.umich.edu } 5133804Ssaidi@eecs.umich.edu 5143833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5153836Ssaidi@eecs.umich.edu cacheValid = true; 5163836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5173836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5183836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5193804Ssaidi@eecs.umich.edu return NoFault; 5203804Ssaidi@eecs.umich.edu } 5213804Ssaidi@eecs.umich.edu 5223836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5233836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5243804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 5253804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5263804Ssaidi@eecs.umich.edu } 5273804Ssaidi@eecs.umich.edu 5283804Ssaidi@eecs.umich.edu if (addr_mask) 5293804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5303804Ssaidi@eecs.umich.edu 5313804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5323804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 5333804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5343804Ssaidi@eecs.umich.edu } 5353804Ssaidi@eecs.umich.edu 5363833Ssaidi@eecs.umich.edu if (!lsu_im) { 5373836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5383804Ssaidi@eecs.umich.edu real = true; 5393804Ssaidi@eecs.umich.edu context = 0; 5403804Ssaidi@eecs.umich.edu } else { 5413804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5423804Ssaidi@eecs.umich.edu } 5433804Ssaidi@eecs.umich.edu 5443804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5453916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5463804Ssaidi@eecs.umich.edu if (real) 5473804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5483804Ssaidi@eecs.umich.edu else 5493804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5503804Ssaidi@eecs.umich.edu } 5513804Ssaidi@eecs.umich.edu 5523804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5533804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5543928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5553804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5563804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5573804Ssaidi@eecs.umich.edu } 5583804Ssaidi@eecs.umich.edu 5593836Ssaidi@eecs.umich.edu // cache translation date for next translation 5603836Ssaidi@eecs.umich.edu cacheValid = true; 5613836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5623836Ssaidi@eecs.umich.edu cacheEntry = e; 5633836Ssaidi@eecs.umich.edu 5643826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5653836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5663836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5673804Ssaidi@eecs.umich.edu return NoFault; 5683804Ssaidi@eecs.umich.edu} 5693804Ssaidi@eecs.umich.edu 5703804Ssaidi@eecs.umich.edu 5713804Ssaidi@eecs.umich.edu 5723804Ssaidi@eecs.umich.eduFault 5733804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5743804Ssaidi@eecs.umich.edu{ 5753804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5764172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5773836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5783836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5793836Ssaidi@eecs.umich.edu ASI asi; 5803836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5813836Ssaidi@eecs.umich.edu bool implicit = false; 5823836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5833833Ssaidi@eecs.umich.edu 5843836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5853836Ssaidi@eecs.umich.edu vaddr, size, asi); 5863836Ssaidi@eecs.umich.edu 5873929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5883929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5893929Ssaidi@eecs.umich.edu freeList.size()); 5903836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5913836Ssaidi@eecs.umich.edu implicit = true; 5923836Ssaidi@eecs.umich.edu 5933836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5943836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5953836Ssaidi@eecs.umich.edu return NoFault; 5963836Ssaidi@eecs.umich.edu } 5973836Ssaidi@eecs.umich.edu 5983836Ssaidi@eecs.umich.edu // Be fast if we can! 5993836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 6004090Ssaidi@eecs.umich.edu 6014090Ssaidi@eecs.umich.edu 6024090Ssaidi@eecs.umich.edu 6034989Sgblack@eecs.umich.edu if (cacheEntry[0]) { 6044090Ssaidi@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 6054989Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 6064090Ssaidi@eecs.umich.edu if (cacheAsi[0] == asi && 6074090Ssaidi@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6084090Ssaidi@eecs.umich.edu (!write || ce->pte.writable())) { 6094090Ssaidi@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6104090Ssaidi@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6114090Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6124090Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6134090Ssaidi@eecs.umich.edu return NoFault; 6144090Ssaidi@eecs.umich.edu } // if matched 6154090Ssaidi@eecs.umich.edu } // if cache entry valid 6164090Ssaidi@eecs.umich.edu if (cacheEntry[1]) { 6174090Ssaidi@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 6184090Ssaidi@eecs.umich.edu Addr ce_va = ce->range.va; 6194090Ssaidi@eecs.umich.edu if (cacheAsi[1] == asi && 6204090Ssaidi@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 6214090Ssaidi@eecs.umich.edu (!write || ce->pte.writable())) { 6224090Ssaidi@eecs.umich.edu req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 6234090Ssaidi@eecs.umich.edu if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 6244090Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 6254090Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 6264090Ssaidi@eecs.umich.edu return NoFault; 6274090Ssaidi@eecs.umich.edu } // if matched 6284090Ssaidi@eecs.umich.edu } // if cache entry valid 6294090Ssaidi@eecs.umich.edu } 6303836Ssaidi@eecs.umich.edu 6313833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6323833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6333833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6343833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6353833Ssaidi@eecs.umich.edu 6363833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6373833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6383833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6393916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6403833Ssaidi@eecs.umich.edu 6413804Ssaidi@eecs.umich.edu bool real = false; 6423832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6433832Ssaidi@eecs.umich.edu int context = 0; 6443804Ssaidi@eecs.umich.edu 6453804Ssaidi@eecs.umich.edu TlbEntry *e; 6463804Ssaidi@eecs.umich.edu 6473833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6483833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6493804Ssaidi@eecs.umich.edu 6503804Ssaidi@eecs.umich.edu if (implicit) { 6513804Ssaidi@eecs.umich.edu if (tl > 0) { 6523804Ssaidi@eecs.umich.edu asi = ASI_N; 6533804Ssaidi@eecs.umich.edu ct = Nucleus; 6543804Ssaidi@eecs.umich.edu context = 0; 6553804Ssaidi@eecs.umich.edu } else { 6563804Ssaidi@eecs.umich.edu asi = ASI_P; 6573804Ssaidi@eecs.umich.edu ct = Primary; 6583833Ssaidi@eecs.umich.edu context = pri_context; 6593804Ssaidi@eecs.umich.edu } 6603910Ssaidi@eecs.umich.edu } else { 6613804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6623910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6633804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6643804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6653804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6663804Ssaidi@eecs.umich.edu } 6673910Ssaidi@eecs.umich.edu 6683910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6693804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6703804Ssaidi@eecs.umich.edu return new DataAccessException; 6713804Ssaidi@eecs.umich.edu } 6723804Ssaidi@eecs.umich.edu 6733910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6743910Ssaidi@eecs.umich.edu context = pri_context; 6753910Ssaidi@eecs.umich.edu ct = Primary; 6763910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6773910Ssaidi@eecs.umich.edu context = sec_context; 6783910Ssaidi@eecs.umich.edu ct = Secondary; 6793910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6803910Ssaidi@eecs.umich.edu ct = Nucleus; 6813910Ssaidi@eecs.umich.edu context = 0; 6823910Ssaidi@eecs.umich.edu } else { // ???? 6833910Ssaidi@eecs.umich.edu ct = Primary; 6843910Ssaidi@eecs.umich.edu context = pri_context; 6853910Ssaidi@eecs.umich.edu } 6863902Ssaidi@eecs.umich.edu } 6873804Ssaidi@eecs.umich.edu 6883926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6893804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6903804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6914989Sgblack@eecs.umich.edu 6924989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6934989Sgblack@eecs.umich.edu //load differs from a regular one, other than what happens concerning 6944989Sgblack@eecs.umich.edu //nfo and e bits in the TTE 6954989Sgblack@eecs.umich.edu// if (AsiIsNoFault(asi)) 6964989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6973856Ssaidi@eecs.umich.edu 6983804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6993804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 7004103Ssaidi@eecs.umich.edu 7014191Ssaidi@eecs.umich.edu if (AsiIsCmt(asi)) 7024191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 7034191Ssaidi@eecs.umich.edu 7043824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 7054103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 7063804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 7073804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 7083804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 7093804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 7103824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 7113824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 7123825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 7133825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 7143823Ssaidi@eecs.umich.edu 7153926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 7164989Sgblack@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 7173823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 7183804Ssaidi@eecs.umich.edu } 7193804Ssaidi@eecs.umich.edu 7203826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 7213826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 7223826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 7233826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7243826Ssaidi@eecs.umich.edu } 7253826Ssaidi@eecs.umich.edu 7263826Ssaidi@eecs.umich.edu if (addr_mask) 7273826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7283826Ssaidi@eecs.umich.edu 7293826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7303826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 7313826Ssaidi@eecs.umich.edu return new DataAccessException; 7323826Ssaidi@eecs.umich.edu } 7333826Ssaidi@eecs.umich.edu 7343826Ssaidi@eecs.umich.edu 7353910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7363804Ssaidi@eecs.umich.edu real = true; 7373804Ssaidi@eecs.umich.edu context = 0; 7383804Ssaidi@eecs.umich.edu }; 7393804Ssaidi@eecs.umich.edu 7403804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7413836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7423804Ssaidi@eecs.umich.edu return NoFault; 7433804Ssaidi@eecs.umich.edu } 7443804Ssaidi@eecs.umich.edu 7453836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7463804Ssaidi@eecs.umich.edu 7473804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7483916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7493811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7503804Ssaidi@eecs.umich.edu if (real) 7513804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7523804Ssaidi@eecs.umich.edu else 7533804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7543804Ssaidi@eecs.umich.edu 7553804Ssaidi@eecs.umich.edu } 7563804Ssaidi@eecs.umich.edu 7573928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7583928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7593928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7603928Ssaidi@eecs.umich.edu return new DataAccessException; 7613928Ssaidi@eecs.umich.edu } 7623804Ssaidi@eecs.umich.edu 7633804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7643928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7653804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7663804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7673804Ssaidi@eecs.umich.edu } 7683804Ssaidi@eecs.umich.edu 7693804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7703928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7713804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7723804Ssaidi@eecs.umich.edu return new DataAccessException; 7733804Ssaidi@eecs.umich.edu } 7743804Ssaidi@eecs.umich.edu 7753928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7763928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7773928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7783928Ssaidi@eecs.umich.edu return new DataAccessException; 7793928Ssaidi@eecs.umich.edu } 7803928Ssaidi@eecs.umich.edu 7813928Ssaidi@eecs.umich.edu 7824090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 7833804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7843804Ssaidi@eecs.umich.edu 7853836Ssaidi@eecs.umich.edu // cache translation date for next translation 7863836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7873881Ssaidi@eecs.umich.edu if (!cacheValid) { 7883881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7893881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7903881Ssaidi@eecs.umich.edu } 7913881Ssaidi@eecs.umich.edu 7923836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7933836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7943836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7953836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7963836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7973836Ssaidi@eecs.umich.edu if (implicit) 7983836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7993836Ssaidi@eecs.umich.edu } 8003881Ssaidi@eecs.umich.edu cacheValid = true; 8013826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 8023836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 8033836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 8043804Ssaidi@eecs.umich.edu return NoFault; 8054103Ssaidi@eecs.umich.edu 8063806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 8074103Ssaidi@eecs.umich.eduhandleIntRegAccess: 8084103Ssaidi@eecs.umich.edu if (!hpriv) { 8094103Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8104103Ssaidi@eecs.umich.edu if (priv) 8114103Ssaidi@eecs.umich.edu return new DataAccessException; 8124103Ssaidi@eecs.umich.edu else 8134103Ssaidi@eecs.umich.edu return new PrivilegedAction; 8144103Ssaidi@eecs.umich.edu } 8154103Ssaidi@eecs.umich.edu 8164103Ssaidi@eecs.umich.edu if (asi == ASI_SWVR_UDB_INTR_W && !write || 8174103Ssaidi@eecs.umich.edu asi == ASI_SWVR_UDB_INTR_R && write) { 8184103Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8194103Ssaidi@eecs.umich.edu return new DataAccessException; 8204103Ssaidi@eecs.umich.edu } 8214103Ssaidi@eecs.umich.edu 8224103Ssaidi@eecs.umich.edu goto regAccessOk; 8234103Ssaidi@eecs.umich.edu 8243804Ssaidi@eecs.umich.edu 8253806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8263806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8273806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8283806Ssaidi@eecs.umich.edu return new DataAccessException; 8293806Ssaidi@eecs.umich.edu } 8303824Ssaidi@eecs.umich.edu goto regAccessOk; 8313824Ssaidi@eecs.umich.edu 8323824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8333824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8343824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8353824Ssaidi@eecs.umich.edu return new PrivilegedAction; 8363824Ssaidi@eecs.umich.edu } 8373881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 8383824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8393824Ssaidi@eecs.umich.edu return new DataAccessException; 8403824Ssaidi@eecs.umich.edu } 8413824Ssaidi@eecs.umich.edu goto regAccessOk; 8423824Ssaidi@eecs.umich.edu 8433825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8443825Ssaidi@eecs.umich.edu if (!hpriv) { 8454070Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8464070Ssaidi@eecs.umich.edu if (priv) 8473825Ssaidi@eecs.umich.edu return new DataAccessException; 8484070Ssaidi@eecs.umich.edu else 8493825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8503825Ssaidi@eecs.umich.edu } 8513825Ssaidi@eecs.umich.edu goto regAccessOk; 8523825Ssaidi@eecs.umich.edu 8533825Ssaidi@eecs.umich.edu 8543824Ssaidi@eecs.umich.eduregAccessOk: 8553804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8563811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8573806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8583806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8593806Ssaidi@eecs.umich.edu return NoFault; 8603804Ssaidi@eecs.umich.edu}; 8613804Ssaidi@eecs.umich.edu 8623806Ssaidi@eecs.umich.eduTick 8633806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8643806Ssaidi@eecs.umich.edu{ 8653823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8663823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8674070Ssaidi@eecs.umich.edu uint64_t temp; 8683823Ssaidi@eecs.umich.edu 8693823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8703823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8713823Ssaidi@eecs.umich.edu 8723823Ssaidi@eecs.umich.edu switch (asi) { 8733823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8743823Ssaidi@eecs.umich.edu assert(va == 0); 8754172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8763823Ssaidi@eecs.umich.edu break; 8773823Ssaidi@eecs.umich.edu case ASI_MMU: 8783823Ssaidi@eecs.umich.edu switch (va) { 8793823Ssaidi@eecs.umich.edu case 0x8: 8804172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu case 0x10: 8834172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8843823Ssaidi@eecs.umich.edu break; 8853823Ssaidi@eecs.umich.edu default: 8863823Ssaidi@eecs.umich.edu goto doMmuReadError; 8873823Ssaidi@eecs.umich.edu } 8883823Ssaidi@eecs.umich.edu break; 8893824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8904172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8913824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8923824Ssaidi@eecs.umich.edu break; 8933823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8943823Ssaidi@eecs.umich.edu assert(va == 0); 8954172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8963823Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 8994172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1)); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 9034172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG)); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 9074172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0)); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 9114172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1)); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 9154172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG)); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 9194172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0)); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 9234172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1)); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 9274172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 9314172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0)); 9323823Ssaidi@eecs.umich.edu break; 9333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9343823Ssaidi@eecs.umich.edu assert(va == 0); 9354172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1)); 9363823Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9383823Ssaidi@eecs.umich.edu assert(va == 0); 9394172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); 9403823Ssaidi@eecs.umich.edu break; 9413826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9423912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9433826Ssaidi@eecs.umich.edu break; 9443823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9453823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9464172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9473823Ssaidi@eecs.umich.edu break; 9483826Ssaidi@eecs.umich.edu case ASI_IMMU: 9493826Ssaidi@eecs.umich.edu switch (va) { 9503833Ssaidi@eecs.umich.edu case 0x0: 9514172Ssaidi@eecs.umich.edu temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); 9523833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9533833Ssaidi@eecs.umich.edu break; 9543906Ssaidi@eecs.umich.edu case 0x18: 9554172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR)); 9563906Ssaidi@eecs.umich.edu break; 9573826Ssaidi@eecs.umich.edu case 0x30: 9584172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS)); 9593826Ssaidi@eecs.umich.edu break; 9603826Ssaidi@eecs.umich.edu default: 9613826Ssaidi@eecs.umich.edu goto doMmuReadError; 9623826Ssaidi@eecs.umich.edu } 9633826Ssaidi@eecs.umich.edu break; 9643823Ssaidi@eecs.umich.edu case ASI_DMMU: 9653823Ssaidi@eecs.umich.edu switch (va) { 9663833Ssaidi@eecs.umich.edu case 0x0: 9674172Ssaidi@eecs.umich.edu temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); 9683833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9693833Ssaidi@eecs.umich.edu break; 9703906Ssaidi@eecs.umich.edu case 0x18: 9714172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR)); 9723906Ssaidi@eecs.umich.edu break; 9733906Ssaidi@eecs.umich.edu case 0x20: 9744172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR)); 9753906Ssaidi@eecs.umich.edu break; 9763826Ssaidi@eecs.umich.edu case 0x30: 9774172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS)); 9783826Ssaidi@eecs.umich.edu break; 9793823Ssaidi@eecs.umich.edu case 0x80: 9804172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9813823Ssaidi@eecs.umich.edu break; 9823823Ssaidi@eecs.umich.edu default: 9833823Ssaidi@eecs.umich.edu goto doMmuReadError; 9843823Ssaidi@eecs.umich.edu } 9853823Ssaidi@eecs.umich.edu break; 9863833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9874070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9884172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), 9894172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), 9904172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 9914172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), 9924172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); 9933833Ssaidi@eecs.umich.edu break; 9943833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9954070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9964172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), 9974172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), 9984172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 9994172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), 10004172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); 10013833Ssaidi@eecs.umich.edu break; 10023899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10034070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10044172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), 10054172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), 10064172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 10074172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), 10084172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); 10093899Ssaidi@eecs.umich.edu break; 10103899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10114070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10124172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), 10134172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), 10144172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 10154172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), 10164172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); 10173899Ssaidi@eecs.umich.edu break; 10184103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10194103Ssaidi@eecs.umich.edu pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10204103Ssaidi@eecs.umich.edu break; 10214103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10224103Ssaidi@eecs.umich.edu temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 10234103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 10244103Ssaidi@eecs.umich.edu pkt->set(temp); 10254103Ssaidi@eecs.umich.edu break; 10263823Ssaidi@eecs.umich.edu default: 10273823Ssaidi@eecs.umich.edudoMmuReadError: 10283823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10293823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10303823Ssaidi@eecs.umich.edu } 10314870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10323823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10333806Ssaidi@eecs.umich.edu} 10343806Ssaidi@eecs.umich.edu 10353806Ssaidi@eecs.umich.eduTick 10363806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10373806Ssaidi@eecs.umich.edu{ 10383823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10393823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10403823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10413823Ssaidi@eecs.umich.edu 10423826Ssaidi@eecs.umich.edu Addr ta_insert; 10433826Ssaidi@eecs.umich.edu Addr va_insert; 10443826Ssaidi@eecs.umich.edu Addr ct_insert; 10453826Ssaidi@eecs.umich.edu int part_insert; 10463826Ssaidi@eecs.umich.edu int entry_insert = -1; 10473826Ssaidi@eecs.umich.edu bool real_insert; 10483863Ssaidi@eecs.umich.edu bool ignore; 10493863Ssaidi@eecs.umich.edu int part_id; 10503863Ssaidi@eecs.umich.edu int ctx_id; 10513826Ssaidi@eecs.umich.edu PageTableEntry pte; 10523826Ssaidi@eecs.umich.edu 10533825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10543823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10553823Ssaidi@eecs.umich.edu 10563823Ssaidi@eecs.umich.edu switch (asi) { 10573823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10583823Ssaidi@eecs.umich.edu assert(va == 0); 10594172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu case ASI_MMU: 10623823Ssaidi@eecs.umich.edu switch (va) { 10633823Ssaidi@eecs.umich.edu case 0x8: 10644172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10653823Ssaidi@eecs.umich.edu break; 10663823Ssaidi@eecs.umich.edu case 0x10: 10674172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10683823Ssaidi@eecs.umich.edu break; 10693823Ssaidi@eecs.umich.edu default: 10703823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10713823Ssaidi@eecs.umich.edu } 10723823Ssaidi@eecs.umich.edu break; 10733824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10743825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10754172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10763824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10773824Ssaidi@eecs.umich.edu break; 10783823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10793823Ssaidi@eecs.umich.edu assert(va == 0); 10804172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 10813823Ssaidi@eecs.umich.edu break; 10823823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10833823Ssaidi@eecs.umich.edu assert(va == 0); 10844172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 10853823Ssaidi@eecs.umich.edu break; 10863823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10873823Ssaidi@eecs.umich.edu assert(va == 0); 10884172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data); 10893823Ssaidi@eecs.umich.edu break; 10903823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10913823Ssaidi@eecs.umich.edu assert(va == 0); 10924172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10933823Ssaidi@eecs.umich.edu break; 10943823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10953823Ssaidi@eecs.umich.edu assert(va == 0); 10964172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10973823Ssaidi@eecs.umich.edu break; 10983823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10993823Ssaidi@eecs.umich.edu assert(va == 0); 11004172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data); 11013823Ssaidi@eecs.umich.edu break; 11023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11033823Ssaidi@eecs.umich.edu assert(va == 0); 11044172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 11053823Ssaidi@eecs.umich.edu break; 11063823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11073823Ssaidi@eecs.umich.edu assert(va == 0); 11084172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 11093823Ssaidi@eecs.umich.edu break; 11103823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11113823Ssaidi@eecs.umich.edu assert(va == 0); 11124172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data); 11133823Ssaidi@eecs.umich.edu break; 11143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11153823Ssaidi@eecs.umich.edu assert(va == 0); 11164172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 11173823Ssaidi@eecs.umich.edu break; 11183823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11193823Ssaidi@eecs.umich.edu assert(va == 0); 11204172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 11213823Ssaidi@eecs.umich.edu break; 11223823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11233823Ssaidi@eecs.umich.edu assert(va == 0); 11244172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data); 11253823Ssaidi@eecs.umich.edu break; 11263825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11273825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11283825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11293825Ssaidi@eecs.umich.edu break; 11303823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11313823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11324172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11333823Ssaidi@eecs.umich.edu break; 11343826Ssaidi@eecs.umich.edu case ASI_IMMU: 11353826Ssaidi@eecs.umich.edu switch (va) { 11363906Ssaidi@eecs.umich.edu case 0x18: 11374172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data); 11383906Ssaidi@eecs.umich.edu break; 11393826Ssaidi@eecs.umich.edu case 0x30: 11403916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11414172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data); 11423826Ssaidi@eecs.umich.edu break; 11433826Ssaidi@eecs.umich.edu default: 11443826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11453826Ssaidi@eecs.umich.edu } 11463826Ssaidi@eecs.umich.edu break; 11473826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11483826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11493826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11503826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11514172Ssaidi@eecs.umich.edu ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); 11523826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11533826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11544172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11553826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11563826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11573826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11583826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11593826Ssaidi@eecs.umich.edu pte, entry_insert); 11603826Ssaidi@eecs.umich.edu break; 11613826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11623826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11633826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11643826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11654172Ssaidi@eecs.umich.edu ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); 11663826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11673826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11684172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11693826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11703826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11713826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11723826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11733826Ssaidi@eecs.umich.edu break; 11743863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11753863Ssaidi@eecs.umich.edu ignore = false; 11763863Ssaidi@eecs.umich.edu ctx_id = -1; 11774172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11783863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11793863Ssaidi@eecs.umich.edu case 0: 11804172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11813863Ssaidi@eecs.umich.edu break; 11823863Ssaidi@eecs.umich.edu case 1: 11833863Ssaidi@eecs.umich.edu ignore = true; 11843863Ssaidi@eecs.umich.edu break; 11853863Ssaidi@eecs.umich.edu case 3: 11863863Ssaidi@eecs.umich.edu ctx_id = 0; 11873863Ssaidi@eecs.umich.edu break; 11883863Ssaidi@eecs.umich.edu default: 11893863Ssaidi@eecs.umich.edu ignore = true; 11903863Ssaidi@eecs.umich.edu } 11913863Ssaidi@eecs.umich.edu 11923863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11933863Ssaidi@eecs.umich.edu case 0: // demap page 11943863Ssaidi@eecs.umich.edu if (!ignore) 11953863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11963863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11973863Ssaidi@eecs.umich.edu break; 11983863Ssaidi@eecs.umich.edu case 1: //demap context 11993863Ssaidi@eecs.umich.edu if (!ignore) 12003863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 12013863Ssaidi@eecs.umich.edu break; 12023863Ssaidi@eecs.umich.edu case 2: 12033863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 12043863Ssaidi@eecs.umich.edu break; 12053863Ssaidi@eecs.umich.edu default: 12063863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12073863Ssaidi@eecs.umich.edu } 12083863Ssaidi@eecs.umich.edu break; 12093823Ssaidi@eecs.umich.edu case ASI_DMMU: 12103823Ssaidi@eecs.umich.edu switch (va) { 12113906Ssaidi@eecs.umich.edu case 0x18: 12124172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data); 12133906Ssaidi@eecs.umich.edu break; 12143826Ssaidi@eecs.umich.edu case 0x30: 12153916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12164172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data); 12173826Ssaidi@eecs.umich.edu break; 12183823Ssaidi@eecs.umich.edu case 0x80: 12194172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12203823Ssaidi@eecs.umich.edu break; 12213823Ssaidi@eecs.umich.edu default: 12223823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12233823Ssaidi@eecs.umich.edu } 12243823Ssaidi@eecs.umich.edu break; 12253863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12263863Ssaidi@eecs.umich.edu ignore = false; 12273863Ssaidi@eecs.umich.edu ctx_id = -1; 12284172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12293863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12303863Ssaidi@eecs.umich.edu case 0: 12314172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12323863Ssaidi@eecs.umich.edu break; 12333863Ssaidi@eecs.umich.edu case 1: 12344172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12353863Ssaidi@eecs.umich.edu break; 12363863Ssaidi@eecs.umich.edu case 3: 12373863Ssaidi@eecs.umich.edu ctx_id = 0; 12383863Ssaidi@eecs.umich.edu break; 12393863Ssaidi@eecs.umich.edu default: 12403863Ssaidi@eecs.umich.edu ignore = true; 12413863Ssaidi@eecs.umich.edu } 12423863Ssaidi@eecs.umich.edu 12433863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12443863Ssaidi@eecs.umich.edu case 0: // demap page 12453863Ssaidi@eecs.umich.edu if (!ignore) 12463863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12473863Ssaidi@eecs.umich.edu break; 12483863Ssaidi@eecs.umich.edu case 1: //demap context 12493863Ssaidi@eecs.umich.edu if (!ignore) 12503863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12513863Ssaidi@eecs.umich.edu break; 12523863Ssaidi@eecs.umich.edu case 2: 12533863Ssaidi@eecs.umich.edu demapAll(part_id); 12543863Ssaidi@eecs.umich.edu break; 12553863Ssaidi@eecs.umich.edu default: 12563863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12573863Ssaidi@eecs.umich.edu } 12583863Ssaidi@eecs.umich.edu break; 12594103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12604103Ssaidi@eecs.umich.edu int msb; 12614103Ssaidi@eecs.umich.edu // clear all the interrupts that aren't set in the write 12624103Ssaidi@eecs.umich.edu while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) { 12634103Ssaidi@eecs.umich.edu msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data); 12644103Ssaidi@eecs.umich.edu tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); 12654103Ssaidi@eecs.umich.edu } 12664103Ssaidi@eecs.umich.edu break; 12674103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12684103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 12694103Ssaidi@eecs.umich.edu post_interrupt(bits(data,5,0),0); 12704103Ssaidi@eecs.umich.edu break; 12714103Ssaidi@eecs.umich.edu default: 12723823Ssaidi@eecs.umich.edudoMmuWriteError: 12733823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12743823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12753823Ssaidi@eecs.umich.edu } 12764870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12773823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12783806Ssaidi@eecs.umich.edu} 12793806Ssaidi@eecs.umich.edu 12803804Ssaidi@eecs.umich.eduvoid 12814070Ssaidi@eecs.umich.eduDTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12824070Ssaidi@eecs.umich.edu{ 12834070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 12844070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 12854172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), 12864172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 12874172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), 12884172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); 12894070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 12904172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), 12914172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 12924172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), 12934172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); 12944070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 12954172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), 12964172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 12974172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), 12984172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); 12994070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13004172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), 13014172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 13024172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), 13034172Ssaidi@eecs.umich.edu tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); 13044070Ssaidi@eecs.umich.edu} 13054070Ssaidi@eecs.umich.edu 13064070Ssaidi@eecs.umich.edu 13074070Ssaidi@eecs.umich.edu 13084070Ssaidi@eecs.umich.edu 13094070Ssaidi@eecs.umich.edu 13104070Ssaidi@eecs.umich.eduuint64_t 13114070Ssaidi@eecs.umich.eduDTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13124070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13134070Ssaidi@eecs.umich.edu{ 13144070Ssaidi@eecs.umich.edu uint64_t tsb; 13154070Ssaidi@eecs.umich.edu uint64_t config; 13164070Ssaidi@eecs.umich.edu 13174070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13184070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13194070Ssaidi@eecs.umich.edu config = c0_config; 13204070Ssaidi@eecs.umich.edu } else { 13214070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13224070Ssaidi@eecs.umich.edu config = cX_config; 13234070Ssaidi@eecs.umich.edu } 13244070Ssaidi@eecs.umich.edu 13254070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13264070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13274070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13284070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13294070Ssaidi@eecs.umich.edu 13304070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13314070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13324070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13334070Ssaidi@eecs.umich.edu 13344070Ssaidi@eecs.umich.edu return ptr; 13354070Ssaidi@eecs.umich.edu} 13364070Ssaidi@eecs.umich.edu 13374070Ssaidi@eecs.umich.edu 13384070Ssaidi@eecs.umich.eduvoid 13393804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 13403804Ssaidi@eecs.umich.edu{ 13414000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13424000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13434000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13444000Ssaidi@eecs.umich.edu 13454000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 13464000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 13474000Ssaidi@eecs.umich.edu int cntr = 0; 13484000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 13494000Ssaidi@eecs.umich.edu i = freeList.begin(); 13504000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 13514000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 13524000Ssaidi@eecs.umich.edu i++; 13534000Ssaidi@eecs.umich.edu } 13544000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 13554000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 13564000Ssaidi@eecs.umich.edu 13574000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13584000Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 13594000Ssaidi@eecs.umich.edu tlb[x].serialize(os); 13604000Ssaidi@eecs.umich.edu } 13613804Ssaidi@eecs.umich.edu} 13623804Ssaidi@eecs.umich.edu 13633804Ssaidi@eecs.umich.eduvoid 13643804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 13653804Ssaidi@eecs.umich.edu{ 13664000Ssaidi@eecs.umich.edu int oldSize; 13674000Ssaidi@eecs.umich.edu 13684000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 13694000Ssaidi@eecs.umich.edu if (oldSize != size) 13704000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13714000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13724000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13734000Ssaidi@eecs.umich.edu 13744000Ssaidi@eecs.umich.edu int cntr; 13754000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 13764000Ssaidi@eecs.umich.edu 13774000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 13784000Ssaidi@eecs.umich.edu freeList.clear(); 13794000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 13804000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 13814000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 13824000Ssaidi@eecs.umich.edu 13834000Ssaidi@eecs.umich.edu lookupTable.clear(); 13844000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 13854000Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 13864000Ssaidi@eecs.umich.edu if (tlb[x].valid) 13874000Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 13884000Ssaidi@eecs.umich.edu 13894000Ssaidi@eecs.umich.edu } 13903804Ssaidi@eecs.umich.edu} 13913804Ssaidi@eecs.umich.edu 13924088Sbinkertn@umich.edu/* end namespace SparcISA */ } 13934088Sbinkertn@umich.edu 13944762Snate@binkert.orgSparcISA::ITB * 13954762Snate@binkert.orgSparcITBParams::create() 13963804Ssaidi@eecs.umich.edu{ 13974762Snate@binkert.org return new SparcISA::ITB(name, size); 13983804Ssaidi@eecs.umich.edu} 13993804Ssaidi@eecs.umich.edu 14004762Snate@binkert.orgSparcISA::DTB * 14014762Snate@binkert.orgSparcDTBParams::create() 14023804Ssaidi@eecs.umich.edu{ 14034762Snate@binkert.org return new SparcISA::DTB(name, size); 14043804Ssaidi@eecs.umich.edu} 1405