tlb.cc revision 4010
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 333804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 343811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 363824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 373811Ssaidi@eecs.umich.edu#include "base/trace.hh" 383811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 393823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 403823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 413823Ssaidi@eecs.umich.edu#include "mem/request.hh" 423569Sgblack@eecs.umich.edu#include "sim/builder.hh" 433569Sgblack@eecs.umich.edu 443804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 453804Ssaidi@eecs.umich.edu * */ 463569Sgblack@eecs.umich.edunamespace SparcISA 473569Sgblack@eecs.umich.edu{ 483569Sgblack@eecs.umich.edu 493804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 503881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 513881Ssaidi@eecs.umich.edu cacheValid(false) 523804Ssaidi@eecs.umich.edu{ 533804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 543804Ssaidi@eecs.umich.edu if (size > 64) 553804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 563569Sgblack@eecs.umich.edu 573804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 583918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 593881Ssaidi@eecs.umich.edu 603881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 613881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 623804Ssaidi@eecs.umich.edu} 633569Sgblack@eecs.umich.edu 643804Ssaidi@eecs.umich.eduvoid 653804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 663804Ssaidi@eecs.umich.edu{ 673804Ssaidi@eecs.umich.edu MapIter i; 683881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 693804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 703804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 713804Ssaidi@eecs.umich.edu t->used = false; 723804Ssaidi@eecs.umich.edu usedEntries--; 733804Ssaidi@eecs.umich.edu } 743804Ssaidi@eecs.umich.edu } 753804Ssaidi@eecs.umich.edu} 763569Sgblack@eecs.umich.edu 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.eduvoid 793804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 803826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 813804Ssaidi@eecs.umich.edu{ 823569Sgblack@eecs.umich.edu 833569Sgblack@eecs.umich.edu 843804Ssaidi@eecs.umich.edu MapIter i; 853826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 863907Ssaidi@eecs.umich.edu// TlbRange tr; 873826Ssaidi@eecs.umich.edu int x; 883811Ssaidi@eecs.umich.edu 893836Ssaidi@eecs.umich.edu cacheValid = false; 903915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 913907Ssaidi@eecs.umich.edu /* tr.va = va; 923881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 933881Ssaidi@eecs.umich.edu tr.contextId = context_id; 943881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 953881Ssaidi@eecs.umich.edu tr.real = real; 963907Ssaidi@eecs.umich.edu*/ 973881Ssaidi@eecs.umich.edu 983881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 993881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1003881Ssaidi@eecs.umich.edu 1013881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1023907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1033907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1043907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1053907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1063907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1073907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1083907Ssaidi@eecs.umich.edu { 1093907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1103907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1113907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1123907Ssaidi@eecs.umich.edu 1133907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1143907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1153907Ssaidi@eecs.umich.edu tlb[x].used = false; 1163907Ssaidi@eecs.umich.edu usedEntries--; 1173907Ssaidi@eecs.umich.edu } 1183907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1193907Ssaidi@eecs.umich.edu } 1203907Ssaidi@eecs.umich.edu } 1213907Ssaidi@eecs.umich.edu } 1223907Ssaidi@eecs.umich.edu 1233907Ssaidi@eecs.umich.edu 1243907Ssaidi@eecs.umich.edu/* 1253881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1263881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1273881Ssaidi@eecs.umich.edu i->second->valid = false; 1283881Ssaidi@eecs.umich.edu if (i->second->used) { 1293881Ssaidi@eecs.umich.edu i->second->used = false; 1303881Ssaidi@eecs.umich.edu usedEntries--; 1313881Ssaidi@eecs.umich.edu } 1323881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1333881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1343881Ssaidi@eecs.umich.edu i->second); 1353881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1363881Ssaidi@eecs.umich.edu } 1373907Ssaidi@eecs.umich.edu*/ 1383811Ssaidi@eecs.umich.edu 1393826Ssaidi@eecs.umich.edu if (entry != -1) { 1403826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1413826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1423826Ssaidi@eecs.umich.edu } else { 1433881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1443881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1453881Ssaidi@eecs.umich.edu } else { 1463881Ssaidi@eecs.umich.edu x = lastReplaced; 1473881Ssaidi@eecs.umich.edu do { 1483881Ssaidi@eecs.umich.edu ++x; 1493881Ssaidi@eecs.umich.edu if (x == size) 1503881Ssaidi@eecs.umich.edu x = 0; 1513881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1523881Ssaidi@eecs.umich.edu goto insertAllLocked; 1533881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1543881Ssaidi@eecs.umich.edu lastReplaced = x; 1553881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1563881Ssaidi@eecs.umich.edu } 1573881Ssaidi@eecs.umich.edu /* 1583826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1593826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1603826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1613826Ssaidi@eecs.umich.edu break; 1623826Ssaidi@eecs.umich.edu } 1633881Ssaidi@eecs.umich.edu }*/ 1643569Sgblack@eecs.umich.edu } 1653569Sgblack@eecs.umich.edu 1663881Ssaidi@eecs.umich.eduinsertAllLocked: 1673804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1683881Ssaidi@eecs.umich.edu if (!new_entry) { 1693826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1703881Ssaidi@eecs.umich.edu } 1713881Ssaidi@eecs.umich.edu 1723881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1733907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1743907Ssaidi@eecs.umich.edu usedEntries--; 1753929Ssaidi@eecs.umich.edu if (new_entry->valid) 1763929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1773907Ssaidi@eecs.umich.edu 1783907Ssaidi@eecs.umich.edu 1793804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1803804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1813881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1823804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1833804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1843804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1853804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1863804Ssaidi@eecs.umich.edu new_entry->used = true;; 1873804Ssaidi@eecs.umich.edu new_entry->valid = true; 1883804Ssaidi@eecs.umich.edu usedEntries++; 1893569Sgblack@eecs.umich.edu 1903569Sgblack@eecs.umich.edu 1913569Sgblack@eecs.umich.edu 1923863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1933863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1943804Ssaidi@eecs.umich.edu 1953804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1963804Ssaidi@eecs.umich.edu // one we just inserted 1973804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1983804Ssaidi@eecs.umich.edu clearUsedBits(); 1993804Ssaidi@eecs.umich.edu new_entry->used = true; 2003804Ssaidi@eecs.umich.edu usedEntries++; 2013804Ssaidi@eecs.umich.edu } 2023804Ssaidi@eecs.umich.edu 2033569Sgblack@eecs.umich.edu} 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.edu 2063804Ssaidi@eecs.umich.eduTlbEntry* 2073804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 2083804Ssaidi@eecs.umich.edu{ 2093804Ssaidi@eecs.umich.edu MapIter i; 2103804Ssaidi@eecs.umich.edu TlbRange tr; 2113804Ssaidi@eecs.umich.edu TlbEntry *t; 2123804Ssaidi@eecs.umich.edu 2133811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2143811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2153804Ssaidi@eecs.umich.edu // Assemble full address structure 2163804Ssaidi@eecs.umich.edu tr.va = va; 2173863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2183804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2193804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2203804Ssaidi@eecs.umich.edu tr.real = real; 2213804Ssaidi@eecs.umich.edu 2223804Ssaidi@eecs.umich.edu // Try to find the entry 2233804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2243804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2253811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2263804Ssaidi@eecs.umich.edu return NULL; 2273804Ssaidi@eecs.umich.edu } 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2303804Ssaidi@eecs.umich.edu t = i->second; 2313826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2323826Ssaidi@eecs.umich.edu t->pte.size()); 2333804Ssaidi@eecs.umich.edu if (!t->used) { 2343804Ssaidi@eecs.umich.edu t->used = true; 2353804Ssaidi@eecs.umich.edu usedEntries++; 2363804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2373804Ssaidi@eecs.umich.edu clearUsedBits(); 2383804Ssaidi@eecs.umich.edu t->used = true; 2393804Ssaidi@eecs.umich.edu usedEntries++; 2403804Ssaidi@eecs.umich.edu } 2413804Ssaidi@eecs.umich.edu } 2423804Ssaidi@eecs.umich.edu 2433804Ssaidi@eecs.umich.edu return t; 2443804Ssaidi@eecs.umich.edu} 2453804Ssaidi@eecs.umich.edu 2463826Ssaidi@eecs.umich.eduvoid 2473826Ssaidi@eecs.umich.eduTLB::dumpAll() 2483826Ssaidi@eecs.umich.edu{ 2493863Ssaidi@eecs.umich.edu MapIter i; 2503826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2513826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2523826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2533826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2543826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2553826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2563826Ssaidi@eecs.umich.edu } 2573826Ssaidi@eecs.umich.edu } 2583826Ssaidi@eecs.umich.edu} 2593804Ssaidi@eecs.umich.edu 2603804Ssaidi@eecs.umich.eduvoid 2613804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2623804Ssaidi@eecs.umich.edu{ 2633804Ssaidi@eecs.umich.edu TlbRange tr; 2643804Ssaidi@eecs.umich.edu MapIter i; 2653804Ssaidi@eecs.umich.edu 2663863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2673863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2683863Ssaidi@eecs.umich.edu 2693836Ssaidi@eecs.umich.edu cacheValid = false; 2703836Ssaidi@eecs.umich.edu 2713804Ssaidi@eecs.umich.edu // Assemble full address structure 2723804Ssaidi@eecs.umich.edu tr.va = va; 2733863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2743804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2753804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2763804Ssaidi@eecs.umich.edu tr.real = real; 2773804Ssaidi@eecs.umich.edu 2783804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2793804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2803804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2813863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2823804Ssaidi@eecs.umich.edu i->second->valid = false; 2833804Ssaidi@eecs.umich.edu if (i->second->used) { 2843804Ssaidi@eecs.umich.edu i->second->used = false; 2853804Ssaidi@eecs.umich.edu usedEntries--; 2863804Ssaidi@eecs.umich.edu } 2873881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2883804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2893804Ssaidi@eecs.umich.edu } 2903804Ssaidi@eecs.umich.edu} 2913804Ssaidi@eecs.umich.edu 2923804Ssaidi@eecs.umich.eduvoid 2933804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2943804Ssaidi@eecs.umich.edu{ 2953804Ssaidi@eecs.umich.edu int x; 2963863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2973863Ssaidi@eecs.umich.edu partition_id, context_id); 2983836Ssaidi@eecs.umich.edu cacheValid = false; 2993804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3003804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3013804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3023881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3033881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3043881Ssaidi@eecs.umich.edu } 3053804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3063804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3073804Ssaidi@eecs.umich.edu tlb[x].used = false; 3083804Ssaidi@eecs.umich.edu usedEntries--; 3093804Ssaidi@eecs.umich.edu } 3103804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3113804Ssaidi@eecs.umich.edu } 3123804Ssaidi@eecs.umich.edu } 3133804Ssaidi@eecs.umich.edu} 3143804Ssaidi@eecs.umich.edu 3153804Ssaidi@eecs.umich.eduvoid 3163804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3173804Ssaidi@eecs.umich.edu{ 3183804Ssaidi@eecs.umich.edu int x; 3193863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3203836Ssaidi@eecs.umich.edu cacheValid = false; 3213804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3223804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3233881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3243881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3253881Ssaidi@eecs.umich.edu } 3263804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3273804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3283804Ssaidi@eecs.umich.edu tlb[x].used = false; 3293804Ssaidi@eecs.umich.edu usedEntries--; 3303804Ssaidi@eecs.umich.edu } 3313804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3323804Ssaidi@eecs.umich.edu } 3333804Ssaidi@eecs.umich.edu } 3343804Ssaidi@eecs.umich.edu} 3353804Ssaidi@eecs.umich.edu 3363804Ssaidi@eecs.umich.eduvoid 3373804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3383804Ssaidi@eecs.umich.edu{ 3393804Ssaidi@eecs.umich.edu int x; 3403836Ssaidi@eecs.umich.edu cacheValid = false; 3413836Ssaidi@eecs.umich.edu 3423881Ssaidi@eecs.umich.edu freeList.clear(); 3433907Ssaidi@eecs.umich.edu lookupTable.clear(); 3443804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3453881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3463881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3473804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3483907Ssaidi@eecs.umich.edu tlb[x].used = false; 3493804Ssaidi@eecs.umich.edu } 3503804Ssaidi@eecs.umich.edu usedEntries = 0; 3513804Ssaidi@eecs.umich.edu} 3523804Ssaidi@eecs.umich.edu 3533804Ssaidi@eecs.umich.eduuint64_t 3543804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3553881Ssaidi@eecs.umich.edu if (entry >= size) 3563881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3573881Ssaidi@eecs.umich.edu 3583804Ssaidi@eecs.umich.edu assert(entry < size); 3593881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3603881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3613881Ssaidi@eecs.umich.edu else 3623881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3633804Ssaidi@eecs.umich.edu} 3643804Ssaidi@eecs.umich.edu 3653804Ssaidi@eecs.umich.eduuint64_t 3663804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3673804Ssaidi@eecs.umich.edu assert(entry < size); 3683804Ssaidi@eecs.umich.edu uint64_t tag; 3693881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3703881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3713804Ssaidi@eecs.umich.edu 3723881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3733881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3743881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3753804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3763804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3773804Ssaidi@eecs.umich.edu return tag; 3783804Ssaidi@eecs.umich.edu} 3793804Ssaidi@eecs.umich.edu 3803804Ssaidi@eecs.umich.edubool 3813804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3823804Ssaidi@eecs.umich.edu{ 3833804Ssaidi@eecs.umich.edu if (am) 3843804Ssaidi@eecs.umich.edu return true; 3853804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3863804Ssaidi@eecs.umich.edu return false; 3873804Ssaidi@eecs.umich.edu return true; 3883804Ssaidi@eecs.umich.edu} 3893804Ssaidi@eecs.umich.edu 3903804Ssaidi@eecs.umich.eduvoid 3913804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3923804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3933804Ssaidi@eecs.umich.edu{ 3943804Ssaidi@eecs.umich.edu uint64_t sfsr; 3953804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3963804Ssaidi@eecs.umich.edu 3973804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3983804Ssaidi@eecs.umich.edu sfsr = 0x3; 3993804Ssaidi@eecs.umich.edu else 4003804Ssaidi@eecs.umich.edu sfsr = 1; 4013804Ssaidi@eecs.umich.edu 4023804Ssaidi@eecs.umich.edu if (write) 4033804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4043804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4053804Ssaidi@eecs.umich.edu if (se) 4063804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4073804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4083804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4093826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 4103804Ssaidi@eecs.umich.edu} 4113804Ssaidi@eecs.umich.edu 4123826Ssaidi@eecs.umich.eduvoid 4133826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 4143826Ssaidi@eecs.umich.edu{ 4153916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4163916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4173916Ssaidi@eecs.umich.edu 4183826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 4193826Ssaidi@eecs.umich.edu} 4203804Ssaidi@eecs.umich.edu 4213804Ssaidi@eecs.umich.eduvoid 4223804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 4233804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4243804Ssaidi@eecs.umich.edu{ 4253811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4263811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4273804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 4283804Ssaidi@eecs.umich.edu} 4293804Ssaidi@eecs.umich.edu 4303804Ssaidi@eecs.umich.eduvoid 4313826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4323826Ssaidi@eecs.umich.edu{ 4333826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4343826Ssaidi@eecs.umich.edu} 4353826Ssaidi@eecs.umich.edu 4363826Ssaidi@eecs.umich.eduvoid 4373804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4383804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4393804Ssaidi@eecs.umich.edu{ 4403811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4413811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4423804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4433826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 4443804Ssaidi@eecs.umich.edu} 4453804Ssaidi@eecs.umich.edu 4463836Ssaidi@eecs.umich.eduvoid 4473826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4483826Ssaidi@eecs.umich.edu{ 4493826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4503826Ssaidi@eecs.umich.edu} 4513826Ssaidi@eecs.umich.edu 4523826Ssaidi@eecs.umich.edu 4533804Ssaidi@eecs.umich.edu 4543804Ssaidi@eecs.umich.eduFault 4553804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4563804Ssaidi@eecs.umich.edu{ 4573833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4583833Ssaidi@eecs.umich.edu 4593836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4603836Ssaidi@eecs.umich.edu TlbEntry *e; 4613836Ssaidi@eecs.umich.edu 4623836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4633836Ssaidi@eecs.umich.edu 4643836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4653836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4663836Ssaidi@eecs.umich.edu 4673836Ssaidi@eecs.umich.edu // Be fast if we can! 4683836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4693836Ssaidi@eecs.umich.edu if (cacheEntry) { 4703836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4713836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4723836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4733836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4743836Ssaidi@eecs.umich.edu return NoFault; 4753836Ssaidi@eecs.umich.edu } 4763836Ssaidi@eecs.umich.edu } else { 4773836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4783836Ssaidi@eecs.umich.edu return NoFault; 4793836Ssaidi@eecs.umich.edu } 4803836Ssaidi@eecs.umich.edu } 4813836Ssaidi@eecs.umich.edu 4823833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4833833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4843833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4853833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4863833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4873833Ssaidi@eecs.umich.edu 4883833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4893833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4903833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4913804Ssaidi@eecs.umich.edu int context; 4923804Ssaidi@eecs.umich.edu ContextType ct; 4933804Ssaidi@eecs.umich.edu int asi; 4943804Ssaidi@eecs.umich.edu bool real = false; 4953804Ssaidi@eecs.umich.edu 4963833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4973833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4983811Ssaidi@eecs.umich.edu 4993804Ssaidi@eecs.umich.edu if (tl > 0) { 5003804Ssaidi@eecs.umich.edu asi = ASI_N; 5013804Ssaidi@eecs.umich.edu ct = Nucleus; 5023804Ssaidi@eecs.umich.edu context = 0; 5033804Ssaidi@eecs.umich.edu } else { 5043804Ssaidi@eecs.umich.edu asi = ASI_P; 5053804Ssaidi@eecs.umich.edu ct = Primary; 5063833Ssaidi@eecs.umich.edu context = pri_context; 5073804Ssaidi@eecs.umich.edu } 5083804Ssaidi@eecs.umich.edu 5093833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5103836Ssaidi@eecs.umich.edu cacheValid = true; 5113836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5123836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5133836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5143804Ssaidi@eecs.umich.edu return NoFault; 5153804Ssaidi@eecs.umich.edu } 5163804Ssaidi@eecs.umich.edu 5173836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5183836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5193804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 5203804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5213804Ssaidi@eecs.umich.edu } 5223804Ssaidi@eecs.umich.edu 5233804Ssaidi@eecs.umich.edu if (addr_mask) 5243804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5253804Ssaidi@eecs.umich.edu 5263804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5273804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 5283804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5293804Ssaidi@eecs.umich.edu } 5303804Ssaidi@eecs.umich.edu 5313833Ssaidi@eecs.umich.edu if (!lsu_im) { 5323836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5333804Ssaidi@eecs.umich.edu real = true; 5343804Ssaidi@eecs.umich.edu context = 0; 5353804Ssaidi@eecs.umich.edu } else { 5363804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5373804Ssaidi@eecs.umich.edu } 5383804Ssaidi@eecs.umich.edu 5393804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5403916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5413804Ssaidi@eecs.umich.edu if (real) 5423804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5433804Ssaidi@eecs.umich.edu else 5443804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5453804Ssaidi@eecs.umich.edu } 5463804Ssaidi@eecs.umich.edu 5473804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5483804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5493928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5503804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5513804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5523804Ssaidi@eecs.umich.edu } 5533804Ssaidi@eecs.umich.edu 5543836Ssaidi@eecs.umich.edu // cache translation date for next translation 5553836Ssaidi@eecs.umich.edu cacheValid = true; 5563836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5573836Ssaidi@eecs.umich.edu cacheEntry = e; 5583836Ssaidi@eecs.umich.edu 5593826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5603836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5613836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5623804Ssaidi@eecs.umich.edu return NoFault; 5633804Ssaidi@eecs.umich.edu} 5643804Ssaidi@eecs.umich.edu 5653804Ssaidi@eecs.umich.edu 5663804Ssaidi@eecs.umich.edu 5673804Ssaidi@eecs.umich.eduFault 5683804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5693804Ssaidi@eecs.umich.edu{ 5703804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5713833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 5723836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5733836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5743836Ssaidi@eecs.umich.edu ASI asi; 5753836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5763836Ssaidi@eecs.umich.edu bool implicit = false; 5773836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5783833Ssaidi@eecs.umich.edu 5793836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5803836Ssaidi@eecs.umich.edu vaddr, size, asi); 5813836Ssaidi@eecs.umich.edu 5823929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5833929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5843929Ssaidi@eecs.umich.edu freeList.size()); 5853836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5863836Ssaidi@eecs.umich.edu implicit = true; 5873836Ssaidi@eecs.umich.edu 5883836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5893836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5903836Ssaidi@eecs.umich.edu return NoFault; 5913836Ssaidi@eecs.umich.edu } 5923836Ssaidi@eecs.umich.edu 5933836Ssaidi@eecs.umich.edu // Be fast if we can! 5943836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5953836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 5963928Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr && 5973928Ssaidi@eecs.umich.edu (!write || cacheEntry[0]->pte.writable())) { 5983836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 5993836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 6003836Ssaidi@eecs.umich.edu return NoFault; 6013836Ssaidi@eecs.umich.edu } 6023836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 6033928Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr && 6043928Ssaidi@eecs.umich.edu (!write || cacheEntry[1]->pte.writable())) { 6053836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 6063836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 6073836Ssaidi@eecs.umich.edu return NoFault; 6083836Ssaidi@eecs.umich.edu } 6093836Ssaidi@eecs.umich.edu } 6103836Ssaidi@eecs.umich.edu 6113833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6123833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6133833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6143833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6153833Ssaidi@eecs.umich.edu 6163833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6173833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6183833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6193916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6203833Ssaidi@eecs.umich.edu 6213804Ssaidi@eecs.umich.edu bool real = false; 6223832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6233832Ssaidi@eecs.umich.edu int context = 0; 6243804Ssaidi@eecs.umich.edu 6253804Ssaidi@eecs.umich.edu TlbEntry *e; 6263804Ssaidi@eecs.umich.edu 6273833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6283833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6293804Ssaidi@eecs.umich.edu 6303804Ssaidi@eecs.umich.edu if (implicit) { 6313804Ssaidi@eecs.umich.edu if (tl > 0) { 6323804Ssaidi@eecs.umich.edu asi = ASI_N; 6333804Ssaidi@eecs.umich.edu ct = Nucleus; 6343804Ssaidi@eecs.umich.edu context = 0; 6353804Ssaidi@eecs.umich.edu } else { 6363804Ssaidi@eecs.umich.edu asi = ASI_P; 6373804Ssaidi@eecs.umich.edu ct = Primary; 6383833Ssaidi@eecs.umich.edu context = pri_context; 6393804Ssaidi@eecs.umich.edu } 6403910Ssaidi@eecs.umich.edu } else { 6413804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6423910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6433804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6443804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6453804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6463804Ssaidi@eecs.umich.edu } 6473910Ssaidi@eecs.umich.edu 6483910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6493804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6503804Ssaidi@eecs.umich.edu return new DataAccessException; 6513804Ssaidi@eecs.umich.edu } 6523804Ssaidi@eecs.umich.edu 6533910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6543910Ssaidi@eecs.umich.edu context = pri_context; 6553910Ssaidi@eecs.umich.edu ct = Primary; 6563910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6573910Ssaidi@eecs.umich.edu context = sec_context; 6583910Ssaidi@eecs.umich.edu ct = Secondary; 6593910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6603910Ssaidi@eecs.umich.edu ct = Nucleus; 6613910Ssaidi@eecs.umich.edu context = 0; 6623910Ssaidi@eecs.umich.edu } else { // ???? 6633910Ssaidi@eecs.umich.edu ct = Primary; 6643910Ssaidi@eecs.umich.edu context = pri_context; 6653910Ssaidi@eecs.umich.edu } 6663902Ssaidi@eecs.umich.edu } 6673804Ssaidi@eecs.umich.edu 6683926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6693804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6703804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6713804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 6723804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 6733856Ssaidi@eecs.umich.edu 6743804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6753804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6763824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6773824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 6783823Ssaidi@eecs.umich.edu 6793804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6803804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6813804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6823804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6833824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6843824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6853825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6863825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6873823Ssaidi@eecs.umich.edu 6883926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 6894010Ssaidi@eecs.umich.edu !AsiIsTwin(asi) && !AsiIsBlock(asi)) 6903823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6913804Ssaidi@eecs.umich.edu } 6923804Ssaidi@eecs.umich.edu 6933826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6943826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6953826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 6963826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6973826Ssaidi@eecs.umich.edu } 6983826Ssaidi@eecs.umich.edu 6993826Ssaidi@eecs.umich.edu if (addr_mask) 7003826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7013826Ssaidi@eecs.umich.edu 7023826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7033826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 7043826Ssaidi@eecs.umich.edu return new DataAccessException; 7053826Ssaidi@eecs.umich.edu } 7063826Ssaidi@eecs.umich.edu 7073826Ssaidi@eecs.umich.edu 7083910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7093804Ssaidi@eecs.umich.edu real = true; 7103804Ssaidi@eecs.umich.edu context = 0; 7113804Ssaidi@eecs.umich.edu }; 7123804Ssaidi@eecs.umich.edu 7133804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7143836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7153804Ssaidi@eecs.umich.edu return NoFault; 7163804Ssaidi@eecs.umich.edu } 7173804Ssaidi@eecs.umich.edu 7183836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7193804Ssaidi@eecs.umich.edu 7203804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7213916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7223811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7233804Ssaidi@eecs.umich.edu if (real) 7243804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7253804Ssaidi@eecs.umich.edu else 7263804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7273804Ssaidi@eecs.umich.edu 7283804Ssaidi@eecs.umich.edu } 7293804Ssaidi@eecs.umich.edu 7303928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7313928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7323928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7333928Ssaidi@eecs.umich.edu return new DataAccessException; 7343928Ssaidi@eecs.umich.edu } 7353804Ssaidi@eecs.umich.edu 7363804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7373928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7383804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7393804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7403804Ssaidi@eecs.umich.edu } 7413804Ssaidi@eecs.umich.edu 7423804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7433928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7443804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7453804Ssaidi@eecs.umich.edu return new DataAccessException; 7463804Ssaidi@eecs.umich.edu } 7473804Ssaidi@eecs.umich.edu 7483928Ssaidi@eecs.umich.edu if (e->pte.sideffect() && AsiIsNoFault(asi)) { 7493928Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7503928Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 7513928Ssaidi@eecs.umich.edu return new DataAccessException; 7523928Ssaidi@eecs.umich.edu } 7533928Ssaidi@eecs.umich.edu 7543928Ssaidi@eecs.umich.edu 7553804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 7563804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7573804Ssaidi@eecs.umich.edu 7583836Ssaidi@eecs.umich.edu // cache translation date for next translation 7593836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7603881Ssaidi@eecs.umich.edu if (!cacheValid) { 7613881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7623881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7633881Ssaidi@eecs.umich.edu } 7643881Ssaidi@eecs.umich.edu 7653836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7663836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7673836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7683836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7693836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7703836Ssaidi@eecs.umich.edu if (implicit) 7713836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7723836Ssaidi@eecs.umich.edu } 7733881Ssaidi@eecs.umich.edu cacheValid = true; 7743826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7753836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7763836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7773804Ssaidi@eecs.umich.edu return NoFault; 7783806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7793804Ssaidi@eecs.umich.edu 7803806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7813806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7823806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7833806Ssaidi@eecs.umich.edu return new DataAccessException; 7843806Ssaidi@eecs.umich.edu } 7853824Ssaidi@eecs.umich.edu goto regAccessOk; 7863824Ssaidi@eecs.umich.edu 7873824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7883824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7893824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7903824Ssaidi@eecs.umich.edu return new PrivilegedAction; 7913824Ssaidi@eecs.umich.edu } 7923881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 7933824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7943824Ssaidi@eecs.umich.edu return new DataAccessException; 7953824Ssaidi@eecs.umich.edu } 7963824Ssaidi@eecs.umich.edu goto regAccessOk; 7973824Ssaidi@eecs.umich.edu 7983825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 7993825Ssaidi@eecs.umich.edu if (!hpriv) { 8003825Ssaidi@eecs.umich.edu if (priv) { 8013825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8023825Ssaidi@eecs.umich.edu return new DataAccessException; 8033825Ssaidi@eecs.umich.edu } else { 8043825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8053825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8063825Ssaidi@eecs.umich.edu } 8073825Ssaidi@eecs.umich.edu } 8083825Ssaidi@eecs.umich.edu goto regAccessOk; 8093825Ssaidi@eecs.umich.edu 8103825Ssaidi@eecs.umich.edu 8113824Ssaidi@eecs.umich.eduregAccessOk: 8123804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8133811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8143806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8153806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8163806Ssaidi@eecs.umich.edu return NoFault; 8173804Ssaidi@eecs.umich.edu}; 8183804Ssaidi@eecs.umich.edu 8193806Ssaidi@eecs.umich.eduTick 8203806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8213806Ssaidi@eecs.umich.edu{ 8223823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8233823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8243833Ssaidi@eecs.umich.edu uint64_t temp, data; 8253833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 8263823Ssaidi@eecs.umich.edu 8273823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8283823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8293823Ssaidi@eecs.umich.edu 8303823Ssaidi@eecs.umich.edu switch (asi) { 8313823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8323823Ssaidi@eecs.umich.edu assert(va == 0); 8333823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 8343823Ssaidi@eecs.umich.edu break; 8353823Ssaidi@eecs.umich.edu case ASI_MMU: 8363823Ssaidi@eecs.umich.edu switch (va) { 8373823Ssaidi@eecs.umich.edu case 0x8: 8383823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 8393823Ssaidi@eecs.umich.edu break; 8403823Ssaidi@eecs.umich.edu case 0x10: 8413823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 8423823Ssaidi@eecs.umich.edu break; 8433823Ssaidi@eecs.umich.edu default: 8443823Ssaidi@eecs.umich.edu goto doMmuReadError; 8453823Ssaidi@eecs.umich.edu } 8463823Ssaidi@eecs.umich.edu break; 8473824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8483824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8493824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8503824Ssaidi@eecs.umich.edu break; 8513823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8523823Ssaidi@eecs.umich.edu assert(va == 0); 8533823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8543823Ssaidi@eecs.umich.edu break; 8553823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8563823Ssaidi@eecs.umich.edu assert(va == 0); 8573823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 8583823Ssaidi@eecs.umich.edu break; 8593823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8603823Ssaidi@eecs.umich.edu assert(va == 0); 8613823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 8623823Ssaidi@eecs.umich.edu break; 8633823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8643823Ssaidi@eecs.umich.edu assert(va == 0); 8653823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 8663823Ssaidi@eecs.umich.edu break; 8673823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8683823Ssaidi@eecs.umich.edu assert(va == 0); 8693823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 8703823Ssaidi@eecs.umich.edu break; 8713823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8723823Ssaidi@eecs.umich.edu assert(va == 0); 8733823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 8743823Ssaidi@eecs.umich.edu break; 8753823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8763823Ssaidi@eecs.umich.edu assert(va == 0); 8773823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 8783823Ssaidi@eecs.umich.edu break; 8793823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8803823Ssaidi@eecs.umich.edu assert(va == 0); 8813823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 8823823Ssaidi@eecs.umich.edu break; 8833823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8843823Ssaidi@eecs.umich.edu assert(va == 0); 8853823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 8863823Ssaidi@eecs.umich.edu break; 8873823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8883823Ssaidi@eecs.umich.edu assert(va == 0); 8893823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 8903823Ssaidi@eecs.umich.edu break; 8913823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8923823Ssaidi@eecs.umich.edu assert(va == 0); 8933823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 8943823Ssaidi@eecs.umich.edu break; 8953823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8963823Ssaidi@eecs.umich.edu assert(va == 0); 8973823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 8983823Ssaidi@eecs.umich.edu break; 8993826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9003912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9013826Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9033823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9043823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9053823Ssaidi@eecs.umich.edu break; 9063826Ssaidi@eecs.umich.edu case ASI_IMMU: 9073826Ssaidi@eecs.umich.edu switch (va) { 9083833Ssaidi@eecs.umich.edu case 0x0: 9093833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9103833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9113833Ssaidi@eecs.umich.edu break; 9123906Ssaidi@eecs.umich.edu case 0x18: 9133906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 9143906Ssaidi@eecs.umich.edu break; 9153826Ssaidi@eecs.umich.edu case 0x30: 9163826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 9173826Ssaidi@eecs.umich.edu break; 9183826Ssaidi@eecs.umich.edu default: 9193826Ssaidi@eecs.umich.edu goto doMmuReadError; 9203826Ssaidi@eecs.umich.edu } 9213826Ssaidi@eecs.umich.edu break; 9223823Ssaidi@eecs.umich.edu case ASI_DMMU: 9233823Ssaidi@eecs.umich.edu switch (va) { 9243833Ssaidi@eecs.umich.edu case 0x0: 9253833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9263833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9273833Ssaidi@eecs.umich.edu break; 9283906Ssaidi@eecs.umich.edu case 0x18: 9293906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 9303906Ssaidi@eecs.umich.edu break; 9313906Ssaidi@eecs.umich.edu case 0x20: 9323906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 9333906Ssaidi@eecs.umich.edu break; 9343826Ssaidi@eecs.umich.edu case 0x30: 9353826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 9363826Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case 0x80: 9383823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 9393823Ssaidi@eecs.umich.edu break; 9403823Ssaidi@eecs.umich.edu default: 9413823Ssaidi@eecs.umich.edu goto doMmuReadError; 9423823Ssaidi@eecs.umich.edu } 9433823Ssaidi@eecs.umich.edu break; 9443833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9453833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9463833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9473833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 9483833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9493833Ssaidi@eecs.umich.edu } else { 9503833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 9513833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9523833Ssaidi@eecs.umich.edu } 9533833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9543833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9553833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9563833Ssaidi@eecs.umich.edu pkt->set(data); 9573833Ssaidi@eecs.umich.edu break; 9583833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9593833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9603833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9613833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 9623833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9633833Ssaidi@eecs.umich.edu } else { 9643833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 9653833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9663833Ssaidi@eecs.umich.edu } 9673833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9683833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9693833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 9703910Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 9713833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9723833Ssaidi@eecs.umich.edu pkt->set(data); 9733833Ssaidi@eecs.umich.edu break; 9743899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9753899Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9763899Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9773899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); 9783899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 9793899Ssaidi@eecs.umich.edu } else { 9803899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); 9813899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 9823899Ssaidi@eecs.umich.edu } 9833899Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9843899Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9853899Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9863899Ssaidi@eecs.umich.edu pkt->set(data); 9873899Ssaidi@eecs.umich.edu break; 9883899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 9893899Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9903899Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9913899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); 9923899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 9933899Ssaidi@eecs.umich.edu } else { 9943899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); 9953899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 9963899Ssaidi@eecs.umich.edu } 9973899Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9983899Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9993899Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 10003910Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 10013899Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 10023899Ssaidi@eecs.umich.edu pkt->set(data); 10033899Ssaidi@eecs.umich.edu break; 10043833Ssaidi@eecs.umich.edu 10053823Ssaidi@eecs.umich.edu default: 10063823Ssaidi@eecs.umich.edudoMmuReadError: 10073823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10083823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10093823Ssaidi@eecs.umich.edu } 10103823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 10113823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10123806Ssaidi@eecs.umich.edu} 10133806Ssaidi@eecs.umich.edu 10143806Ssaidi@eecs.umich.eduTick 10153806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10163806Ssaidi@eecs.umich.edu{ 10173823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10183823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10193823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10203823Ssaidi@eecs.umich.edu 10213826Ssaidi@eecs.umich.edu Addr ta_insert; 10223826Ssaidi@eecs.umich.edu Addr va_insert; 10233826Ssaidi@eecs.umich.edu Addr ct_insert; 10243826Ssaidi@eecs.umich.edu int part_insert; 10253826Ssaidi@eecs.umich.edu int entry_insert = -1; 10263826Ssaidi@eecs.umich.edu bool real_insert; 10273863Ssaidi@eecs.umich.edu bool ignore; 10283863Ssaidi@eecs.umich.edu int part_id; 10293863Ssaidi@eecs.umich.edu int ctx_id; 10303826Ssaidi@eecs.umich.edu PageTableEntry pte; 10313826Ssaidi@eecs.umich.edu 10323825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10333823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10343823Ssaidi@eecs.umich.edu 10353823Ssaidi@eecs.umich.edu switch (asi) { 10363823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10373823Ssaidi@eecs.umich.edu assert(va == 0); 10383823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 10393823Ssaidi@eecs.umich.edu break; 10403823Ssaidi@eecs.umich.edu case ASI_MMU: 10413823Ssaidi@eecs.umich.edu switch (va) { 10423823Ssaidi@eecs.umich.edu case 0x8: 10433823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 10443823Ssaidi@eecs.umich.edu break; 10453823Ssaidi@eecs.umich.edu case 0x10: 10463823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 10473823Ssaidi@eecs.umich.edu break; 10483823Ssaidi@eecs.umich.edu default: 10493823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10503823Ssaidi@eecs.umich.edu } 10513823Ssaidi@eecs.umich.edu break; 10523824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10533825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10543824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 10553824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10563824Ssaidi@eecs.umich.edu break; 10573823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10583823Ssaidi@eecs.umich.edu assert(va == 0); 10593823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10623823Ssaidi@eecs.umich.edu assert(va == 0); 10633823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 10643823Ssaidi@eecs.umich.edu break; 10653823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10663823Ssaidi@eecs.umich.edu assert(va == 0); 10673823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 10683823Ssaidi@eecs.umich.edu break; 10693823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10703823Ssaidi@eecs.umich.edu assert(va == 0); 10713823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10723823Ssaidi@eecs.umich.edu break; 10733823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10743823Ssaidi@eecs.umich.edu assert(va == 0); 10753823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10763823Ssaidi@eecs.umich.edu break; 10773823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10783823Ssaidi@eecs.umich.edu assert(va == 0); 10793823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 10803823Ssaidi@eecs.umich.edu break; 10813823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10823823Ssaidi@eecs.umich.edu assert(va == 0); 10833823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 10843823Ssaidi@eecs.umich.edu break; 10853823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 10863823Ssaidi@eecs.umich.edu assert(va == 0); 10873823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 10883823Ssaidi@eecs.umich.edu break; 10893823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 10903823Ssaidi@eecs.umich.edu assert(va == 0); 10913823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 10923823Ssaidi@eecs.umich.edu break; 10933823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 10943823Ssaidi@eecs.umich.edu assert(va == 0); 10953823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 10963823Ssaidi@eecs.umich.edu break; 10973823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 10983823Ssaidi@eecs.umich.edu assert(va == 0); 10993823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 11003823Ssaidi@eecs.umich.edu break; 11013823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11023823Ssaidi@eecs.umich.edu assert(va == 0); 11033823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 11043823Ssaidi@eecs.umich.edu break; 11053825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11063825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11073825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11083825Ssaidi@eecs.umich.edu break; 11093823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11103823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11113823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11123823Ssaidi@eecs.umich.edu break; 11133826Ssaidi@eecs.umich.edu case ASI_IMMU: 11143826Ssaidi@eecs.umich.edu switch (va) { 11153906Ssaidi@eecs.umich.edu case 0x18: 11163906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 11173906Ssaidi@eecs.umich.edu break; 11183826Ssaidi@eecs.umich.edu case 0x30: 11193916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11203826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 11213826Ssaidi@eecs.umich.edu break; 11223826Ssaidi@eecs.umich.edu default: 11233826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11243826Ssaidi@eecs.umich.edu } 11253826Ssaidi@eecs.umich.edu break; 11263826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11273826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11283826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11293826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11303826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 11313826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11323826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11333826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11343826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11353826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11363826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11373826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11383826Ssaidi@eecs.umich.edu pte, entry_insert); 11393826Ssaidi@eecs.umich.edu break; 11403826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11413826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11423826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11433826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11443826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 11453826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11463826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11473826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11483826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11493826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11503826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11513826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11523826Ssaidi@eecs.umich.edu break; 11533863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11543863Ssaidi@eecs.umich.edu ignore = false; 11553863Ssaidi@eecs.umich.edu ctx_id = -1; 11563863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11573863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11583863Ssaidi@eecs.umich.edu case 0: 11593863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11603863Ssaidi@eecs.umich.edu break; 11613863Ssaidi@eecs.umich.edu case 1: 11623863Ssaidi@eecs.umich.edu ignore = true; 11633863Ssaidi@eecs.umich.edu break; 11643863Ssaidi@eecs.umich.edu case 3: 11653863Ssaidi@eecs.umich.edu ctx_id = 0; 11663863Ssaidi@eecs.umich.edu break; 11673863Ssaidi@eecs.umich.edu default: 11683863Ssaidi@eecs.umich.edu ignore = true; 11693863Ssaidi@eecs.umich.edu } 11703863Ssaidi@eecs.umich.edu 11713863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11723863Ssaidi@eecs.umich.edu case 0: // demap page 11733863Ssaidi@eecs.umich.edu if (!ignore) 11743863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11753863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11763863Ssaidi@eecs.umich.edu break; 11773863Ssaidi@eecs.umich.edu case 1: //demap context 11783863Ssaidi@eecs.umich.edu if (!ignore) 11793863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11803863Ssaidi@eecs.umich.edu break; 11813863Ssaidi@eecs.umich.edu case 2: 11823863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 11833863Ssaidi@eecs.umich.edu break; 11843863Ssaidi@eecs.umich.edu default: 11853863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11863863Ssaidi@eecs.umich.edu } 11873863Ssaidi@eecs.umich.edu break; 11883823Ssaidi@eecs.umich.edu case ASI_DMMU: 11893823Ssaidi@eecs.umich.edu switch (va) { 11903906Ssaidi@eecs.umich.edu case 0x18: 11913906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 11923906Ssaidi@eecs.umich.edu break; 11933826Ssaidi@eecs.umich.edu case 0x30: 11943916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11953826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 11963826Ssaidi@eecs.umich.edu break; 11973823Ssaidi@eecs.umich.edu case 0x80: 11983823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 11993823Ssaidi@eecs.umich.edu break; 12003823Ssaidi@eecs.umich.edu default: 12013823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12023823Ssaidi@eecs.umich.edu } 12033823Ssaidi@eecs.umich.edu break; 12043863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12053863Ssaidi@eecs.umich.edu ignore = false; 12063863Ssaidi@eecs.umich.edu ctx_id = -1; 12073863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 12083863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12093863Ssaidi@eecs.umich.edu case 0: 12103863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 12113863Ssaidi@eecs.umich.edu break; 12123863Ssaidi@eecs.umich.edu case 1: 12133863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 12143863Ssaidi@eecs.umich.edu break; 12153863Ssaidi@eecs.umich.edu case 3: 12163863Ssaidi@eecs.umich.edu ctx_id = 0; 12173863Ssaidi@eecs.umich.edu break; 12183863Ssaidi@eecs.umich.edu default: 12193863Ssaidi@eecs.umich.edu ignore = true; 12203863Ssaidi@eecs.umich.edu } 12213863Ssaidi@eecs.umich.edu 12223863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12233863Ssaidi@eecs.umich.edu case 0: // demap page 12243863Ssaidi@eecs.umich.edu if (!ignore) 12253863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12263863Ssaidi@eecs.umich.edu break; 12273863Ssaidi@eecs.umich.edu case 1: //demap context 12283863Ssaidi@eecs.umich.edu if (!ignore) 12293863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12303863Ssaidi@eecs.umich.edu break; 12313863Ssaidi@eecs.umich.edu case 2: 12323863Ssaidi@eecs.umich.edu demapAll(part_id); 12333863Ssaidi@eecs.umich.edu break; 12343863Ssaidi@eecs.umich.edu default: 12353863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12363863Ssaidi@eecs.umich.edu } 12373863Ssaidi@eecs.umich.edu break; 12383823Ssaidi@eecs.umich.edu default: 12393823Ssaidi@eecs.umich.edudoMmuWriteError: 12403823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12413823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12423823Ssaidi@eecs.umich.edu } 12433823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 12443823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12453806Ssaidi@eecs.umich.edu} 12463806Ssaidi@eecs.umich.edu 12473804Ssaidi@eecs.umich.eduvoid 12483804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 12493804Ssaidi@eecs.umich.edu{ 12504000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 12514000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 12524000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 12534000Ssaidi@eecs.umich.edu 12544000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 12554000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * size); 12564000Ssaidi@eecs.umich.edu int cntr = 0; 12574000Ssaidi@eecs.umich.edu std::list<TlbEntry*>::iterator i; 12584000Ssaidi@eecs.umich.edu i = freeList.begin(); 12594000Ssaidi@eecs.umich.edu while (i != freeList.end()) { 12604000Ssaidi@eecs.umich.edu free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 12614000Ssaidi@eecs.umich.edu i++; 12624000Ssaidi@eecs.umich.edu } 12634000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cntr); 12644000Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(free_list, cntr); 12654000Ssaidi@eecs.umich.edu 12664000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 12674000Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), x)); 12684000Ssaidi@eecs.umich.edu tlb[x].serialize(os); 12694000Ssaidi@eecs.umich.edu } 12703804Ssaidi@eecs.umich.edu} 12713804Ssaidi@eecs.umich.edu 12723804Ssaidi@eecs.umich.eduvoid 12733804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 12743804Ssaidi@eecs.umich.edu{ 12754000Ssaidi@eecs.umich.edu int oldSize; 12764000Ssaidi@eecs.umich.edu 12774000Ssaidi@eecs.umich.edu paramIn(cp, section, "size", oldSize); 12784000Ssaidi@eecs.umich.edu if (oldSize != size) 12794000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 12804000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 12814000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 12824000Ssaidi@eecs.umich.edu 12834000Ssaidi@eecs.umich.edu int cntr; 12844000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(cntr); 12854000Ssaidi@eecs.umich.edu 12864000Ssaidi@eecs.umich.edu int *free_list = (int*)malloc(sizeof(int) * cntr); 12874000Ssaidi@eecs.umich.edu freeList.clear(); 12884000Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(free_list, cntr); 12894000Ssaidi@eecs.umich.edu for (int x = 0; x < cntr; x++) 12904000Ssaidi@eecs.umich.edu freeList.push_back(&tlb[free_list[x]]); 12914000Ssaidi@eecs.umich.edu 12924000Ssaidi@eecs.umich.edu lookupTable.clear(); 12934000Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 12944000Ssaidi@eecs.umich.edu tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 12954000Ssaidi@eecs.umich.edu if (tlb[x].valid) 12964000Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 12974000Ssaidi@eecs.umich.edu 12984000Ssaidi@eecs.umich.edu } 12993804Ssaidi@eecs.umich.edu} 13003804Ssaidi@eecs.umich.edu 13013804Ssaidi@eecs.umich.edu 13023804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 13033804Ssaidi@eecs.umich.edu 13043804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 13053804Ssaidi@eecs.umich.edu 13063804Ssaidi@eecs.umich.edu Param<int> size; 13073804Ssaidi@eecs.umich.edu 13083804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 13093804Ssaidi@eecs.umich.edu 13103804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 13113804Ssaidi@eecs.umich.edu 13123804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 13133804Ssaidi@eecs.umich.edu 13143804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 13153804Ssaidi@eecs.umich.edu 13163804Ssaidi@eecs.umich.edu 13173804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 13183804Ssaidi@eecs.umich.edu{ 13193804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 13203804Ssaidi@eecs.umich.edu} 13213804Ssaidi@eecs.umich.edu 13223804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 13233804Ssaidi@eecs.umich.edu 13243804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 13253804Ssaidi@eecs.umich.edu 13263804Ssaidi@eecs.umich.edu Param<int> size; 13273804Ssaidi@eecs.umich.edu 13283804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 13293804Ssaidi@eecs.umich.edu 13303804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 13313804Ssaidi@eecs.umich.edu 13323804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 13333804Ssaidi@eecs.umich.edu 13343804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 13353804Ssaidi@eecs.umich.edu 13363804Ssaidi@eecs.umich.edu 13373804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 13383804Ssaidi@eecs.umich.edu{ 13393804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 13403804Ssaidi@eecs.umich.edu} 13413804Ssaidi@eecs.umich.edu 13423804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 13433804Ssaidi@eecs.umich.edu} 1344