tlb.cc revision 3926
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 493881Ssaidi@eecs.umich.edu cacheValid(false) 503804Ssaidi@eecs.umich.edu{ 513804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 523804Ssaidi@eecs.umich.edu if (size > 64) 533804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 543569Sgblack@eecs.umich.edu 553804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 563804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 573881Ssaidi@eecs.umich.edu 583881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 593881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 603804Ssaidi@eecs.umich.edu} 613569Sgblack@eecs.umich.edu 623804Ssaidi@eecs.umich.eduvoid 633804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 643804Ssaidi@eecs.umich.edu{ 653804Ssaidi@eecs.umich.edu MapIter i; 663881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 673804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 683804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 693804Ssaidi@eecs.umich.edu t->used = false; 703804Ssaidi@eecs.umich.edu usedEntries--; 713804Ssaidi@eecs.umich.edu } 723804Ssaidi@eecs.umich.edu } 733804Ssaidi@eecs.umich.edu} 743569Sgblack@eecs.umich.edu 753569Sgblack@eecs.umich.edu 763804Ssaidi@eecs.umich.eduvoid 773804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 783826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 793804Ssaidi@eecs.umich.edu{ 803569Sgblack@eecs.umich.edu 813569Sgblack@eecs.umich.edu 823804Ssaidi@eecs.umich.edu MapIter i; 833826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 843907Ssaidi@eecs.umich.edu// TlbRange tr; 853826Ssaidi@eecs.umich.edu int x; 863811Ssaidi@eecs.umich.edu 873836Ssaidi@eecs.umich.edu cacheValid = false; 883915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 893907Ssaidi@eecs.umich.edu /* tr.va = va; 903881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 913881Ssaidi@eecs.umich.edu tr.contextId = context_id; 923881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 933881Ssaidi@eecs.umich.edu tr.real = real; 943907Ssaidi@eecs.umich.edu*/ 953881Ssaidi@eecs.umich.edu 963881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 973881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 983881Ssaidi@eecs.umich.edu 993881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1003907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1013907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1023907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1033907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1043907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1053907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1063907Ssaidi@eecs.umich.edu { 1073907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1083907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1093907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1103907Ssaidi@eecs.umich.edu 1113907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1123907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1133907Ssaidi@eecs.umich.edu tlb[x].used = false; 1143907Ssaidi@eecs.umich.edu usedEntries--; 1153907Ssaidi@eecs.umich.edu } 1163907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1173907Ssaidi@eecs.umich.edu } 1183907Ssaidi@eecs.umich.edu } 1193907Ssaidi@eecs.umich.edu } 1203907Ssaidi@eecs.umich.edu 1213907Ssaidi@eecs.umich.edu 1223907Ssaidi@eecs.umich.edu/* 1233881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1243881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1253881Ssaidi@eecs.umich.edu i->second->valid = false; 1263881Ssaidi@eecs.umich.edu if (i->second->used) { 1273881Ssaidi@eecs.umich.edu i->second->used = false; 1283881Ssaidi@eecs.umich.edu usedEntries--; 1293881Ssaidi@eecs.umich.edu } 1303881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1313881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1323881Ssaidi@eecs.umich.edu i->second); 1333881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1343881Ssaidi@eecs.umich.edu } 1353907Ssaidi@eecs.umich.edu*/ 1363811Ssaidi@eecs.umich.edu 1373826Ssaidi@eecs.umich.edu if (entry != -1) { 1383826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1393826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1403826Ssaidi@eecs.umich.edu } else { 1413881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1423881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1433881Ssaidi@eecs.umich.edu } else { 1443881Ssaidi@eecs.umich.edu x = lastReplaced; 1453881Ssaidi@eecs.umich.edu do { 1463881Ssaidi@eecs.umich.edu ++x; 1473881Ssaidi@eecs.umich.edu if (x == size) 1483881Ssaidi@eecs.umich.edu x = 0; 1493881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1503881Ssaidi@eecs.umich.edu goto insertAllLocked; 1513881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1523881Ssaidi@eecs.umich.edu lastReplaced = x; 1533881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1543881Ssaidi@eecs.umich.edu } 1553881Ssaidi@eecs.umich.edu /* 1563826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1573826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1583826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1593826Ssaidi@eecs.umich.edu break; 1603826Ssaidi@eecs.umich.edu } 1613881Ssaidi@eecs.umich.edu }*/ 1623569Sgblack@eecs.umich.edu } 1633569Sgblack@eecs.umich.edu 1643881Ssaidi@eecs.umich.eduinsertAllLocked: 1653804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1663881Ssaidi@eecs.umich.edu if (!new_entry) { 1673826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1683881Ssaidi@eecs.umich.edu } 1693881Ssaidi@eecs.umich.edu 1703881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1713907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1723907Ssaidi@eecs.umich.edu usedEntries--; 1733907Ssaidi@eecs.umich.edu 1743907Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1753907Ssaidi@eecs.umich.edu 1763907Ssaidi@eecs.umich.edu 1773881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Using entry: %#X\n", new_entry); 1783569Sgblack@eecs.umich.edu 1793804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1803804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1813881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1823804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1833804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1843804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1853804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1863804Ssaidi@eecs.umich.edu new_entry->used = true;; 1873804Ssaidi@eecs.umich.edu new_entry->valid = true; 1883804Ssaidi@eecs.umich.edu usedEntries++; 1893569Sgblack@eecs.umich.edu 1903569Sgblack@eecs.umich.edu 1913569Sgblack@eecs.umich.edu 1923863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1933863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1943804Ssaidi@eecs.umich.edu 1953804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1963804Ssaidi@eecs.umich.edu // one we just inserted 1973804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1983804Ssaidi@eecs.umich.edu clearUsedBits(); 1993804Ssaidi@eecs.umich.edu new_entry->used = true; 2003804Ssaidi@eecs.umich.edu usedEntries++; 2013804Ssaidi@eecs.umich.edu } 2023804Ssaidi@eecs.umich.edu 2033569Sgblack@eecs.umich.edu} 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.edu 2063804Ssaidi@eecs.umich.eduTlbEntry* 2073804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 2083804Ssaidi@eecs.umich.edu{ 2093804Ssaidi@eecs.umich.edu MapIter i; 2103804Ssaidi@eecs.umich.edu TlbRange tr; 2113804Ssaidi@eecs.umich.edu TlbEntry *t; 2123804Ssaidi@eecs.umich.edu 2133811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2143811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2153804Ssaidi@eecs.umich.edu // Assemble full address structure 2163804Ssaidi@eecs.umich.edu tr.va = va; 2173863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2183804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2193804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2203804Ssaidi@eecs.umich.edu tr.real = real; 2213804Ssaidi@eecs.umich.edu 2223804Ssaidi@eecs.umich.edu // Try to find the entry 2233804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2243804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2253811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2263804Ssaidi@eecs.umich.edu return NULL; 2273804Ssaidi@eecs.umich.edu } 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2303804Ssaidi@eecs.umich.edu t = i->second; 2313826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2323826Ssaidi@eecs.umich.edu t->pte.size()); 2333804Ssaidi@eecs.umich.edu if (!t->used) { 2343804Ssaidi@eecs.umich.edu t->used = true; 2353804Ssaidi@eecs.umich.edu usedEntries++; 2363804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2373804Ssaidi@eecs.umich.edu clearUsedBits(); 2383804Ssaidi@eecs.umich.edu t->used = true; 2393804Ssaidi@eecs.umich.edu usedEntries++; 2403804Ssaidi@eecs.umich.edu } 2413804Ssaidi@eecs.umich.edu } 2423804Ssaidi@eecs.umich.edu 2433804Ssaidi@eecs.umich.edu return t; 2443804Ssaidi@eecs.umich.edu} 2453804Ssaidi@eecs.umich.edu 2463826Ssaidi@eecs.umich.eduvoid 2473826Ssaidi@eecs.umich.eduTLB::dumpAll() 2483826Ssaidi@eecs.umich.edu{ 2493863Ssaidi@eecs.umich.edu MapIter i; 2503826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2513826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2523826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2533826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2543826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2553826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2563826Ssaidi@eecs.umich.edu } 2573826Ssaidi@eecs.umich.edu } 2583826Ssaidi@eecs.umich.edu} 2593804Ssaidi@eecs.umich.edu 2603804Ssaidi@eecs.umich.eduvoid 2613804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2623804Ssaidi@eecs.umich.edu{ 2633804Ssaidi@eecs.umich.edu TlbRange tr; 2643804Ssaidi@eecs.umich.edu MapIter i; 2653804Ssaidi@eecs.umich.edu 2663863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2673863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2683863Ssaidi@eecs.umich.edu 2693836Ssaidi@eecs.umich.edu cacheValid = false; 2703836Ssaidi@eecs.umich.edu 2713804Ssaidi@eecs.umich.edu // Assemble full address structure 2723804Ssaidi@eecs.umich.edu tr.va = va; 2733863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2743804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2753804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2763804Ssaidi@eecs.umich.edu tr.real = real; 2773804Ssaidi@eecs.umich.edu 2783804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2793804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2803804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2813863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2823804Ssaidi@eecs.umich.edu i->second->valid = false; 2833804Ssaidi@eecs.umich.edu if (i->second->used) { 2843804Ssaidi@eecs.umich.edu i->second->used = false; 2853804Ssaidi@eecs.umich.edu usedEntries--; 2863804Ssaidi@eecs.umich.edu } 2873881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2883881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second); 2893804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2903804Ssaidi@eecs.umich.edu } 2913804Ssaidi@eecs.umich.edu} 2923804Ssaidi@eecs.umich.edu 2933804Ssaidi@eecs.umich.eduvoid 2943804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2953804Ssaidi@eecs.umich.edu{ 2963804Ssaidi@eecs.umich.edu int x; 2973863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2983863Ssaidi@eecs.umich.edu partition_id, context_id); 2993836Ssaidi@eecs.umich.edu cacheValid = false; 3003804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3013804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3023804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3033881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3043881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3053881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]); 3063881Ssaidi@eecs.umich.edu } 3073804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3083804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3093804Ssaidi@eecs.umich.edu tlb[x].used = false; 3103804Ssaidi@eecs.umich.edu usedEntries--; 3113804Ssaidi@eecs.umich.edu } 3123804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3133804Ssaidi@eecs.umich.edu } 3143804Ssaidi@eecs.umich.edu } 3153804Ssaidi@eecs.umich.edu} 3163804Ssaidi@eecs.umich.edu 3173804Ssaidi@eecs.umich.eduvoid 3183804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3193804Ssaidi@eecs.umich.edu{ 3203804Ssaidi@eecs.umich.edu int x; 3213863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3223836Ssaidi@eecs.umich.edu cacheValid = false; 3233804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3243804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3253881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3263881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3273881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]); 3283881Ssaidi@eecs.umich.edu } 3293804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3303804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3313804Ssaidi@eecs.umich.edu tlb[x].used = false; 3323804Ssaidi@eecs.umich.edu usedEntries--; 3333804Ssaidi@eecs.umich.edu } 3343804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3353804Ssaidi@eecs.umich.edu } 3363804Ssaidi@eecs.umich.edu } 3373804Ssaidi@eecs.umich.edu} 3383804Ssaidi@eecs.umich.edu 3393804Ssaidi@eecs.umich.eduvoid 3403804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3413804Ssaidi@eecs.umich.edu{ 3423804Ssaidi@eecs.umich.edu int x; 3433836Ssaidi@eecs.umich.edu cacheValid = false; 3443836Ssaidi@eecs.umich.edu 3453881Ssaidi@eecs.umich.edu freeList.clear(); 3463907Ssaidi@eecs.umich.edu lookupTable.clear(); 3473804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3483881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3493881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3503804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3513907Ssaidi@eecs.umich.edu tlb[x].used = false; 3523804Ssaidi@eecs.umich.edu } 3533804Ssaidi@eecs.umich.edu usedEntries = 0; 3543804Ssaidi@eecs.umich.edu} 3553804Ssaidi@eecs.umich.edu 3563804Ssaidi@eecs.umich.eduuint64_t 3573804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3583881Ssaidi@eecs.umich.edu if (entry >= size) 3593881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3603881Ssaidi@eecs.umich.edu 3613804Ssaidi@eecs.umich.edu assert(entry < size); 3623881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3633881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3643881Ssaidi@eecs.umich.edu else 3653881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3663804Ssaidi@eecs.umich.edu} 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.eduuint64_t 3693804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3703804Ssaidi@eecs.umich.edu assert(entry < size); 3713804Ssaidi@eecs.umich.edu uint64_t tag; 3723881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3733881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3743804Ssaidi@eecs.umich.edu 3753881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3763881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3773881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3783804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3793804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3803804Ssaidi@eecs.umich.edu return tag; 3813804Ssaidi@eecs.umich.edu} 3823804Ssaidi@eecs.umich.edu 3833804Ssaidi@eecs.umich.edubool 3843804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3853804Ssaidi@eecs.umich.edu{ 3863804Ssaidi@eecs.umich.edu if (am) 3873804Ssaidi@eecs.umich.edu return true; 3883804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3893804Ssaidi@eecs.umich.edu return false; 3903804Ssaidi@eecs.umich.edu return true; 3913804Ssaidi@eecs.umich.edu} 3923804Ssaidi@eecs.umich.edu 3933804Ssaidi@eecs.umich.eduvoid 3943804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3953804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3963804Ssaidi@eecs.umich.edu{ 3973804Ssaidi@eecs.umich.edu uint64_t sfsr; 3983804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3993804Ssaidi@eecs.umich.edu 4003804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4013804Ssaidi@eecs.umich.edu sfsr = 0x3; 4023804Ssaidi@eecs.umich.edu else 4033804Ssaidi@eecs.umich.edu sfsr = 1; 4043804Ssaidi@eecs.umich.edu 4053804Ssaidi@eecs.umich.edu if (write) 4063804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4073804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4083804Ssaidi@eecs.umich.edu if (se) 4093804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4103804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4113804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4123826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 4133804Ssaidi@eecs.umich.edu} 4143804Ssaidi@eecs.umich.edu 4153826Ssaidi@eecs.umich.eduvoid 4163826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 4173826Ssaidi@eecs.umich.edu{ 4183916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4193916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4203916Ssaidi@eecs.umich.edu 4213826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 4223826Ssaidi@eecs.umich.edu} 4233804Ssaidi@eecs.umich.edu 4243804Ssaidi@eecs.umich.eduvoid 4253804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 4263804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4273804Ssaidi@eecs.umich.edu{ 4283811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4293811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4303804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 4313804Ssaidi@eecs.umich.edu} 4323804Ssaidi@eecs.umich.edu 4333804Ssaidi@eecs.umich.eduvoid 4343826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4353826Ssaidi@eecs.umich.edu{ 4363826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4373826Ssaidi@eecs.umich.edu} 4383826Ssaidi@eecs.umich.edu 4393826Ssaidi@eecs.umich.eduvoid 4403804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4413804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4423804Ssaidi@eecs.umich.edu{ 4433811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4443811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4453804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4463826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 4473804Ssaidi@eecs.umich.edu} 4483804Ssaidi@eecs.umich.edu 4493836Ssaidi@eecs.umich.eduvoid 4503826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4513826Ssaidi@eecs.umich.edu{ 4523826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4533826Ssaidi@eecs.umich.edu} 4543826Ssaidi@eecs.umich.edu 4553826Ssaidi@eecs.umich.edu 4563804Ssaidi@eecs.umich.edu 4573804Ssaidi@eecs.umich.eduFault 4583804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4593804Ssaidi@eecs.umich.edu{ 4603833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4613833Ssaidi@eecs.umich.edu 4623836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4633836Ssaidi@eecs.umich.edu TlbEntry *e; 4643836Ssaidi@eecs.umich.edu 4653836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4663836Ssaidi@eecs.umich.edu 4673836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4683836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4693836Ssaidi@eecs.umich.edu 4703836Ssaidi@eecs.umich.edu // Be fast if we can! 4713836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4723836Ssaidi@eecs.umich.edu if (cacheEntry) { 4733836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4743836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4753836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4763836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4773836Ssaidi@eecs.umich.edu return NoFault; 4783836Ssaidi@eecs.umich.edu } 4793836Ssaidi@eecs.umich.edu } else { 4803836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4813836Ssaidi@eecs.umich.edu return NoFault; 4823836Ssaidi@eecs.umich.edu } 4833836Ssaidi@eecs.umich.edu } 4843836Ssaidi@eecs.umich.edu 4853833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4863833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4873833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4883833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4893833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4903833Ssaidi@eecs.umich.edu 4913833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4923833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4933833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4943804Ssaidi@eecs.umich.edu int context; 4953804Ssaidi@eecs.umich.edu ContextType ct; 4963804Ssaidi@eecs.umich.edu int asi; 4973804Ssaidi@eecs.umich.edu bool real = false; 4983804Ssaidi@eecs.umich.edu 4993833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 5003833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 5013811Ssaidi@eecs.umich.edu 5023804Ssaidi@eecs.umich.edu if (tl > 0) { 5033804Ssaidi@eecs.umich.edu asi = ASI_N; 5043804Ssaidi@eecs.umich.edu ct = Nucleus; 5053804Ssaidi@eecs.umich.edu context = 0; 5063804Ssaidi@eecs.umich.edu } else { 5073804Ssaidi@eecs.umich.edu asi = ASI_P; 5083804Ssaidi@eecs.umich.edu ct = Primary; 5093833Ssaidi@eecs.umich.edu context = pri_context; 5103804Ssaidi@eecs.umich.edu } 5113804Ssaidi@eecs.umich.edu 5123833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5133836Ssaidi@eecs.umich.edu cacheValid = true; 5143836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5153836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5163836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5173804Ssaidi@eecs.umich.edu return NoFault; 5183804Ssaidi@eecs.umich.edu } 5193804Ssaidi@eecs.umich.edu 5203836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5213836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5223804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 5233804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5243804Ssaidi@eecs.umich.edu } 5253804Ssaidi@eecs.umich.edu 5263804Ssaidi@eecs.umich.edu if (addr_mask) 5273804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5283804Ssaidi@eecs.umich.edu 5293804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5303804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 5313804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5323804Ssaidi@eecs.umich.edu } 5333804Ssaidi@eecs.umich.edu 5343833Ssaidi@eecs.umich.edu if (!lsu_im) { 5353836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5363804Ssaidi@eecs.umich.edu real = true; 5373804Ssaidi@eecs.umich.edu context = 0; 5383804Ssaidi@eecs.umich.edu } else { 5393804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5403804Ssaidi@eecs.umich.edu } 5413804Ssaidi@eecs.umich.edu 5423804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5433916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 5443804Ssaidi@eecs.umich.edu if (real) 5453804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5463804Ssaidi@eecs.umich.edu else 5473804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5483804Ssaidi@eecs.umich.edu } 5493804Ssaidi@eecs.umich.edu 5503804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5513804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5523804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5533804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5543804Ssaidi@eecs.umich.edu } 5553804Ssaidi@eecs.umich.edu 5563836Ssaidi@eecs.umich.edu // cache translation date for next translation 5573836Ssaidi@eecs.umich.edu cacheValid = true; 5583836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5593836Ssaidi@eecs.umich.edu cacheEntry = e; 5603836Ssaidi@eecs.umich.edu 5613826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5623836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5633836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5643804Ssaidi@eecs.umich.edu return NoFault; 5653804Ssaidi@eecs.umich.edu} 5663804Ssaidi@eecs.umich.edu 5673804Ssaidi@eecs.umich.edu 5683804Ssaidi@eecs.umich.edu 5693804Ssaidi@eecs.umich.eduFault 5703804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5713804Ssaidi@eecs.umich.edu{ 5723804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5733833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 5743836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5753836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5763836Ssaidi@eecs.umich.edu ASI asi; 5773836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5783836Ssaidi@eecs.umich.edu bool implicit = false; 5793836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5803833Ssaidi@eecs.umich.edu 5813836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5823836Ssaidi@eecs.umich.edu vaddr, size, asi); 5833836Ssaidi@eecs.umich.edu 5843836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5853836Ssaidi@eecs.umich.edu implicit = true; 5863836Ssaidi@eecs.umich.edu 5873836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5883836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5893836Ssaidi@eecs.umich.edu return NoFault; 5903836Ssaidi@eecs.umich.edu } 5913836Ssaidi@eecs.umich.edu 5923836Ssaidi@eecs.umich.edu // Be fast if we can! 5933836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5943836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 5953881Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) { 5963836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 5973836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 5983836Ssaidi@eecs.umich.edu return NoFault; 5993836Ssaidi@eecs.umich.edu } 6003836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 6013881Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) { 6023836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 6033836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 6043836Ssaidi@eecs.umich.edu return NoFault; 6053836Ssaidi@eecs.umich.edu } 6063836Ssaidi@eecs.umich.edu } 6073836Ssaidi@eecs.umich.edu 6083833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6093833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6103833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6113833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6123833Ssaidi@eecs.umich.edu 6133833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6143833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6153833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6163916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6173833Ssaidi@eecs.umich.edu 6183804Ssaidi@eecs.umich.edu bool real = false; 6193832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6203832Ssaidi@eecs.umich.edu int context = 0; 6213804Ssaidi@eecs.umich.edu 6223804Ssaidi@eecs.umich.edu TlbEntry *e; 6233804Ssaidi@eecs.umich.edu 6243833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6253833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6263804Ssaidi@eecs.umich.edu 6273804Ssaidi@eecs.umich.edu if (implicit) { 6283804Ssaidi@eecs.umich.edu if (tl > 0) { 6293804Ssaidi@eecs.umich.edu asi = ASI_N; 6303804Ssaidi@eecs.umich.edu ct = Nucleus; 6313804Ssaidi@eecs.umich.edu context = 0; 6323804Ssaidi@eecs.umich.edu } else { 6333804Ssaidi@eecs.umich.edu asi = ASI_P; 6343804Ssaidi@eecs.umich.edu ct = Primary; 6353833Ssaidi@eecs.umich.edu context = pri_context; 6363804Ssaidi@eecs.umich.edu } 6373910Ssaidi@eecs.umich.edu } else { 6383804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6393910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6403804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6413804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6423804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6433804Ssaidi@eecs.umich.edu } 6443910Ssaidi@eecs.umich.edu 6453910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6463804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6473804Ssaidi@eecs.umich.edu return new DataAccessException; 6483804Ssaidi@eecs.umich.edu } 6493804Ssaidi@eecs.umich.edu 6503910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6513910Ssaidi@eecs.umich.edu context = pri_context; 6523910Ssaidi@eecs.umich.edu ct = Primary; 6533910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6543910Ssaidi@eecs.umich.edu context = sec_context; 6553910Ssaidi@eecs.umich.edu ct = Secondary; 6563910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6573910Ssaidi@eecs.umich.edu ct = Nucleus; 6583910Ssaidi@eecs.umich.edu context = 0; 6593910Ssaidi@eecs.umich.edu } else { // ???? 6603910Ssaidi@eecs.umich.edu ct = Primary; 6613910Ssaidi@eecs.umich.edu context = pri_context; 6623910Ssaidi@eecs.umich.edu } 6633902Ssaidi@eecs.umich.edu } 6643804Ssaidi@eecs.umich.edu 6653926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6663804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6673804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6683804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 6693804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 6703804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 6713804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 6723910Ssaidi@eecs.umich.edu 6733804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6743804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6753824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6763824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 6773823Ssaidi@eecs.umich.edu 6783804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6793804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6803804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6813804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6823824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6833824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6843825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6853825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6863823Ssaidi@eecs.umich.edu 6873926Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 6883926Ssaidi@eecs.umich.edu !AsiIsTwin(asi)) 6893823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6903804Ssaidi@eecs.umich.edu } 6913804Ssaidi@eecs.umich.edu 6923826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6933826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6943826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 6953826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6963826Ssaidi@eecs.umich.edu } 6973826Ssaidi@eecs.umich.edu 6983826Ssaidi@eecs.umich.edu if (addr_mask) 6993826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7003826Ssaidi@eecs.umich.edu 7013826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7023826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 7033826Ssaidi@eecs.umich.edu return new DataAccessException; 7043826Ssaidi@eecs.umich.edu } 7053826Ssaidi@eecs.umich.edu 7063826Ssaidi@eecs.umich.edu 7073910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7083804Ssaidi@eecs.umich.edu real = true; 7093804Ssaidi@eecs.umich.edu context = 0; 7103804Ssaidi@eecs.umich.edu }; 7113804Ssaidi@eecs.umich.edu 7123804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7133836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7143804Ssaidi@eecs.umich.edu return NoFault; 7153804Ssaidi@eecs.umich.edu } 7163804Ssaidi@eecs.umich.edu 7173836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7183804Ssaidi@eecs.umich.edu 7193804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7203916Ssaidi@eecs.umich.edu writeTagAccess(tc, vaddr, context); 7213811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7223804Ssaidi@eecs.umich.edu if (real) 7233804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7243804Ssaidi@eecs.umich.edu else 7253804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7263804Ssaidi@eecs.umich.edu 7273804Ssaidi@eecs.umich.edu } 7283804Ssaidi@eecs.umich.edu 7293804Ssaidi@eecs.umich.edu 7303804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7313804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7323804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7333804Ssaidi@eecs.umich.edu } 7343804Ssaidi@eecs.umich.edu 7353804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7363804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7373804Ssaidi@eecs.umich.edu return new DataAccessException; 7383804Ssaidi@eecs.umich.edu } 7393804Ssaidi@eecs.umich.edu 7403804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 7413804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7423804Ssaidi@eecs.umich.edu 7433804Ssaidi@eecs.umich.edu 7443804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7453804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7463804Ssaidi@eecs.umich.edu return new DataAccessException; 7473804Ssaidi@eecs.umich.edu } 7483804Ssaidi@eecs.umich.edu 7493836Ssaidi@eecs.umich.edu // cache translation date for next translation 7503836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7513881Ssaidi@eecs.umich.edu if (!cacheValid) { 7523881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7533881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7543881Ssaidi@eecs.umich.edu } 7553881Ssaidi@eecs.umich.edu 7563836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7573836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7583836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7593836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7603836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7613836Ssaidi@eecs.umich.edu if (implicit) 7623836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7633836Ssaidi@eecs.umich.edu } 7643881Ssaidi@eecs.umich.edu cacheValid = true; 7653826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7663836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7673836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7683804Ssaidi@eecs.umich.edu return NoFault; 7693806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7703804Ssaidi@eecs.umich.edu 7713806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7723806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7733806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7743806Ssaidi@eecs.umich.edu return new DataAccessException; 7753806Ssaidi@eecs.umich.edu } 7763824Ssaidi@eecs.umich.edu goto regAccessOk; 7773824Ssaidi@eecs.umich.edu 7783824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7793824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7803824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7813824Ssaidi@eecs.umich.edu return new PrivilegedAction; 7823824Ssaidi@eecs.umich.edu } 7833881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 7843824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7853824Ssaidi@eecs.umich.edu return new DataAccessException; 7863824Ssaidi@eecs.umich.edu } 7873824Ssaidi@eecs.umich.edu goto regAccessOk; 7883824Ssaidi@eecs.umich.edu 7893825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 7903825Ssaidi@eecs.umich.edu if (!hpriv) { 7913825Ssaidi@eecs.umich.edu if (priv) { 7923825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7933825Ssaidi@eecs.umich.edu return new DataAccessException; 7943825Ssaidi@eecs.umich.edu } else { 7953825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7963825Ssaidi@eecs.umich.edu return new PrivilegedAction; 7973825Ssaidi@eecs.umich.edu } 7983825Ssaidi@eecs.umich.edu } 7993825Ssaidi@eecs.umich.edu goto regAccessOk; 8003825Ssaidi@eecs.umich.edu 8013825Ssaidi@eecs.umich.edu 8023824Ssaidi@eecs.umich.eduregAccessOk: 8033804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8043811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8053806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8063806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8073806Ssaidi@eecs.umich.edu return NoFault; 8083804Ssaidi@eecs.umich.edu}; 8093804Ssaidi@eecs.umich.edu 8103806Ssaidi@eecs.umich.eduTick 8113806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8123806Ssaidi@eecs.umich.edu{ 8133823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8143823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8153833Ssaidi@eecs.umich.edu uint64_t temp, data; 8163833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 8173823Ssaidi@eecs.umich.edu 8183823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8193823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8203823Ssaidi@eecs.umich.edu 8213823Ssaidi@eecs.umich.edu switch (asi) { 8223823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8233823Ssaidi@eecs.umich.edu assert(va == 0); 8243823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 8253823Ssaidi@eecs.umich.edu break; 8263823Ssaidi@eecs.umich.edu case ASI_MMU: 8273823Ssaidi@eecs.umich.edu switch (va) { 8283823Ssaidi@eecs.umich.edu case 0x8: 8293823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 8303823Ssaidi@eecs.umich.edu break; 8313823Ssaidi@eecs.umich.edu case 0x10: 8323823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 8333823Ssaidi@eecs.umich.edu break; 8343823Ssaidi@eecs.umich.edu default: 8353823Ssaidi@eecs.umich.edu goto doMmuReadError; 8363823Ssaidi@eecs.umich.edu } 8373823Ssaidi@eecs.umich.edu break; 8383824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8393824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8403824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8413824Ssaidi@eecs.umich.edu break; 8423823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8433823Ssaidi@eecs.umich.edu assert(va == 0); 8443823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8453823Ssaidi@eecs.umich.edu break; 8463823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8473823Ssaidi@eecs.umich.edu assert(va == 0); 8483823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 8493823Ssaidi@eecs.umich.edu break; 8503823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8513823Ssaidi@eecs.umich.edu assert(va == 0); 8523823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 8533823Ssaidi@eecs.umich.edu break; 8543823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8553823Ssaidi@eecs.umich.edu assert(va == 0); 8563823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 8573823Ssaidi@eecs.umich.edu break; 8583823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8593823Ssaidi@eecs.umich.edu assert(va == 0); 8603823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 8613823Ssaidi@eecs.umich.edu break; 8623823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8633823Ssaidi@eecs.umich.edu assert(va == 0); 8643823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 8653823Ssaidi@eecs.umich.edu break; 8663823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8673823Ssaidi@eecs.umich.edu assert(va == 0); 8683823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 8693823Ssaidi@eecs.umich.edu break; 8703823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8713823Ssaidi@eecs.umich.edu assert(va == 0); 8723823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 8733823Ssaidi@eecs.umich.edu break; 8743823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8753823Ssaidi@eecs.umich.edu assert(va == 0); 8763823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 8773823Ssaidi@eecs.umich.edu break; 8783823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8793823Ssaidi@eecs.umich.edu assert(va == 0); 8803823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8833823Ssaidi@eecs.umich.edu assert(va == 0); 8843823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 8853823Ssaidi@eecs.umich.edu break; 8863823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8873823Ssaidi@eecs.umich.edu assert(va == 0); 8883823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 8893823Ssaidi@eecs.umich.edu break; 8903826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 8913826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 8923912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 8933826Ssaidi@eecs.umich.edu break; 8943823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 8953823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 8963823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 8973823Ssaidi@eecs.umich.edu break; 8983826Ssaidi@eecs.umich.edu case ASI_IMMU: 8993826Ssaidi@eecs.umich.edu switch (va) { 9003833Ssaidi@eecs.umich.edu case 0x0: 9013833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9023833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9033833Ssaidi@eecs.umich.edu break; 9043906Ssaidi@eecs.umich.edu case 0x18: 9053906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 9063906Ssaidi@eecs.umich.edu break; 9073826Ssaidi@eecs.umich.edu case 0x30: 9083826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 9093826Ssaidi@eecs.umich.edu break; 9103826Ssaidi@eecs.umich.edu default: 9113826Ssaidi@eecs.umich.edu goto doMmuReadError; 9123826Ssaidi@eecs.umich.edu } 9133826Ssaidi@eecs.umich.edu break; 9143823Ssaidi@eecs.umich.edu case ASI_DMMU: 9153823Ssaidi@eecs.umich.edu switch (va) { 9163833Ssaidi@eecs.umich.edu case 0x0: 9173833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9183833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9193833Ssaidi@eecs.umich.edu break; 9203906Ssaidi@eecs.umich.edu case 0x18: 9213906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 9223906Ssaidi@eecs.umich.edu break; 9233906Ssaidi@eecs.umich.edu case 0x20: 9243906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 9253906Ssaidi@eecs.umich.edu break; 9263826Ssaidi@eecs.umich.edu case 0x30: 9273826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 9283826Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case 0x80: 9303823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 9313823Ssaidi@eecs.umich.edu break; 9323823Ssaidi@eecs.umich.edu default: 9333823Ssaidi@eecs.umich.edu goto doMmuReadError; 9343823Ssaidi@eecs.umich.edu } 9353823Ssaidi@eecs.umich.edu break; 9363833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9373833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9383833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9393833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 9403833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9413833Ssaidi@eecs.umich.edu } else { 9423833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 9433833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9443833Ssaidi@eecs.umich.edu } 9453833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9463833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9473833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9483833Ssaidi@eecs.umich.edu pkt->set(data); 9493833Ssaidi@eecs.umich.edu break; 9503833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9513833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9523833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9533833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 9543833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9553833Ssaidi@eecs.umich.edu } else { 9563833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 9573833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9583833Ssaidi@eecs.umich.edu } 9593833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9603833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9613833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 9623910Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 9633833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9643833Ssaidi@eecs.umich.edu pkt->set(data); 9653833Ssaidi@eecs.umich.edu break; 9663899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9673899Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9683899Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9693899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); 9703899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 9713899Ssaidi@eecs.umich.edu } else { 9723899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); 9733899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 9743899Ssaidi@eecs.umich.edu } 9753899Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9763899Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9773899Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9783899Ssaidi@eecs.umich.edu pkt->set(data); 9793899Ssaidi@eecs.umich.edu break; 9803899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 9813899Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9823899Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9833899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); 9843899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 9853899Ssaidi@eecs.umich.edu } else { 9863899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); 9873899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 9883899Ssaidi@eecs.umich.edu } 9893899Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9903899Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9913899Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 9923910Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 9933899Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9943899Ssaidi@eecs.umich.edu pkt->set(data); 9953899Ssaidi@eecs.umich.edu break; 9963833Ssaidi@eecs.umich.edu 9973823Ssaidi@eecs.umich.edu default: 9983823Ssaidi@eecs.umich.edudoMmuReadError: 9993823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10003823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10013823Ssaidi@eecs.umich.edu } 10023823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 10033823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10043806Ssaidi@eecs.umich.edu} 10053806Ssaidi@eecs.umich.edu 10063806Ssaidi@eecs.umich.eduTick 10073806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10083806Ssaidi@eecs.umich.edu{ 10093823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10103823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10113823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10123823Ssaidi@eecs.umich.edu 10133826Ssaidi@eecs.umich.edu Addr ta_insert; 10143826Ssaidi@eecs.umich.edu Addr va_insert; 10153826Ssaidi@eecs.umich.edu Addr ct_insert; 10163826Ssaidi@eecs.umich.edu int part_insert; 10173826Ssaidi@eecs.umich.edu int entry_insert = -1; 10183826Ssaidi@eecs.umich.edu bool real_insert; 10193863Ssaidi@eecs.umich.edu bool ignore; 10203863Ssaidi@eecs.umich.edu int part_id; 10213863Ssaidi@eecs.umich.edu int ctx_id; 10223826Ssaidi@eecs.umich.edu PageTableEntry pte; 10233826Ssaidi@eecs.umich.edu 10243825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10253823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10263823Ssaidi@eecs.umich.edu 10273823Ssaidi@eecs.umich.edu switch (asi) { 10283823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10293823Ssaidi@eecs.umich.edu assert(va == 0); 10303823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 10313823Ssaidi@eecs.umich.edu break; 10323823Ssaidi@eecs.umich.edu case ASI_MMU: 10333823Ssaidi@eecs.umich.edu switch (va) { 10343823Ssaidi@eecs.umich.edu case 0x8: 10353823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 10363823Ssaidi@eecs.umich.edu break; 10373823Ssaidi@eecs.umich.edu case 0x10: 10383823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 10393823Ssaidi@eecs.umich.edu break; 10403823Ssaidi@eecs.umich.edu default: 10413823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10423823Ssaidi@eecs.umich.edu } 10433823Ssaidi@eecs.umich.edu break; 10443824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10453825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10463824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 10473824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10483824Ssaidi@eecs.umich.edu break; 10493823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10503823Ssaidi@eecs.umich.edu assert(va == 0); 10513823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 10523823Ssaidi@eecs.umich.edu break; 10533823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10543823Ssaidi@eecs.umich.edu assert(va == 0); 10553823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 10563823Ssaidi@eecs.umich.edu break; 10573823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10583823Ssaidi@eecs.umich.edu assert(va == 0); 10593823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 10603823Ssaidi@eecs.umich.edu break; 10613823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10623823Ssaidi@eecs.umich.edu assert(va == 0); 10633823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10643823Ssaidi@eecs.umich.edu break; 10653823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10663823Ssaidi@eecs.umich.edu assert(va == 0); 10673823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10683823Ssaidi@eecs.umich.edu break; 10693823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10703823Ssaidi@eecs.umich.edu assert(va == 0); 10713823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 10723823Ssaidi@eecs.umich.edu break; 10733823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10743823Ssaidi@eecs.umich.edu assert(va == 0); 10753823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 10763823Ssaidi@eecs.umich.edu break; 10773823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 10783823Ssaidi@eecs.umich.edu assert(va == 0); 10793823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 10803823Ssaidi@eecs.umich.edu break; 10813823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 10823823Ssaidi@eecs.umich.edu assert(va == 0); 10833823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 10843823Ssaidi@eecs.umich.edu break; 10853823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 10863823Ssaidi@eecs.umich.edu assert(va == 0); 10873823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 10883823Ssaidi@eecs.umich.edu break; 10893823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 10903823Ssaidi@eecs.umich.edu assert(va == 0); 10913823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 10923823Ssaidi@eecs.umich.edu break; 10933823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 10943823Ssaidi@eecs.umich.edu assert(va == 0); 10953823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 10963823Ssaidi@eecs.umich.edu break; 10973825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 10983825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 10993825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11003825Ssaidi@eecs.umich.edu break; 11013823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11023823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11033823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11043823Ssaidi@eecs.umich.edu break; 11053826Ssaidi@eecs.umich.edu case ASI_IMMU: 11063826Ssaidi@eecs.umich.edu switch (va) { 11073906Ssaidi@eecs.umich.edu case 0x18: 11083906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 11093906Ssaidi@eecs.umich.edu break; 11103826Ssaidi@eecs.umich.edu case 0x30: 11113916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11123826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 11133826Ssaidi@eecs.umich.edu break; 11143826Ssaidi@eecs.umich.edu default: 11153826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11163826Ssaidi@eecs.umich.edu } 11173826Ssaidi@eecs.umich.edu break; 11183826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11193826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11203826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11213826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11223826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 11233826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11243826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11253826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11263826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11273826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11283826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11293826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11303826Ssaidi@eecs.umich.edu pte, entry_insert); 11313826Ssaidi@eecs.umich.edu break; 11323826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11333826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11343826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11353826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11363826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 11373826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11383826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11393826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11403826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11413826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11423826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11433826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11443826Ssaidi@eecs.umich.edu break; 11453863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11463863Ssaidi@eecs.umich.edu ignore = false; 11473863Ssaidi@eecs.umich.edu ctx_id = -1; 11483863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11493863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11503863Ssaidi@eecs.umich.edu case 0: 11513863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11523863Ssaidi@eecs.umich.edu break; 11533863Ssaidi@eecs.umich.edu case 1: 11543863Ssaidi@eecs.umich.edu ignore = true; 11553863Ssaidi@eecs.umich.edu break; 11563863Ssaidi@eecs.umich.edu case 3: 11573863Ssaidi@eecs.umich.edu ctx_id = 0; 11583863Ssaidi@eecs.umich.edu break; 11593863Ssaidi@eecs.umich.edu default: 11603863Ssaidi@eecs.umich.edu ignore = true; 11613863Ssaidi@eecs.umich.edu } 11623863Ssaidi@eecs.umich.edu 11633863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11643863Ssaidi@eecs.umich.edu case 0: // demap page 11653863Ssaidi@eecs.umich.edu if (!ignore) 11663863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11673863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11683863Ssaidi@eecs.umich.edu break; 11693863Ssaidi@eecs.umich.edu case 1: //demap context 11703863Ssaidi@eecs.umich.edu if (!ignore) 11713863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11723863Ssaidi@eecs.umich.edu break; 11733863Ssaidi@eecs.umich.edu case 2: 11743863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 11753863Ssaidi@eecs.umich.edu break; 11763863Ssaidi@eecs.umich.edu default: 11773863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11783863Ssaidi@eecs.umich.edu } 11793863Ssaidi@eecs.umich.edu break; 11803823Ssaidi@eecs.umich.edu case ASI_DMMU: 11813823Ssaidi@eecs.umich.edu switch (va) { 11823906Ssaidi@eecs.umich.edu case 0x18: 11833906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 11843906Ssaidi@eecs.umich.edu break; 11853826Ssaidi@eecs.umich.edu case 0x30: 11863916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11873826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 11883826Ssaidi@eecs.umich.edu break; 11893823Ssaidi@eecs.umich.edu case 0x80: 11903823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 11913823Ssaidi@eecs.umich.edu break; 11923823Ssaidi@eecs.umich.edu default: 11933823Ssaidi@eecs.umich.edu goto doMmuWriteError; 11943823Ssaidi@eecs.umich.edu } 11953823Ssaidi@eecs.umich.edu break; 11963863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 11973863Ssaidi@eecs.umich.edu ignore = false; 11983863Ssaidi@eecs.umich.edu ctx_id = -1; 11993863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 12003863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12013863Ssaidi@eecs.umich.edu case 0: 12023863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 12033863Ssaidi@eecs.umich.edu break; 12043863Ssaidi@eecs.umich.edu case 1: 12053863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 12063863Ssaidi@eecs.umich.edu break; 12073863Ssaidi@eecs.umich.edu case 3: 12083863Ssaidi@eecs.umich.edu ctx_id = 0; 12093863Ssaidi@eecs.umich.edu break; 12103863Ssaidi@eecs.umich.edu default: 12113863Ssaidi@eecs.umich.edu ignore = true; 12123863Ssaidi@eecs.umich.edu } 12133863Ssaidi@eecs.umich.edu 12143863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12153863Ssaidi@eecs.umich.edu case 0: // demap page 12163863Ssaidi@eecs.umich.edu if (!ignore) 12173863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12183863Ssaidi@eecs.umich.edu break; 12193863Ssaidi@eecs.umich.edu case 1: //demap context 12203863Ssaidi@eecs.umich.edu if (!ignore) 12213863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12223863Ssaidi@eecs.umich.edu break; 12233863Ssaidi@eecs.umich.edu case 2: 12243863Ssaidi@eecs.umich.edu demapAll(part_id); 12253863Ssaidi@eecs.umich.edu break; 12263863Ssaidi@eecs.umich.edu default: 12273863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12283863Ssaidi@eecs.umich.edu } 12293863Ssaidi@eecs.umich.edu break; 12303823Ssaidi@eecs.umich.edu default: 12313823Ssaidi@eecs.umich.edudoMmuWriteError: 12323823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12333823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12343823Ssaidi@eecs.umich.edu } 12353823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 12363823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12373806Ssaidi@eecs.umich.edu} 12383806Ssaidi@eecs.umich.edu 12393804Ssaidi@eecs.umich.eduvoid 12403804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 12413804Ssaidi@eecs.umich.edu{ 12423804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 12433804Ssaidi@eecs.umich.edu} 12443804Ssaidi@eecs.umich.edu 12453804Ssaidi@eecs.umich.eduvoid 12463804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 12473804Ssaidi@eecs.umich.edu{ 12483804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 12493804Ssaidi@eecs.umich.edu} 12503804Ssaidi@eecs.umich.edu 12513804Ssaidi@eecs.umich.edu 12523804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 12533804Ssaidi@eecs.umich.edu 12543804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 12553804Ssaidi@eecs.umich.edu 12563804Ssaidi@eecs.umich.edu Param<int> size; 12573804Ssaidi@eecs.umich.edu 12583804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 12593804Ssaidi@eecs.umich.edu 12603804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 12613804Ssaidi@eecs.umich.edu 12623804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 12633804Ssaidi@eecs.umich.edu 12643804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 12653804Ssaidi@eecs.umich.edu 12663804Ssaidi@eecs.umich.edu 12673804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 12683804Ssaidi@eecs.umich.edu{ 12693804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 12703804Ssaidi@eecs.umich.edu} 12713804Ssaidi@eecs.umich.edu 12723804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 12733804Ssaidi@eecs.umich.edu 12743804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 12753804Ssaidi@eecs.umich.edu 12763804Ssaidi@eecs.umich.edu Param<int> size; 12773804Ssaidi@eecs.umich.edu 12783804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 12793804Ssaidi@eecs.umich.edu 12803804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 12813804Ssaidi@eecs.umich.edu 12823804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 12833804Ssaidi@eecs.umich.edu 12843804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 12853804Ssaidi@eecs.umich.edu 12863804Ssaidi@eecs.umich.edu 12873804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 12883804Ssaidi@eecs.umich.edu{ 12893804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 12903804Ssaidi@eecs.umich.edu} 12913804Ssaidi@eecs.umich.edu 12923804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 12933804Ssaidi@eecs.umich.edu} 1294