tlb.cc revision 3912
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 493881Ssaidi@eecs.umich.edu cacheValid(false) 503804Ssaidi@eecs.umich.edu{ 513804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 523804Ssaidi@eecs.umich.edu if (size > 64) 533804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 543569Sgblack@eecs.umich.edu 553804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 563804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 573881Ssaidi@eecs.umich.edu 583881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 593881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 603804Ssaidi@eecs.umich.edu} 613569Sgblack@eecs.umich.edu 623804Ssaidi@eecs.umich.eduvoid 633804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 643804Ssaidi@eecs.umich.edu{ 653804Ssaidi@eecs.umich.edu MapIter i; 663881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 673804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 683804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 693804Ssaidi@eecs.umich.edu t->used = false; 703804Ssaidi@eecs.umich.edu usedEntries--; 713804Ssaidi@eecs.umich.edu } 723804Ssaidi@eecs.umich.edu } 733804Ssaidi@eecs.umich.edu} 743569Sgblack@eecs.umich.edu 753569Sgblack@eecs.umich.edu 763804Ssaidi@eecs.umich.eduvoid 773804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 783826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 793804Ssaidi@eecs.umich.edu{ 803569Sgblack@eecs.umich.edu 813569Sgblack@eecs.umich.edu 823804Ssaidi@eecs.umich.edu MapIter i; 833826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 843907Ssaidi@eecs.umich.edu// TlbRange tr; 853826Ssaidi@eecs.umich.edu int x; 863811Ssaidi@eecs.umich.edu 873836Ssaidi@eecs.umich.edu cacheValid = false; 883907Ssaidi@eecs.umich.edu /* tr.va = va; 893881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 903881Ssaidi@eecs.umich.edu tr.contextId = context_id; 913881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 923881Ssaidi@eecs.umich.edu tr.real = real; 933907Ssaidi@eecs.umich.edu*/ 943881Ssaidi@eecs.umich.edu 953881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 963881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 973881Ssaidi@eecs.umich.edu 983881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 993907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1003907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1013907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1023907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1033907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1043907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1053907Ssaidi@eecs.umich.edu { 1063907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1073907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1083907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1093907Ssaidi@eecs.umich.edu 1103907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1113907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1123907Ssaidi@eecs.umich.edu tlb[x].used = false; 1133907Ssaidi@eecs.umich.edu usedEntries--; 1143907Ssaidi@eecs.umich.edu } 1153907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1163907Ssaidi@eecs.umich.edu } 1173907Ssaidi@eecs.umich.edu } 1183907Ssaidi@eecs.umich.edu } 1193907Ssaidi@eecs.umich.edu 1203907Ssaidi@eecs.umich.edu 1213907Ssaidi@eecs.umich.edu/* 1223881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1233881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1243881Ssaidi@eecs.umich.edu i->second->valid = false; 1253881Ssaidi@eecs.umich.edu if (i->second->used) { 1263881Ssaidi@eecs.umich.edu i->second->used = false; 1273881Ssaidi@eecs.umich.edu usedEntries--; 1283881Ssaidi@eecs.umich.edu } 1293881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1303881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1313881Ssaidi@eecs.umich.edu i->second); 1323881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1333881Ssaidi@eecs.umich.edu } 1343907Ssaidi@eecs.umich.edu*/ 1353811Ssaidi@eecs.umich.edu 1363826Ssaidi@eecs.umich.edu if (entry != -1) { 1373826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1383826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1393826Ssaidi@eecs.umich.edu } else { 1403881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1413881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1423881Ssaidi@eecs.umich.edu } else { 1433881Ssaidi@eecs.umich.edu x = lastReplaced; 1443881Ssaidi@eecs.umich.edu do { 1453881Ssaidi@eecs.umich.edu ++x; 1463881Ssaidi@eecs.umich.edu if (x == size) 1473881Ssaidi@eecs.umich.edu x = 0; 1483881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1493881Ssaidi@eecs.umich.edu goto insertAllLocked; 1503881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1513881Ssaidi@eecs.umich.edu lastReplaced = x; 1523881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1533881Ssaidi@eecs.umich.edu } 1543881Ssaidi@eecs.umich.edu /* 1553826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1563826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1573826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1583826Ssaidi@eecs.umich.edu break; 1593826Ssaidi@eecs.umich.edu } 1603881Ssaidi@eecs.umich.edu }*/ 1613569Sgblack@eecs.umich.edu } 1623569Sgblack@eecs.umich.edu 1633881Ssaidi@eecs.umich.eduinsertAllLocked: 1643804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1653881Ssaidi@eecs.umich.edu if (!new_entry) { 1663826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1673881Ssaidi@eecs.umich.edu } 1683881Ssaidi@eecs.umich.edu 1693881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1703907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1713907Ssaidi@eecs.umich.edu usedEntries--; 1723907Ssaidi@eecs.umich.edu 1733907Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1743907Ssaidi@eecs.umich.edu 1753907Ssaidi@eecs.umich.edu 1763881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Using entry: %#X\n", new_entry); 1773569Sgblack@eecs.umich.edu 1783804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1793804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1803881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1813804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1823804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1833804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1843804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1853804Ssaidi@eecs.umich.edu new_entry->used = true;; 1863804Ssaidi@eecs.umich.edu new_entry->valid = true; 1873804Ssaidi@eecs.umich.edu usedEntries++; 1883569Sgblack@eecs.umich.edu 1893569Sgblack@eecs.umich.edu 1903569Sgblack@eecs.umich.edu 1913863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1923863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1953804Ssaidi@eecs.umich.edu // one we just inserted 1963804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1973804Ssaidi@eecs.umich.edu clearUsedBits(); 1983804Ssaidi@eecs.umich.edu new_entry->used = true; 1993804Ssaidi@eecs.umich.edu usedEntries++; 2003804Ssaidi@eecs.umich.edu } 2013804Ssaidi@eecs.umich.edu 2023569Sgblack@eecs.umich.edu} 2033804Ssaidi@eecs.umich.edu 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.eduTlbEntry* 2063804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 2073804Ssaidi@eecs.umich.edu{ 2083804Ssaidi@eecs.umich.edu MapIter i; 2093804Ssaidi@eecs.umich.edu TlbRange tr; 2103804Ssaidi@eecs.umich.edu TlbEntry *t; 2113804Ssaidi@eecs.umich.edu 2123811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2133811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2143804Ssaidi@eecs.umich.edu // Assemble full address structure 2153804Ssaidi@eecs.umich.edu tr.va = va; 2163863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2173804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2183804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2193804Ssaidi@eecs.umich.edu tr.real = real; 2203804Ssaidi@eecs.umich.edu 2213804Ssaidi@eecs.umich.edu // Try to find the entry 2223804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2233804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2243811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2253804Ssaidi@eecs.umich.edu return NULL; 2263804Ssaidi@eecs.umich.edu } 2273804Ssaidi@eecs.umich.edu 2283804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2293804Ssaidi@eecs.umich.edu t = i->second; 2303826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2313826Ssaidi@eecs.umich.edu t->pte.size()); 2323804Ssaidi@eecs.umich.edu if (!t->used) { 2333804Ssaidi@eecs.umich.edu t->used = true; 2343804Ssaidi@eecs.umich.edu usedEntries++; 2353804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2363804Ssaidi@eecs.umich.edu clearUsedBits(); 2373804Ssaidi@eecs.umich.edu t->used = true; 2383804Ssaidi@eecs.umich.edu usedEntries++; 2393804Ssaidi@eecs.umich.edu } 2403804Ssaidi@eecs.umich.edu } 2413804Ssaidi@eecs.umich.edu 2423804Ssaidi@eecs.umich.edu return t; 2433804Ssaidi@eecs.umich.edu} 2443804Ssaidi@eecs.umich.edu 2453826Ssaidi@eecs.umich.eduvoid 2463826Ssaidi@eecs.umich.eduTLB::dumpAll() 2473826Ssaidi@eecs.umich.edu{ 2483863Ssaidi@eecs.umich.edu MapIter i; 2493826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2503826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2513826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2523826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2533826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2543826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2553826Ssaidi@eecs.umich.edu } 2563826Ssaidi@eecs.umich.edu } 2573826Ssaidi@eecs.umich.edu} 2583804Ssaidi@eecs.umich.edu 2593804Ssaidi@eecs.umich.eduvoid 2603804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2613804Ssaidi@eecs.umich.edu{ 2623804Ssaidi@eecs.umich.edu TlbRange tr; 2633804Ssaidi@eecs.umich.edu MapIter i; 2643804Ssaidi@eecs.umich.edu 2653863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2663863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2673863Ssaidi@eecs.umich.edu 2683836Ssaidi@eecs.umich.edu cacheValid = false; 2693836Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.edu // Assemble full address structure 2713804Ssaidi@eecs.umich.edu tr.va = va; 2723863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2733804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2743804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2753804Ssaidi@eecs.umich.edu tr.real = real; 2763804Ssaidi@eecs.umich.edu 2773804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2783804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2793804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2803863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2813804Ssaidi@eecs.umich.edu i->second->valid = false; 2823804Ssaidi@eecs.umich.edu if (i->second->used) { 2833804Ssaidi@eecs.umich.edu i->second->used = false; 2843804Ssaidi@eecs.umich.edu usedEntries--; 2853804Ssaidi@eecs.umich.edu } 2863881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2873881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second); 2883804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2893804Ssaidi@eecs.umich.edu } 2903804Ssaidi@eecs.umich.edu} 2913804Ssaidi@eecs.umich.edu 2923804Ssaidi@eecs.umich.eduvoid 2933804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2943804Ssaidi@eecs.umich.edu{ 2953804Ssaidi@eecs.umich.edu int x; 2963863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2973863Ssaidi@eecs.umich.edu partition_id, context_id); 2983836Ssaidi@eecs.umich.edu cacheValid = false; 2993804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3003804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 3013804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3023881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 3033881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3043881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]); 3053881Ssaidi@eecs.umich.edu } 3063804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3073804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3083804Ssaidi@eecs.umich.edu tlb[x].used = false; 3093804Ssaidi@eecs.umich.edu usedEntries--; 3103804Ssaidi@eecs.umich.edu } 3113804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3123804Ssaidi@eecs.umich.edu } 3133804Ssaidi@eecs.umich.edu } 3143804Ssaidi@eecs.umich.edu} 3153804Ssaidi@eecs.umich.edu 3163804Ssaidi@eecs.umich.eduvoid 3173804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3183804Ssaidi@eecs.umich.edu{ 3193804Ssaidi@eecs.umich.edu int x; 3203863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3213836Ssaidi@eecs.umich.edu cacheValid = false; 3223804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3233804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 3243881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 3253881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 3263881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]); 3273881Ssaidi@eecs.umich.edu } 3283804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3293804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3303804Ssaidi@eecs.umich.edu tlb[x].used = false; 3313804Ssaidi@eecs.umich.edu usedEntries--; 3323804Ssaidi@eecs.umich.edu } 3333804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3343804Ssaidi@eecs.umich.edu } 3353804Ssaidi@eecs.umich.edu } 3363804Ssaidi@eecs.umich.edu} 3373804Ssaidi@eecs.umich.edu 3383804Ssaidi@eecs.umich.eduvoid 3393804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3403804Ssaidi@eecs.umich.edu{ 3413804Ssaidi@eecs.umich.edu int x; 3423836Ssaidi@eecs.umich.edu cacheValid = false; 3433836Ssaidi@eecs.umich.edu 3443881Ssaidi@eecs.umich.edu freeList.clear(); 3453907Ssaidi@eecs.umich.edu lookupTable.clear(); 3463804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3473881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3483881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3493804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3503907Ssaidi@eecs.umich.edu tlb[x].used = false; 3513804Ssaidi@eecs.umich.edu } 3523804Ssaidi@eecs.umich.edu usedEntries = 0; 3533804Ssaidi@eecs.umich.edu} 3543804Ssaidi@eecs.umich.edu 3553804Ssaidi@eecs.umich.eduuint64_t 3563804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3573881Ssaidi@eecs.umich.edu if (entry >= size) 3583881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3593881Ssaidi@eecs.umich.edu 3603804Ssaidi@eecs.umich.edu assert(entry < size); 3613881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3623881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3633881Ssaidi@eecs.umich.edu else 3643881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3653804Ssaidi@eecs.umich.edu} 3663804Ssaidi@eecs.umich.edu 3673804Ssaidi@eecs.umich.eduuint64_t 3683804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3693804Ssaidi@eecs.umich.edu assert(entry < size); 3703804Ssaidi@eecs.umich.edu uint64_t tag; 3713881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3723881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3733804Ssaidi@eecs.umich.edu 3743881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3753881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3763881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3773804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3783804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3793804Ssaidi@eecs.umich.edu return tag; 3803804Ssaidi@eecs.umich.edu} 3813804Ssaidi@eecs.umich.edu 3823804Ssaidi@eecs.umich.edubool 3833804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3843804Ssaidi@eecs.umich.edu{ 3853804Ssaidi@eecs.umich.edu if (am) 3863804Ssaidi@eecs.umich.edu return true; 3873804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3883804Ssaidi@eecs.umich.edu return false; 3893804Ssaidi@eecs.umich.edu return true; 3903804Ssaidi@eecs.umich.edu} 3913804Ssaidi@eecs.umich.edu 3923804Ssaidi@eecs.umich.eduvoid 3933804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3943804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3953804Ssaidi@eecs.umich.edu{ 3963804Ssaidi@eecs.umich.edu uint64_t sfsr; 3973804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3983804Ssaidi@eecs.umich.edu 3993804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 4003804Ssaidi@eecs.umich.edu sfsr = 0x3; 4013804Ssaidi@eecs.umich.edu else 4023804Ssaidi@eecs.umich.edu sfsr = 1; 4033804Ssaidi@eecs.umich.edu 4043804Ssaidi@eecs.umich.edu if (write) 4053804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 4063804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 4073804Ssaidi@eecs.umich.edu if (se) 4083804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 4093804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 4103804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 4113826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 4123804Ssaidi@eecs.umich.edu} 4133804Ssaidi@eecs.umich.edu 4143826Ssaidi@eecs.umich.eduvoid 4153826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 4163826Ssaidi@eecs.umich.edu{ 4173826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 4183826Ssaidi@eecs.umich.edu} 4193804Ssaidi@eecs.umich.edu 4203804Ssaidi@eecs.umich.eduvoid 4213804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 4223804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4233804Ssaidi@eecs.umich.edu{ 4243811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 4253811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 4263804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 4273804Ssaidi@eecs.umich.edu} 4283804Ssaidi@eecs.umich.edu 4293804Ssaidi@eecs.umich.eduvoid 4303826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4313826Ssaidi@eecs.umich.edu{ 4323826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4333826Ssaidi@eecs.umich.edu} 4343826Ssaidi@eecs.umich.edu 4353826Ssaidi@eecs.umich.eduvoid 4363804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4373804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4383804Ssaidi@eecs.umich.edu{ 4393811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4403811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4413804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4423826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 4433804Ssaidi@eecs.umich.edu} 4443804Ssaidi@eecs.umich.edu 4453836Ssaidi@eecs.umich.eduvoid 4463826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4473826Ssaidi@eecs.umich.edu{ 4483826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4493826Ssaidi@eecs.umich.edu} 4503826Ssaidi@eecs.umich.edu 4513826Ssaidi@eecs.umich.edu 4523804Ssaidi@eecs.umich.edu 4533804Ssaidi@eecs.umich.eduFault 4543804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4553804Ssaidi@eecs.umich.edu{ 4563833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4573833Ssaidi@eecs.umich.edu 4583836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4593836Ssaidi@eecs.umich.edu TlbEntry *e; 4603836Ssaidi@eecs.umich.edu 4613836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4623836Ssaidi@eecs.umich.edu 4633836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4643836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4653836Ssaidi@eecs.umich.edu 4663836Ssaidi@eecs.umich.edu // Be fast if we can! 4673836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4683836Ssaidi@eecs.umich.edu if (cacheEntry) { 4693836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4703836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4713836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4723836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4733836Ssaidi@eecs.umich.edu return NoFault; 4743836Ssaidi@eecs.umich.edu } 4753836Ssaidi@eecs.umich.edu } else { 4763836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4773836Ssaidi@eecs.umich.edu return NoFault; 4783836Ssaidi@eecs.umich.edu } 4793836Ssaidi@eecs.umich.edu } 4803836Ssaidi@eecs.umich.edu 4813833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4823833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4833833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4843833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4853833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4863833Ssaidi@eecs.umich.edu 4873833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4883833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4893833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4903804Ssaidi@eecs.umich.edu int context; 4913804Ssaidi@eecs.umich.edu ContextType ct; 4923804Ssaidi@eecs.umich.edu int asi; 4933804Ssaidi@eecs.umich.edu bool real = false; 4943804Ssaidi@eecs.umich.edu 4953833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4963833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4973811Ssaidi@eecs.umich.edu 4983804Ssaidi@eecs.umich.edu if (tl > 0) { 4993804Ssaidi@eecs.umich.edu asi = ASI_N; 5003804Ssaidi@eecs.umich.edu ct = Nucleus; 5013804Ssaidi@eecs.umich.edu context = 0; 5023804Ssaidi@eecs.umich.edu } else { 5033804Ssaidi@eecs.umich.edu asi = ASI_P; 5043804Ssaidi@eecs.umich.edu ct = Primary; 5053833Ssaidi@eecs.umich.edu context = pri_context; 5063804Ssaidi@eecs.umich.edu } 5073804Ssaidi@eecs.umich.edu 5083833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 5093836Ssaidi@eecs.umich.edu cacheValid = true; 5103836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5113836Ssaidi@eecs.umich.edu cacheEntry = NULL; 5123836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5133804Ssaidi@eecs.umich.edu return NoFault; 5143804Ssaidi@eecs.umich.edu } 5153804Ssaidi@eecs.umich.edu 5163836Ssaidi@eecs.umich.edu // If the access is unaligned trap 5173836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 5183804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 5193804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5203804Ssaidi@eecs.umich.edu } 5213804Ssaidi@eecs.umich.edu 5223804Ssaidi@eecs.umich.edu if (addr_mask) 5233804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5243804Ssaidi@eecs.umich.edu 5253804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5263804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 5273804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5283804Ssaidi@eecs.umich.edu } 5293804Ssaidi@eecs.umich.edu 5303833Ssaidi@eecs.umich.edu if (!lsu_im) { 5313836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5323804Ssaidi@eecs.umich.edu real = true; 5333804Ssaidi@eecs.umich.edu context = 0; 5343804Ssaidi@eecs.umich.edu } else { 5353804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5363804Ssaidi@eecs.umich.edu } 5373804Ssaidi@eecs.umich.edu 5383804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5393804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 5403804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 5413804Ssaidi@eecs.umich.edu if (real) 5423804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5433804Ssaidi@eecs.umich.edu else 5443804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5453804Ssaidi@eecs.umich.edu } 5463804Ssaidi@eecs.umich.edu 5473804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5483804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5493804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5503804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5513804Ssaidi@eecs.umich.edu } 5523804Ssaidi@eecs.umich.edu 5533836Ssaidi@eecs.umich.edu // cache translation date for next translation 5543836Ssaidi@eecs.umich.edu cacheValid = true; 5553836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5563836Ssaidi@eecs.umich.edu cacheEntry = e; 5573836Ssaidi@eecs.umich.edu 5583826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5593836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5603836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5613804Ssaidi@eecs.umich.edu return NoFault; 5623804Ssaidi@eecs.umich.edu} 5633804Ssaidi@eecs.umich.edu 5643804Ssaidi@eecs.umich.edu 5653804Ssaidi@eecs.umich.edu 5663804Ssaidi@eecs.umich.eduFault 5673804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5683804Ssaidi@eecs.umich.edu{ 5693804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5703833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 5713836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5723836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5733836Ssaidi@eecs.umich.edu ASI asi; 5743836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5753836Ssaidi@eecs.umich.edu bool implicit = false; 5763836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5773833Ssaidi@eecs.umich.edu 5783836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5793836Ssaidi@eecs.umich.edu vaddr, size, asi); 5803836Ssaidi@eecs.umich.edu 5813836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5823836Ssaidi@eecs.umich.edu implicit = true; 5833836Ssaidi@eecs.umich.edu 5843836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5853836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5863836Ssaidi@eecs.umich.edu return NoFault; 5873836Ssaidi@eecs.umich.edu } 5883836Ssaidi@eecs.umich.edu 5893836Ssaidi@eecs.umich.edu // Be fast if we can! 5903836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5913836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 5923881Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) { 5933836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 5943836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 5953836Ssaidi@eecs.umich.edu return NoFault; 5963836Ssaidi@eecs.umich.edu } 5973836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 5983881Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) { 5993836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 6003836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 6013836Ssaidi@eecs.umich.edu return NoFault; 6023836Ssaidi@eecs.umich.edu } 6033836Ssaidi@eecs.umich.edu } 6043836Ssaidi@eecs.umich.edu 6053833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6063833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6073833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6083833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6093833Ssaidi@eecs.umich.edu 6103833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6113833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6123833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6133833Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,47,32); 6143833Ssaidi@eecs.umich.edu 6153804Ssaidi@eecs.umich.edu bool real = false; 6163832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6173832Ssaidi@eecs.umich.edu int context = 0; 6183804Ssaidi@eecs.umich.edu 6193804Ssaidi@eecs.umich.edu TlbEntry *e; 6203804Ssaidi@eecs.umich.edu 6213833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6223833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 6233804Ssaidi@eecs.umich.edu 6243804Ssaidi@eecs.umich.edu if (implicit) { 6253804Ssaidi@eecs.umich.edu if (tl > 0) { 6263804Ssaidi@eecs.umich.edu asi = ASI_N; 6273804Ssaidi@eecs.umich.edu ct = Nucleus; 6283804Ssaidi@eecs.umich.edu context = 0; 6293804Ssaidi@eecs.umich.edu } else { 6303804Ssaidi@eecs.umich.edu asi = ASI_P; 6313804Ssaidi@eecs.umich.edu ct = Primary; 6323833Ssaidi@eecs.umich.edu context = pri_context; 6333804Ssaidi@eecs.umich.edu } 6343910Ssaidi@eecs.umich.edu } else { 6353804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6363910Ssaidi@eecs.umich.edu if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 6373804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6383804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6393804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6403804Ssaidi@eecs.umich.edu } 6413910Ssaidi@eecs.umich.edu 6423910Ssaidi@eecs.umich.edu if (!hpriv && AsiIsHPriv(asi)) { 6433804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6443804Ssaidi@eecs.umich.edu return new DataAccessException; 6453804Ssaidi@eecs.umich.edu } 6463804Ssaidi@eecs.umich.edu 6473910Ssaidi@eecs.umich.edu if (AsiIsPrimary(asi)) { 6483910Ssaidi@eecs.umich.edu context = pri_context; 6493910Ssaidi@eecs.umich.edu ct = Primary; 6503910Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6513910Ssaidi@eecs.umich.edu context = sec_context; 6523910Ssaidi@eecs.umich.edu ct = Secondary; 6533910Ssaidi@eecs.umich.edu } else if (AsiIsNucleus(asi)) { 6543910Ssaidi@eecs.umich.edu ct = Nucleus; 6553910Ssaidi@eecs.umich.edu context = 0; 6563910Ssaidi@eecs.umich.edu } else { // ???? 6573910Ssaidi@eecs.umich.edu ct = Primary; 6583910Ssaidi@eecs.umich.edu context = pri_context; 6593910Ssaidi@eecs.umich.edu } 6603902Ssaidi@eecs.umich.edu } 6613804Ssaidi@eecs.umich.edu 6623804Ssaidi@eecs.umich.edu if (!implicit) { 6633804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6643804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6653804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 6663804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 6673804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 6683804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 6693910Ssaidi@eecs.umich.edu 6703910Ssaidi@eecs.umich.edu // These twin ASIs are OK 6713910Ssaidi@eecs.umich.edu if (asi == ASI_P || asi == ASI_LDTX_P) 6723910Ssaidi@eecs.umich.edu goto continueDtbFlow; 6733908Ssaidi@eecs.umich.edu if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL)) 6743856Ssaidi@eecs.umich.edu goto continueDtbFlow; 6753856Ssaidi@eecs.umich.edu 6763804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 6773804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 6783804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6793804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6803824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6813824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 6823823Ssaidi@eecs.umich.edu 6833804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6843804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6853804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6863804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6873824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6883824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6893825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6903825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6913823Ssaidi@eecs.umich.edu 6923910Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi)) 6933823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6943804Ssaidi@eecs.umich.edu } 6953804Ssaidi@eecs.umich.edu 6963826Ssaidi@eecs.umich.educontinueDtbFlow: 6973826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6983826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6993826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 7003826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 7013826Ssaidi@eecs.umich.edu } 7023826Ssaidi@eecs.umich.edu 7033826Ssaidi@eecs.umich.edu if (addr_mask) 7043826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7053826Ssaidi@eecs.umich.edu 7063826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7073826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 7083826Ssaidi@eecs.umich.edu return new DataAccessException; 7093826Ssaidi@eecs.umich.edu } 7103826Ssaidi@eecs.umich.edu 7113826Ssaidi@eecs.umich.edu 7123910Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 7133804Ssaidi@eecs.umich.edu real = true; 7143804Ssaidi@eecs.umich.edu context = 0; 7153804Ssaidi@eecs.umich.edu }; 7163804Ssaidi@eecs.umich.edu 7173804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 7183836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7193804Ssaidi@eecs.umich.edu return NoFault; 7203804Ssaidi@eecs.umich.edu } 7213804Ssaidi@eecs.umich.edu 7223836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7233804Ssaidi@eecs.umich.edu 7243804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7253804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 7263804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 7273811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7283804Ssaidi@eecs.umich.edu if (real) 7293804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7303804Ssaidi@eecs.umich.edu else 7313804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7323804Ssaidi@eecs.umich.edu 7333804Ssaidi@eecs.umich.edu } 7343804Ssaidi@eecs.umich.edu 7353804Ssaidi@eecs.umich.edu 7363804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7373804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7383804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7393804Ssaidi@eecs.umich.edu } 7403804Ssaidi@eecs.umich.edu 7413804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7423804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7433804Ssaidi@eecs.umich.edu return new DataAccessException; 7443804Ssaidi@eecs.umich.edu } 7453804Ssaidi@eecs.umich.edu 7463804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 7473804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7483804Ssaidi@eecs.umich.edu 7493804Ssaidi@eecs.umich.edu 7503804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7513804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7523804Ssaidi@eecs.umich.edu return new DataAccessException; 7533804Ssaidi@eecs.umich.edu } 7543804Ssaidi@eecs.umich.edu 7553836Ssaidi@eecs.umich.edu // cache translation date for next translation 7563836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7573881Ssaidi@eecs.umich.edu if (!cacheValid) { 7583881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7593881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7603881Ssaidi@eecs.umich.edu } 7613881Ssaidi@eecs.umich.edu 7623836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7633836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7643836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7653836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7663836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7673836Ssaidi@eecs.umich.edu if (implicit) 7683836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7693836Ssaidi@eecs.umich.edu } 7703881Ssaidi@eecs.umich.edu cacheValid = true; 7713826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7723836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7733836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7743804Ssaidi@eecs.umich.edu return NoFault; 7753806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7763804Ssaidi@eecs.umich.edu 7773806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7783806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7793806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7803806Ssaidi@eecs.umich.edu return new DataAccessException; 7813806Ssaidi@eecs.umich.edu } 7823824Ssaidi@eecs.umich.edu goto regAccessOk; 7833824Ssaidi@eecs.umich.edu 7843824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7853824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7863824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7873824Ssaidi@eecs.umich.edu return new PrivilegedAction; 7883824Ssaidi@eecs.umich.edu } 7893881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 7903824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7913824Ssaidi@eecs.umich.edu return new DataAccessException; 7923824Ssaidi@eecs.umich.edu } 7933824Ssaidi@eecs.umich.edu goto regAccessOk; 7943824Ssaidi@eecs.umich.edu 7953825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 7963825Ssaidi@eecs.umich.edu if (!hpriv) { 7973825Ssaidi@eecs.umich.edu if (priv) { 7983825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7993825Ssaidi@eecs.umich.edu return new DataAccessException; 8003825Ssaidi@eecs.umich.edu } else { 8013825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 8023825Ssaidi@eecs.umich.edu return new PrivilegedAction; 8033825Ssaidi@eecs.umich.edu } 8043825Ssaidi@eecs.umich.edu } 8053825Ssaidi@eecs.umich.edu goto regAccessOk; 8063825Ssaidi@eecs.umich.edu 8073825Ssaidi@eecs.umich.edu 8083824Ssaidi@eecs.umich.eduregAccessOk: 8093804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8103811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8113806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 8123806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8133806Ssaidi@eecs.umich.edu return NoFault; 8143804Ssaidi@eecs.umich.edu}; 8153804Ssaidi@eecs.umich.edu 8163806Ssaidi@eecs.umich.eduTick 8173806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8183806Ssaidi@eecs.umich.edu{ 8193823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8203823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8213833Ssaidi@eecs.umich.edu uint64_t temp, data; 8223833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 8233823Ssaidi@eecs.umich.edu 8243823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8253823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 8263823Ssaidi@eecs.umich.edu 8273823Ssaidi@eecs.umich.edu switch (asi) { 8283823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8293823Ssaidi@eecs.umich.edu assert(va == 0); 8303823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 8313823Ssaidi@eecs.umich.edu break; 8323823Ssaidi@eecs.umich.edu case ASI_MMU: 8333823Ssaidi@eecs.umich.edu switch (va) { 8343823Ssaidi@eecs.umich.edu case 0x8: 8353823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 8363823Ssaidi@eecs.umich.edu break; 8373823Ssaidi@eecs.umich.edu case 0x10: 8383823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 8393823Ssaidi@eecs.umich.edu break; 8403823Ssaidi@eecs.umich.edu default: 8413823Ssaidi@eecs.umich.edu goto doMmuReadError; 8423823Ssaidi@eecs.umich.edu } 8433823Ssaidi@eecs.umich.edu break; 8443824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8453824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8463824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8473824Ssaidi@eecs.umich.edu break; 8483823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8493823Ssaidi@eecs.umich.edu assert(va == 0); 8503823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8513823Ssaidi@eecs.umich.edu break; 8523823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8533823Ssaidi@eecs.umich.edu assert(va == 0); 8543823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 8553823Ssaidi@eecs.umich.edu break; 8563823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8573823Ssaidi@eecs.umich.edu assert(va == 0); 8583823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 8593823Ssaidi@eecs.umich.edu break; 8603823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8613823Ssaidi@eecs.umich.edu assert(va == 0); 8623823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 8633823Ssaidi@eecs.umich.edu break; 8643823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8653823Ssaidi@eecs.umich.edu assert(va == 0); 8663823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 8673823Ssaidi@eecs.umich.edu break; 8683823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8693823Ssaidi@eecs.umich.edu assert(va == 0); 8703823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 8713823Ssaidi@eecs.umich.edu break; 8723823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8733823Ssaidi@eecs.umich.edu assert(va == 0); 8743823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 8753823Ssaidi@eecs.umich.edu break; 8763823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8773823Ssaidi@eecs.umich.edu assert(va == 0); 8783823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 8793823Ssaidi@eecs.umich.edu break; 8803823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8813823Ssaidi@eecs.umich.edu assert(va == 0); 8823823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 8833823Ssaidi@eecs.umich.edu break; 8843823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8853823Ssaidi@eecs.umich.edu assert(va == 0); 8863823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 8873823Ssaidi@eecs.umich.edu break; 8883823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8893823Ssaidi@eecs.umich.edu assert(va == 0); 8903823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 8913823Ssaidi@eecs.umich.edu break; 8923823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8933823Ssaidi@eecs.umich.edu assert(va == 0); 8943823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 8953823Ssaidi@eecs.umich.edu break; 8963826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 8973826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 8983912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 8993826Ssaidi@eecs.umich.edu break; 9003823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9013823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9023823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9033823Ssaidi@eecs.umich.edu break; 9043826Ssaidi@eecs.umich.edu case ASI_IMMU: 9053826Ssaidi@eecs.umich.edu switch (va) { 9063833Ssaidi@eecs.umich.edu case 0x0: 9073833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9083833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9093833Ssaidi@eecs.umich.edu break; 9103906Ssaidi@eecs.umich.edu case 0x18: 9113906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 9123906Ssaidi@eecs.umich.edu break; 9133826Ssaidi@eecs.umich.edu case 0x30: 9143826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 9153826Ssaidi@eecs.umich.edu break; 9163826Ssaidi@eecs.umich.edu default: 9173826Ssaidi@eecs.umich.edu goto doMmuReadError; 9183826Ssaidi@eecs.umich.edu } 9193826Ssaidi@eecs.umich.edu break; 9203823Ssaidi@eecs.umich.edu case ASI_DMMU: 9213823Ssaidi@eecs.umich.edu switch (va) { 9223833Ssaidi@eecs.umich.edu case 0x0: 9233833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9243833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9253833Ssaidi@eecs.umich.edu break; 9263906Ssaidi@eecs.umich.edu case 0x18: 9273906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 9283906Ssaidi@eecs.umich.edu break; 9293906Ssaidi@eecs.umich.edu case 0x20: 9303906Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 9313906Ssaidi@eecs.umich.edu break; 9323826Ssaidi@eecs.umich.edu case 0x30: 9333826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 9343826Ssaidi@eecs.umich.edu break; 9353823Ssaidi@eecs.umich.edu case 0x80: 9363823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 9373823Ssaidi@eecs.umich.edu break; 9383823Ssaidi@eecs.umich.edu default: 9393823Ssaidi@eecs.umich.edu goto doMmuReadError; 9403823Ssaidi@eecs.umich.edu } 9413823Ssaidi@eecs.umich.edu break; 9423833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9433833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9443833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9453833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 9463833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9473833Ssaidi@eecs.umich.edu } else { 9483833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 9493833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9503833Ssaidi@eecs.umich.edu } 9513833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9523833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9533833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9543833Ssaidi@eecs.umich.edu pkt->set(data); 9553833Ssaidi@eecs.umich.edu break; 9563833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9573833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9583833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9593833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 9603833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9613833Ssaidi@eecs.umich.edu } else { 9623833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 9633833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9643833Ssaidi@eecs.umich.edu } 9653833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9663833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9673833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 9683910Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 9693833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9703833Ssaidi@eecs.umich.edu pkt->set(data); 9713833Ssaidi@eecs.umich.edu break; 9723899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 9733899Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9743899Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9753899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); 9763899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 9773899Ssaidi@eecs.umich.edu } else { 9783899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); 9793899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 9803899Ssaidi@eecs.umich.edu } 9813899Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9823899Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9833899Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9843899Ssaidi@eecs.umich.edu pkt->set(data); 9853899Ssaidi@eecs.umich.edu break; 9863899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 9873899Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9883899Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9893899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); 9903899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 9913899Ssaidi@eecs.umich.edu } else { 9923899Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); 9933899Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 9943899Ssaidi@eecs.umich.edu } 9953899Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9963899Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9973899Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 9983910Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 9993899Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 10003899Ssaidi@eecs.umich.edu pkt->set(data); 10013899Ssaidi@eecs.umich.edu break; 10023833Ssaidi@eecs.umich.edu 10033823Ssaidi@eecs.umich.edu default: 10043823Ssaidi@eecs.umich.edudoMmuReadError: 10053823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10063823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10073823Ssaidi@eecs.umich.edu } 10083823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 10093823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 10103806Ssaidi@eecs.umich.edu} 10113806Ssaidi@eecs.umich.edu 10123806Ssaidi@eecs.umich.eduTick 10133806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10143806Ssaidi@eecs.umich.edu{ 10153823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 10163823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10173823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 10183823Ssaidi@eecs.umich.edu 10193826Ssaidi@eecs.umich.edu Addr ta_insert; 10203826Ssaidi@eecs.umich.edu Addr va_insert; 10213826Ssaidi@eecs.umich.edu Addr ct_insert; 10223826Ssaidi@eecs.umich.edu int part_insert; 10233826Ssaidi@eecs.umich.edu int entry_insert = -1; 10243826Ssaidi@eecs.umich.edu bool real_insert; 10253863Ssaidi@eecs.umich.edu bool ignore; 10263863Ssaidi@eecs.umich.edu int part_id; 10273863Ssaidi@eecs.umich.edu int ctx_id; 10283826Ssaidi@eecs.umich.edu PageTableEntry pte; 10293826Ssaidi@eecs.umich.edu 10303825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10313823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10323823Ssaidi@eecs.umich.edu 10333823Ssaidi@eecs.umich.edu switch (asi) { 10343823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10353823Ssaidi@eecs.umich.edu assert(va == 0); 10363823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 10373823Ssaidi@eecs.umich.edu break; 10383823Ssaidi@eecs.umich.edu case ASI_MMU: 10393823Ssaidi@eecs.umich.edu switch (va) { 10403823Ssaidi@eecs.umich.edu case 0x8: 10413823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 10423823Ssaidi@eecs.umich.edu break; 10433823Ssaidi@eecs.umich.edu case 0x10: 10443823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 10453823Ssaidi@eecs.umich.edu break; 10463823Ssaidi@eecs.umich.edu default: 10473823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10483823Ssaidi@eecs.umich.edu } 10493823Ssaidi@eecs.umich.edu break; 10503824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10513825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10523824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 10533824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10543824Ssaidi@eecs.umich.edu break; 10553823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10563823Ssaidi@eecs.umich.edu assert(va == 0); 10573823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 10583823Ssaidi@eecs.umich.edu break; 10593823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10603823Ssaidi@eecs.umich.edu assert(va == 0); 10613823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 10623823Ssaidi@eecs.umich.edu break; 10633823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10643823Ssaidi@eecs.umich.edu assert(va == 0); 10653823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 10663823Ssaidi@eecs.umich.edu break; 10673823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10683823Ssaidi@eecs.umich.edu assert(va == 0); 10693823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10703823Ssaidi@eecs.umich.edu break; 10713823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10723823Ssaidi@eecs.umich.edu assert(va == 0); 10733823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10743823Ssaidi@eecs.umich.edu break; 10753823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10763823Ssaidi@eecs.umich.edu assert(va == 0); 10773823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 10783823Ssaidi@eecs.umich.edu break; 10793823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10803823Ssaidi@eecs.umich.edu assert(va == 0); 10813823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 10823823Ssaidi@eecs.umich.edu break; 10833823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 10843823Ssaidi@eecs.umich.edu assert(va == 0); 10853823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 10863823Ssaidi@eecs.umich.edu break; 10873823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 10883823Ssaidi@eecs.umich.edu assert(va == 0); 10893823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 10903823Ssaidi@eecs.umich.edu break; 10913823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 10923823Ssaidi@eecs.umich.edu assert(va == 0); 10933823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 10943823Ssaidi@eecs.umich.edu break; 10953823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 10963823Ssaidi@eecs.umich.edu assert(va == 0); 10973823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 10983823Ssaidi@eecs.umich.edu break; 10993823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11003823Ssaidi@eecs.umich.edu assert(va == 0); 11013823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 11023823Ssaidi@eecs.umich.edu break; 11033825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11043825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11053825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 11063825Ssaidi@eecs.umich.edu break; 11073823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11083823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11093823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11103823Ssaidi@eecs.umich.edu break; 11113826Ssaidi@eecs.umich.edu case ASI_IMMU: 11123826Ssaidi@eecs.umich.edu switch (va) { 11133906Ssaidi@eecs.umich.edu case 0x18: 11143906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 11153906Ssaidi@eecs.umich.edu break; 11163826Ssaidi@eecs.umich.edu case 0x30: 11173826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 11183826Ssaidi@eecs.umich.edu break; 11193826Ssaidi@eecs.umich.edu default: 11203826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11213826Ssaidi@eecs.umich.edu } 11223826Ssaidi@eecs.umich.edu break; 11233826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11243826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11253826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11263826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11273826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 11283826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11293826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11303826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11313826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11323826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11333826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11343826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 11353826Ssaidi@eecs.umich.edu pte, entry_insert); 11363826Ssaidi@eecs.umich.edu break; 11373826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11383826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11393826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11403826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11413826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 11423826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11433826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11443826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11453826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11463826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11473826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11483826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 11493826Ssaidi@eecs.umich.edu break; 11503863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11513863Ssaidi@eecs.umich.edu ignore = false; 11523863Ssaidi@eecs.umich.edu ctx_id = -1; 11533863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11543863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11553863Ssaidi@eecs.umich.edu case 0: 11563863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11573863Ssaidi@eecs.umich.edu break; 11583863Ssaidi@eecs.umich.edu case 1: 11593863Ssaidi@eecs.umich.edu ignore = true; 11603863Ssaidi@eecs.umich.edu break; 11613863Ssaidi@eecs.umich.edu case 3: 11623863Ssaidi@eecs.umich.edu ctx_id = 0; 11633863Ssaidi@eecs.umich.edu break; 11643863Ssaidi@eecs.umich.edu default: 11653863Ssaidi@eecs.umich.edu ignore = true; 11663863Ssaidi@eecs.umich.edu } 11673863Ssaidi@eecs.umich.edu 11683863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11693863Ssaidi@eecs.umich.edu case 0: // demap page 11703863Ssaidi@eecs.umich.edu if (!ignore) 11713863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11723863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11733863Ssaidi@eecs.umich.edu break; 11743863Ssaidi@eecs.umich.edu case 1: //demap context 11753863Ssaidi@eecs.umich.edu if (!ignore) 11763863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11773863Ssaidi@eecs.umich.edu break; 11783863Ssaidi@eecs.umich.edu case 2: 11793863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 11803863Ssaidi@eecs.umich.edu break; 11813863Ssaidi@eecs.umich.edu default: 11823863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11833863Ssaidi@eecs.umich.edu } 11843863Ssaidi@eecs.umich.edu break; 11853823Ssaidi@eecs.umich.edu case ASI_DMMU: 11863823Ssaidi@eecs.umich.edu switch (va) { 11873906Ssaidi@eecs.umich.edu case 0x18: 11883906Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 11893906Ssaidi@eecs.umich.edu break; 11903826Ssaidi@eecs.umich.edu case 0x30: 11913826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 11923826Ssaidi@eecs.umich.edu break; 11933823Ssaidi@eecs.umich.edu case 0x80: 11943823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 11953823Ssaidi@eecs.umich.edu break; 11963823Ssaidi@eecs.umich.edu default: 11973823Ssaidi@eecs.umich.edu goto doMmuWriteError; 11983823Ssaidi@eecs.umich.edu } 11993823Ssaidi@eecs.umich.edu break; 12003863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12013863Ssaidi@eecs.umich.edu ignore = false; 12023863Ssaidi@eecs.umich.edu ctx_id = -1; 12033863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 12043863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12053863Ssaidi@eecs.umich.edu case 0: 12063863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 12073863Ssaidi@eecs.umich.edu break; 12083863Ssaidi@eecs.umich.edu case 1: 12093863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 12103863Ssaidi@eecs.umich.edu break; 12113863Ssaidi@eecs.umich.edu case 3: 12123863Ssaidi@eecs.umich.edu ctx_id = 0; 12133863Ssaidi@eecs.umich.edu break; 12143863Ssaidi@eecs.umich.edu default: 12153863Ssaidi@eecs.umich.edu ignore = true; 12163863Ssaidi@eecs.umich.edu } 12173863Ssaidi@eecs.umich.edu 12183863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 12193863Ssaidi@eecs.umich.edu case 0: // demap page 12203863Ssaidi@eecs.umich.edu if (!ignore) 12213863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12223863Ssaidi@eecs.umich.edu break; 12233863Ssaidi@eecs.umich.edu case 1: //demap context 12243863Ssaidi@eecs.umich.edu if (!ignore) 12253863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12263863Ssaidi@eecs.umich.edu break; 12273863Ssaidi@eecs.umich.edu case 2: 12283863Ssaidi@eecs.umich.edu demapAll(part_id); 12293863Ssaidi@eecs.umich.edu break; 12303863Ssaidi@eecs.umich.edu default: 12313863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12323863Ssaidi@eecs.umich.edu } 12333863Ssaidi@eecs.umich.edu break; 12343823Ssaidi@eecs.umich.edu default: 12353823Ssaidi@eecs.umich.edudoMmuWriteError: 12363823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12373823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 12383823Ssaidi@eecs.umich.edu } 12393823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 12403823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 12413806Ssaidi@eecs.umich.edu} 12423806Ssaidi@eecs.umich.edu 12433804Ssaidi@eecs.umich.eduvoid 12443804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 12453804Ssaidi@eecs.umich.edu{ 12463804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 12473804Ssaidi@eecs.umich.edu} 12483804Ssaidi@eecs.umich.edu 12493804Ssaidi@eecs.umich.eduvoid 12503804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 12513804Ssaidi@eecs.umich.edu{ 12523804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 12533804Ssaidi@eecs.umich.edu} 12543804Ssaidi@eecs.umich.edu 12553804Ssaidi@eecs.umich.edu 12563804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 12573804Ssaidi@eecs.umich.edu 12583804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 12593804Ssaidi@eecs.umich.edu 12603804Ssaidi@eecs.umich.edu Param<int> size; 12613804Ssaidi@eecs.umich.edu 12623804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 12633804Ssaidi@eecs.umich.edu 12643804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 12653804Ssaidi@eecs.umich.edu 12663804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 12673804Ssaidi@eecs.umich.edu 12683804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 12693804Ssaidi@eecs.umich.edu 12703804Ssaidi@eecs.umich.edu 12713804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 12723804Ssaidi@eecs.umich.edu{ 12733804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 12743804Ssaidi@eecs.umich.edu} 12753804Ssaidi@eecs.umich.edu 12763804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 12773804Ssaidi@eecs.umich.edu 12783804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 12793804Ssaidi@eecs.umich.edu 12803804Ssaidi@eecs.umich.edu Param<int> size; 12813804Ssaidi@eecs.umich.edu 12823804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 12833804Ssaidi@eecs.umich.edu 12843804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 12853804Ssaidi@eecs.umich.edu 12863804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 12873804Ssaidi@eecs.umich.edu 12883804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 12893804Ssaidi@eecs.umich.edu 12903804Ssaidi@eecs.umich.edu 12913804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 12923804Ssaidi@eecs.umich.edu{ 12933804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 12943804Ssaidi@eecs.umich.edu} 12953804Ssaidi@eecs.umich.edu 12963804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 12973804Ssaidi@eecs.umich.edu} 1298