tlb.cc revision 3881
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483881Ssaidi@eecs.umich.edu : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 493881Ssaidi@eecs.umich.edu cacheValid(false) 503804Ssaidi@eecs.umich.edu{ 513804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 523804Ssaidi@eecs.umich.edu if (size > 64) 533804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 543569Sgblack@eecs.umich.edu 553804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 563804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 573881Ssaidi@eecs.umich.edu 583881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 593881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 603804Ssaidi@eecs.umich.edu} 613569Sgblack@eecs.umich.edu 623804Ssaidi@eecs.umich.eduvoid 633804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 643804Ssaidi@eecs.umich.edu{ 653804Ssaidi@eecs.umich.edu MapIter i; 663881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 673804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 683804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 693804Ssaidi@eecs.umich.edu t->used = false; 703804Ssaidi@eecs.umich.edu usedEntries--; 713804Ssaidi@eecs.umich.edu } 723804Ssaidi@eecs.umich.edu } 733804Ssaidi@eecs.umich.edu} 743569Sgblack@eecs.umich.edu 753569Sgblack@eecs.umich.edu 763804Ssaidi@eecs.umich.eduvoid 773804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 783826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 793804Ssaidi@eecs.umich.edu{ 803569Sgblack@eecs.umich.edu 813569Sgblack@eecs.umich.edu 823804Ssaidi@eecs.umich.edu MapIter i; 833826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 843881Ssaidi@eecs.umich.edu TlbRange tr; 853826Ssaidi@eecs.umich.edu int x; 863811Ssaidi@eecs.umich.edu 873836Ssaidi@eecs.umich.edu cacheValid = false; 883881Ssaidi@eecs.umich.edu tr.va = va; 893881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 903881Ssaidi@eecs.umich.edu tr.contextId = context_id; 913881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 923881Ssaidi@eecs.umich.edu tr.real = real; 933836Ssaidi@eecs.umich.edu 943881Ssaidi@eecs.umich.edu 953881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 963881Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real, entry); 973881Ssaidi@eecs.umich.edu 983881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 993881Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1003881Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1013881Ssaidi@eecs.umich.edu i->second->valid = false; 1023881Ssaidi@eecs.umich.edu if (i->second->used) { 1033881Ssaidi@eecs.umich.edu i->second->used = false; 1043881Ssaidi@eecs.umich.edu usedEntries--; 1053881Ssaidi@eecs.umich.edu } 1063881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 1073881Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 1083881Ssaidi@eecs.umich.edu i->second); 1093881Ssaidi@eecs.umich.edu lookupTable.erase(i); 1103881Ssaidi@eecs.umich.edu } 1113881Ssaidi@eecs.umich.edu 1123811Ssaidi@eecs.umich.edu 1133826Ssaidi@eecs.umich.edu if (entry != -1) { 1143826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1153826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1163826Ssaidi@eecs.umich.edu } else { 1173881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1183881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1193881Ssaidi@eecs.umich.edu } else { 1203881Ssaidi@eecs.umich.edu x = lastReplaced; 1213881Ssaidi@eecs.umich.edu do { 1223881Ssaidi@eecs.umich.edu ++x; 1233881Ssaidi@eecs.umich.edu if (x == size) 1243881Ssaidi@eecs.umich.edu x = 0; 1253881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1263881Ssaidi@eecs.umich.edu goto insertAllLocked; 1273881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1283881Ssaidi@eecs.umich.edu lastReplaced = x; 1293881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1303881Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1313881Ssaidi@eecs.umich.edu } 1323881Ssaidi@eecs.umich.edu /* 1333826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1343826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 1353826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1363826Ssaidi@eecs.umich.edu break; 1373826Ssaidi@eecs.umich.edu } 1383881Ssaidi@eecs.umich.edu }*/ 1393569Sgblack@eecs.umich.edu } 1403569Sgblack@eecs.umich.edu 1413881Ssaidi@eecs.umich.eduinsertAllLocked: 1423804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1433881Ssaidi@eecs.umich.edu if (!new_entry) { 1443826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1453881Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1463881Ssaidi@eecs.umich.edu } 1473881Ssaidi@eecs.umich.edu 1483881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1493881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Using entry: %#X\n", new_entry); 1503569Sgblack@eecs.umich.edu 1513804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1523804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1533881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1543804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1553804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1563804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1573804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1583804Ssaidi@eecs.umich.edu new_entry->used = true;; 1593804Ssaidi@eecs.umich.edu new_entry->valid = true; 1603804Ssaidi@eecs.umich.edu usedEntries++; 1613569Sgblack@eecs.umich.edu 1623569Sgblack@eecs.umich.edu 1633569Sgblack@eecs.umich.edu 1643863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1653863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1663804Ssaidi@eecs.umich.edu 1673804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1683804Ssaidi@eecs.umich.edu // one we just inserted 1693804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1703804Ssaidi@eecs.umich.edu clearUsedBits(); 1713804Ssaidi@eecs.umich.edu new_entry->used = true; 1723804Ssaidi@eecs.umich.edu usedEntries++; 1733804Ssaidi@eecs.umich.edu } 1743804Ssaidi@eecs.umich.edu 1753569Sgblack@eecs.umich.edu} 1763804Ssaidi@eecs.umich.edu 1773804Ssaidi@eecs.umich.edu 1783804Ssaidi@eecs.umich.eduTlbEntry* 1793804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1803804Ssaidi@eecs.umich.edu{ 1813804Ssaidi@eecs.umich.edu MapIter i; 1823804Ssaidi@eecs.umich.edu TlbRange tr; 1833804Ssaidi@eecs.umich.edu TlbEntry *t; 1843804Ssaidi@eecs.umich.edu 1853811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 1863811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 1873804Ssaidi@eecs.umich.edu // Assemble full address structure 1883804Ssaidi@eecs.umich.edu tr.va = va; 1893863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 1903804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1913804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1923804Ssaidi@eecs.umich.edu tr.real = real; 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.edu // Try to find the entry 1953804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1963804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1973811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 1983804Ssaidi@eecs.umich.edu return NULL; 1993804Ssaidi@eecs.umich.edu } 2003804Ssaidi@eecs.umich.edu 2013804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2023804Ssaidi@eecs.umich.edu t = i->second; 2033826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2043826Ssaidi@eecs.umich.edu t->pte.size()); 2053804Ssaidi@eecs.umich.edu if (!t->used) { 2063804Ssaidi@eecs.umich.edu t->used = true; 2073804Ssaidi@eecs.umich.edu usedEntries++; 2083804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2093804Ssaidi@eecs.umich.edu clearUsedBits(); 2103804Ssaidi@eecs.umich.edu t->used = true; 2113804Ssaidi@eecs.umich.edu usedEntries++; 2123804Ssaidi@eecs.umich.edu } 2133804Ssaidi@eecs.umich.edu } 2143804Ssaidi@eecs.umich.edu 2153804Ssaidi@eecs.umich.edu return t; 2163804Ssaidi@eecs.umich.edu} 2173804Ssaidi@eecs.umich.edu 2183826Ssaidi@eecs.umich.eduvoid 2193826Ssaidi@eecs.umich.eduTLB::dumpAll() 2203826Ssaidi@eecs.umich.edu{ 2213863Ssaidi@eecs.umich.edu MapIter i; 2223826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2233826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2243826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2253826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2263826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2273826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2283826Ssaidi@eecs.umich.edu } 2293826Ssaidi@eecs.umich.edu } 2303826Ssaidi@eecs.umich.edu} 2313804Ssaidi@eecs.umich.edu 2323804Ssaidi@eecs.umich.eduvoid 2333804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2343804Ssaidi@eecs.umich.edu{ 2353804Ssaidi@eecs.umich.edu TlbRange tr; 2363804Ssaidi@eecs.umich.edu MapIter i; 2373804Ssaidi@eecs.umich.edu 2383863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2393863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2403863Ssaidi@eecs.umich.edu 2413836Ssaidi@eecs.umich.edu cacheValid = false; 2423836Ssaidi@eecs.umich.edu 2433804Ssaidi@eecs.umich.edu // Assemble full address structure 2443804Ssaidi@eecs.umich.edu tr.va = va; 2453863Ssaidi@eecs.umich.edu tr.size = MachineBytes; 2463804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2473804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2483804Ssaidi@eecs.umich.edu tr.real = real; 2493804Ssaidi@eecs.umich.edu 2503804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2513804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2523804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2533863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2543804Ssaidi@eecs.umich.edu i->second->valid = false; 2553804Ssaidi@eecs.umich.edu if (i->second->used) { 2563804Ssaidi@eecs.umich.edu i->second->used = false; 2573804Ssaidi@eecs.umich.edu usedEntries--; 2583804Ssaidi@eecs.umich.edu } 2593881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2603881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second); 2613804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2623804Ssaidi@eecs.umich.edu } 2633804Ssaidi@eecs.umich.edu} 2643804Ssaidi@eecs.umich.edu 2653804Ssaidi@eecs.umich.eduvoid 2663804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2673804Ssaidi@eecs.umich.edu{ 2683804Ssaidi@eecs.umich.edu int x; 2693863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2703863Ssaidi@eecs.umich.edu partition_id, context_id); 2713836Ssaidi@eecs.umich.edu cacheValid = false; 2723804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2733804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2743804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2753881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) { 2763881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2773881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]); 2783881Ssaidi@eecs.umich.edu } 2793804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2803804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2813804Ssaidi@eecs.umich.edu tlb[x].used = false; 2823804Ssaidi@eecs.umich.edu usedEntries--; 2833804Ssaidi@eecs.umich.edu } 2843804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2853804Ssaidi@eecs.umich.edu } 2863804Ssaidi@eecs.umich.edu } 2873804Ssaidi@eecs.umich.edu} 2883804Ssaidi@eecs.umich.edu 2893804Ssaidi@eecs.umich.eduvoid 2903804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2913804Ssaidi@eecs.umich.edu{ 2923804Ssaidi@eecs.umich.edu int x; 2933863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 2943836Ssaidi@eecs.umich.edu cacheValid = false; 2953804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2963804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2973881Ssaidi@eecs.umich.edu if (tlb[x].valid == true){ 2983881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2993881Ssaidi@eecs.umich.edu DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]); 3003881Ssaidi@eecs.umich.edu } 3013804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3023804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3033804Ssaidi@eecs.umich.edu tlb[x].used = false; 3043804Ssaidi@eecs.umich.edu usedEntries--; 3053804Ssaidi@eecs.umich.edu } 3063804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3073804Ssaidi@eecs.umich.edu } 3083804Ssaidi@eecs.umich.edu } 3093804Ssaidi@eecs.umich.edu} 3103804Ssaidi@eecs.umich.edu 3113804Ssaidi@eecs.umich.eduvoid 3123804Ssaidi@eecs.umich.eduTLB::invalidateAll() 3133804Ssaidi@eecs.umich.edu{ 3143804Ssaidi@eecs.umich.edu int x; 3153836Ssaidi@eecs.umich.edu cacheValid = false; 3163836Ssaidi@eecs.umich.edu 3173881Ssaidi@eecs.umich.edu freeList.clear(); 3183804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 3193881Ssaidi@eecs.umich.edu if (tlb[x].valid == true) 3203881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3213804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3223804Ssaidi@eecs.umich.edu } 3233804Ssaidi@eecs.umich.edu usedEntries = 0; 3243804Ssaidi@eecs.umich.edu} 3253804Ssaidi@eecs.umich.edu 3263804Ssaidi@eecs.umich.eduuint64_t 3273804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 3283881Ssaidi@eecs.umich.edu if (entry >= size) 3293881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3303881Ssaidi@eecs.umich.edu 3313804Ssaidi@eecs.umich.edu assert(entry < size); 3323881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3333881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3343881Ssaidi@eecs.umich.edu else 3353881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3363804Ssaidi@eecs.umich.edu} 3373804Ssaidi@eecs.umich.edu 3383804Ssaidi@eecs.umich.eduuint64_t 3393804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 3403804Ssaidi@eecs.umich.edu assert(entry < size); 3413804Ssaidi@eecs.umich.edu uint64_t tag; 3423881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3433881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3443804Ssaidi@eecs.umich.edu 3453881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3463881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3473881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3483804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3493804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3503804Ssaidi@eecs.umich.edu return tag; 3513804Ssaidi@eecs.umich.edu} 3523804Ssaidi@eecs.umich.edu 3533804Ssaidi@eecs.umich.edubool 3543804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3553804Ssaidi@eecs.umich.edu{ 3563804Ssaidi@eecs.umich.edu if (am) 3573804Ssaidi@eecs.umich.edu return true; 3583804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3593804Ssaidi@eecs.umich.edu return false; 3603804Ssaidi@eecs.umich.edu return true; 3613804Ssaidi@eecs.umich.edu} 3623804Ssaidi@eecs.umich.edu 3633804Ssaidi@eecs.umich.eduvoid 3643804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 3653804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3663804Ssaidi@eecs.umich.edu{ 3673804Ssaidi@eecs.umich.edu uint64_t sfsr; 3683804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3713804Ssaidi@eecs.umich.edu sfsr = 0x3; 3723804Ssaidi@eecs.umich.edu else 3733804Ssaidi@eecs.umich.edu sfsr = 1; 3743804Ssaidi@eecs.umich.edu 3753804Ssaidi@eecs.umich.edu if (write) 3763804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3773804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3783804Ssaidi@eecs.umich.edu if (se) 3793804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3803804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3813804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3823826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 3833804Ssaidi@eecs.umich.edu} 3843804Ssaidi@eecs.umich.edu 3853826Ssaidi@eecs.umich.eduvoid 3863826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 3873826Ssaidi@eecs.umich.edu{ 3883826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 3893826Ssaidi@eecs.umich.edu} 3903804Ssaidi@eecs.umich.edu 3913804Ssaidi@eecs.umich.eduvoid 3923804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 3933804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3943804Ssaidi@eecs.umich.edu{ 3953811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 3963811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 3973804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 3983804Ssaidi@eecs.umich.edu} 3993804Ssaidi@eecs.umich.edu 4003804Ssaidi@eecs.umich.eduvoid 4013826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4023826Ssaidi@eecs.umich.edu{ 4033826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 4043826Ssaidi@eecs.umich.edu} 4053826Ssaidi@eecs.umich.edu 4063826Ssaidi@eecs.umich.eduvoid 4073804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 4083804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4093804Ssaidi@eecs.umich.edu{ 4103811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4113811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4123804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 4133826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 4143804Ssaidi@eecs.umich.edu} 4153804Ssaidi@eecs.umich.edu 4163836Ssaidi@eecs.umich.eduvoid 4173826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 4183826Ssaidi@eecs.umich.edu{ 4193826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 4203826Ssaidi@eecs.umich.edu} 4213826Ssaidi@eecs.umich.edu 4223826Ssaidi@eecs.umich.edu 4233804Ssaidi@eecs.umich.edu 4243804Ssaidi@eecs.umich.eduFault 4253804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 4263804Ssaidi@eecs.umich.edu{ 4273833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4283833Ssaidi@eecs.umich.edu 4293836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4303836Ssaidi@eecs.umich.edu TlbEntry *e; 4313836Ssaidi@eecs.umich.edu 4323836Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 4333836Ssaidi@eecs.umich.edu 4343836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4353836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4363836Ssaidi@eecs.umich.edu 4373836Ssaidi@eecs.umich.edu // Be fast if we can! 4383836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4393836Ssaidi@eecs.umich.edu if (cacheEntry) { 4403836Ssaidi@eecs.umich.edu if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 4413836Ssaidi@eecs.umich.edu cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 4423836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 4433836Ssaidi@eecs.umich.edu vaddr & cacheEntry->pte.size()-1 ); 4443836Ssaidi@eecs.umich.edu return NoFault; 4453836Ssaidi@eecs.umich.edu } 4463836Ssaidi@eecs.umich.edu } else { 4473836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4483836Ssaidi@eecs.umich.edu return NoFault; 4493836Ssaidi@eecs.umich.edu } 4503836Ssaidi@eecs.umich.edu } 4513836Ssaidi@eecs.umich.edu 4523833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4533833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4543833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4553833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4563833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4573833Ssaidi@eecs.umich.edu 4583833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4593833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4603833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4613804Ssaidi@eecs.umich.edu int context; 4623804Ssaidi@eecs.umich.edu ContextType ct; 4633804Ssaidi@eecs.umich.edu int asi; 4643804Ssaidi@eecs.umich.edu bool real = false; 4653804Ssaidi@eecs.umich.edu 4663833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4673833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4683811Ssaidi@eecs.umich.edu 4693804Ssaidi@eecs.umich.edu if (tl > 0) { 4703804Ssaidi@eecs.umich.edu asi = ASI_N; 4713804Ssaidi@eecs.umich.edu ct = Nucleus; 4723804Ssaidi@eecs.umich.edu context = 0; 4733804Ssaidi@eecs.umich.edu } else { 4743804Ssaidi@eecs.umich.edu asi = ASI_P; 4753804Ssaidi@eecs.umich.edu ct = Primary; 4763833Ssaidi@eecs.umich.edu context = pri_context; 4773804Ssaidi@eecs.umich.edu } 4783804Ssaidi@eecs.umich.edu 4793833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4803836Ssaidi@eecs.umich.edu cacheValid = true; 4813836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4823836Ssaidi@eecs.umich.edu cacheEntry = NULL; 4833836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4843804Ssaidi@eecs.umich.edu return NoFault; 4853804Ssaidi@eecs.umich.edu } 4863804Ssaidi@eecs.umich.edu 4873836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4883836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4893804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 4903804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4913804Ssaidi@eecs.umich.edu } 4923804Ssaidi@eecs.umich.edu 4933804Ssaidi@eecs.umich.edu if (addr_mask) 4943804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4953804Ssaidi@eecs.umich.edu 4963804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4973804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 4983804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4993804Ssaidi@eecs.umich.edu } 5003804Ssaidi@eecs.umich.edu 5013833Ssaidi@eecs.umich.edu if (!lsu_im) { 5023836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 5033804Ssaidi@eecs.umich.edu real = true; 5043804Ssaidi@eecs.umich.edu context = 0; 5053804Ssaidi@eecs.umich.edu } else { 5063804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5073804Ssaidi@eecs.umich.edu } 5083804Ssaidi@eecs.umich.edu 5093804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5103804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 5113804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 5123804Ssaidi@eecs.umich.edu if (real) 5133804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 5143804Ssaidi@eecs.umich.edu else 5153804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 5163804Ssaidi@eecs.umich.edu } 5173804Ssaidi@eecs.umich.edu 5183804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5193804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5203804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 5213804Ssaidi@eecs.umich.edu return new InstructionAccessException; 5223804Ssaidi@eecs.umich.edu } 5233804Ssaidi@eecs.umich.edu 5243836Ssaidi@eecs.umich.edu // cache translation date for next translation 5253836Ssaidi@eecs.umich.edu cacheValid = true; 5263836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5273836Ssaidi@eecs.umich.edu cacheEntry = e; 5283836Ssaidi@eecs.umich.edu 5293826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5303836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1 ); 5313836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5323804Ssaidi@eecs.umich.edu return NoFault; 5333804Ssaidi@eecs.umich.edu} 5343804Ssaidi@eecs.umich.edu 5353804Ssaidi@eecs.umich.edu 5363804Ssaidi@eecs.umich.edu 5373804Ssaidi@eecs.umich.eduFault 5383804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 5393804Ssaidi@eecs.umich.edu{ 5403804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 5413833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 5423836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5433836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5443836Ssaidi@eecs.umich.edu ASI asi; 5453836Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 5463836Ssaidi@eecs.umich.edu bool implicit = false; 5473836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5483833Ssaidi@eecs.umich.edu 5493836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5503836Ssaidi@eecs.umich.edu vaddr, size, asi); 5513836Ssaidi@eecs.umich.edu 5523836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5533836Ssaidi@eecs.umich.edu implicit = true; 5543836Ssaidi@eecs.umich.edu 5553836Ssaidi@eecs.umich.edu if (hpriv && implicit) { 5563836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5573836Ssaidi@eecs.umich.edu return NoFault; 5583836Ssaidi@eecs.umich.edu } 5593836Ssaidi@eecs.umich.edu 5603836Ssaidi@eecs.umich.edu // Be fast if we can! 5613836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5623836Ssaidi@eecs.umich.edu if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 5633881Ssaidi@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) { 5643836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 5653836Ssaidi@eecs.umich.edu vaddr & cacheEntry[0]->pte.size()-1 ); 5663836Ssaidi@eecs.umich.edu return NoFault; 5673836Ssaidi@eecs.umich.edu } 5683836Ssaidi@eecs.umich.edu if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 5693881Ssaidi@eecs.umich.edu cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) { 5703836Ssaidi@eecs.umich.edu req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 5713836Ssaidi@eecs.umich.edu vaddr & cacheEntry[1]->pte.size()-1 ); 5723836Ssaidi@eecs.umich.edu return NoFault; 5733836Ssaidi@eecs.umich.edu } 5743836Ssaidi@eecs.umich.edu } 5753836Ssaidi@eecs.umich.edu 5763833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 5773833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 5783833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 5793833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 5803833Ssaidi@eecs.umich.edu 5813833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 5823833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 5833833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 5843833Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,47,32); 5853833Ssaidi@eecs.umich.edu 5863804Ssaidi@eecs.umich.edu bool real = false; 5873832Ssaidi@eecs.umich.edu ContextType ct = Primary; 5883832Ssaidi@eecs.umich.edu int context = 0; 5893804Ssaidi@eecs.umich.edu 5903804Ssaidi@eecs.umich.edu TlbEntry *e; 5913804Ssaidi@eecs.umich.edu 5923833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 5933833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 5943804Ssaidi@eecs.umich.edu 5953804Ssaidi@eecs.umich.edu if (implicit) { 5963804Ssaidi@eecs.umich.edu if (tl > 0) { 5973804Ssaidi@eecs.umich.edu asi = ASI_N; 5983804Ssaidi@eecs.umich.edu ct = Nucleus; 5993804Ssaidi@eecs.umich.edu context = 0; 6003804Ssaidi@eecs.umich.edu } else { 6013804Ssaidi@eecs.umich.edu asi = ASI_P; 6023804Ssaidi@eecs.umich.edu ct = Primary; 6033833Ssaidi@eecs.umich.edu context = pri_context; 6043804Ssaidi@eecs.umich.edu } 6053804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 6063823Ssaidi@eecs.umich.edu if (tl > 0 || AsiIsNucleus(asi)) { 6073804Ssaidi@eecs.umich.edu ct = Nucleus; 6083804Ssaidi@eecs.umich.edu context = 0; 6093804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 6103804Ssaidi@eecs.umich.edu ct = Secondary; 6113833Ssaidi@eecs.umich.edu context = sec_context; 6123804Ssaidi@eecs.umich.edu } else { 6133833Ssaidi@eecs.umich.edu context = pri_context; 6143804Ssaidi@eecs.umich.edu ct = Primary; //??? 6153804Ssaidi@eecs.umich.edu } 6163804Ssaidi@eecs.umich.edu 6173804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6183804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 6193804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6203804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6213804Ssaidi@eecs.umich.edu return new PrivilegedAction; 6223804Ssaidi@eecs.umich.edu } 6233804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 6243804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 6253804Ssaidi@eecs.umich.edu return new DataAccessException; 6263804Ssaidi@eecs.umich.edu } 6273804Ssaidi@eecs.umich.edu 6283826Ssaidi@eecs.umich.edu } else if (hpriv) { 6293826Ssaidi@eecs.umich.edu if (asi == ASI_P) { 6303826Ssaidi@eecs.umich.edu ct = Primary; 6313833Ssaidi@eecs.umich.edu context = pri_context; 6323826Ssaidi@eecs.umich.edu goto continueDtbFlow; 6333826Ssaidi@eecs.umich.edu } 6343804Ssaidi@eecs.umich.edu } 6353804Ssaidi@eecs.umich.edu 6363804Ssaidi@eecs.umich.edu if (!implicit) { 6373804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 6383804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6393804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 6403804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 6413804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 6423804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 6433832Ssaidi@eecs.umich.edu if (write && asi == ASI_LDTX_P) 6443832Ssaidi@eecs.umich.edu // block init store (like write hint64) 6453832Ssaidi@eecs.umich.edu goto continueDtbFlow; 6463856Ssaidi@eecs.umich.edu if (!write && asi == ASI_QUAD_LDD) 6473856Ssaidi@eecs.umich.edu goto continueDtbFlow; 6483856Ssaidi@eecs.umich.edu 6493804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 6503804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 6513804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 6523804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6533824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 6543824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 6553823Ssaidi@eecs.umich.edu 6563804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 6573804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6583804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 6593804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6603824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 6613824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6623825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 6633825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6643823Ssaidi@eecs.umich.edu 6653823Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 6663823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6673804Ssaidi@eecs.umich.edu } 6683804Ssaidi@eecs.umich.edu 6693826Ssaidi@eecs.umich.educontinueDtbFlow: 6703826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6713826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 6723826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 6733826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 6743826Ssaidi@eecs.umich.edu } 6753826Ssaidi@eecs.umich.edu 6763826Ssaidi@eecs.umich.edu if (addr_mask) 6773826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6783826Ssaidi@eecs.umich.edu 6793826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 6803826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 6813826Ssaidi@eecs.umich.edu return new DataAccessException; 6823826Ssaidi@eecs.umich.edu } 6833826Ssaidi@eecs.umich.edu 6843826Ssaidi@eecs.umich.edu 6853833Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) { 6863804Ssaidi@eecs.umich.edu real = true; 6873804Ssaidi@eecs.umich.edu context = 0; 6883804Ssaidi@eecs.umich.edu }; 6893804Ssaidi@eecs.umich.edu 6903804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 6913836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 6923804Ssaidi@eecs.umich.edu return NoFault; 6933804Ssaidi@eecs.umich.edu } 6943804Ssaidi@eecs.umich.edu 6953836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 6963804Ssaidi@eecs.umich.edu 6973804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 6983804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 6993804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 7003811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7013804Ssaidi@eecs.umich.edu if (real) 7023804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 7033804Ssaidi@eecs.umich.edu else 7043804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 7053804Ssaidi@eecs.umich.edu 7063804Ssaidi@eecs.umich.edu } 7073804Ssaidi@eecs.umich.edu 7083804Ssaidi@eecs.umich.edu 7093804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7103804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 7113804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 7123804Ssaidi@eecs.umich.edu } 7133804Ssaidi@eecs.umich.edu 7143804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 7153804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 7163804Ssaidi@eecs.umich.edu return new DataAccessException; 7173804Ssaidi@eecs.umich.edu } 7183804Ssaidi@eecs.umich.edu 7193804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 7203804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 7213804Ssaidi@eecs.umich.edu 7223804Ssaidi@eecs.umich.edu 7233804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7243804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 7253804Ssaidi@eecs.umich.edu return new DataAccessException; 7263804Ssaidi@eecs.umich.edu } 7273804Ssaidi@eecs.umich.edu 7283836Ssaidi@eecs.umich.edu // cache translation date for next translation 7293836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7303881Ssaidi@eecs.umich.edu if (!cacheValid) { 7313881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7323881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7333881Ssaidi@eecs.umich.edu } 7343881Ssaidi@eecs.umich.edu 7353836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7363836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7373836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7383836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7393836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7403836Ssaidi@eecs.umich.edu if (implicit) 7413836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7423836Ssaidi@eecs.umich.edu } 7433881Ssaidi@eecs.umich.edu cacheValid = true; 7443826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 7453836Ssaidi@eecs.umich.edu vaddr & e->pte.size()-1); 7463836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7473804Ssaidi@eecs.umich.edu return NoFault; 7483806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7493804Ssaidi@eecs.umich.edu 7503806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7513806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7523806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7533806Ssaidi@eecs.umich.edu return new DataAccessException; 7543806Ssaidi@eecs.umich.edu } 7553824Ssaidi@eecs.umich.edu goto regAccessOk; 7563824Ssaidi@eecs.umich.edu 7573824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 7583824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 7593824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7603824Ssaidi@eecs.umich.edu return new PrivilegedAction; 7613824Ssaidi@eecs.umich.edu } 7623881Ssaidi@eecs.umich.edu if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 7633824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7643824Ssaidi@eecs.umich.edu return new DataAccessException; 7653824Ssaidi@eecs.umich.edu } 7663824Ssaidi@eecs.umich.edu goto regAccessOk; 7673824Ssaidi@eecs.umich.edu 7683825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 7693825Ssaidi@eecs.umich.edu if (!hpriv) { 7703825Ssaidi@eecs.umich.edu if (priv) { 7713825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7723825Ssaidi@eecs.umich.edu return new DataAccessException; 7733825Ssaidi@eecs.umich.edu } else { 7743825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 7753825Ssaidi@eecs.umich.edu return new PrivilegedAction; 7763825Ssaidi@eecs.umich.edu } 7773825Ssaidi@eecs.umich.edu } 7783825Ssaidi@eecs.umich.edu goto regAccessOk; 7793825Ssaidi@eecs.umich.edu 7803825Ssaidi@eecs.umich.edu 7813824Ssaidi@eecs.umich.eduregAccessOk: 7823804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 7833811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 7843806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 7853806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 7863806Ssaidi@eecs.umich.edu return NoFault; 7873804Ssaidi@eecs.umich.edu}; 7883804Ssaidi@eecs.umich.edu 7893806Ssaidi@eecs.umich.eduTick 7903806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 7913806Ssaidi@eecs.umich.edu{ 7923823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 7933823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 7943833Ssaidi@eecs.umich.edu uint64_t temp, data; 7953833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 7963823Ssaidi@eecs.umich.edu 7973823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 7983823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 7993823Ssaidi@eecs.umich.edu 8003823Ssaidi@eecs.umich.edu switch (asi) { 8013823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8023823Ssaidi@eecs.umich.edu assert(va == 0); 8033823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 8043823Ssaidi@eecs.umich.edu break; 8053823Ssaidi@eecs.umich.edu case ASI_MMU: 8063823Ssaidi@eecs.umich.edu switch (va) { 8073823Ssaidi@eecs.umich.edu case 0x8: 8083823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 8093823Ssaidi@eecs.umich.edu break; 8103823Ssaidi@eecs.umich.edu case 0x10: 8113823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 8123823Ssaidi@eecs.umich.edu break; 8133823Ssaidi@eecs.umich.edu default: 8143823Ssaidi@eecs.umich.edu goto doMmuReadError; 8153823Ssaidi@eecs.umich.edu } 8163823Ssaidi@eecs.umich.edu break; 8173824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8183824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8193824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8203824Ssaidi@eecs.umich.edu break; 8213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8223823Ssaidi@eecs.umich.edu assert(va == 0); 8233823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 8243823Ssaidi@eecs.umich.edu break; 8253823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8263823Ssaidi@eecs.umich.edu assert(va == 0); 8273823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 8283823Ssaidi@eecs.umich.edu break; 8293823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8303823Ssaidi@eecs.umich.edu assert(va == 0); 8313823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 8323823Ssaidi@eecs.umich.edu break; 8333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8343823Ssaidi@eecs.umich.edu assert(va == 0); 8353823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 8363823Ssaidi@eecs.umich.edu break; 8373823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8383823Ssaidi@eecs.umich.edu assert(va == 0); 8393823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 8403823Ssaidi@eecs.umich.edu break; 8413823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8423823Ssaidi@eecs.umich.edu assert(va == 0); 8433823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 8443823Ssaidi@eecs.umich.edu break; 8453823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8463823Ssaidi@eecs.umich.edu assert(va == 0); 8473823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 8483823Ssaidi@eecs.umich.edu break; 8493823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8503823Ssaidi@eecs.umich.edu assert(va == 0); 8513823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 8523823Ssaidi@eecs.umich.edu break; 8533823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8543823Ssaidi@eecs.umich.edu assert(va == 0); 8553823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 8563823Ssaidi@eecs.umich.edu break; 8573823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8583823Ssaidi@eecs.umich.edu assert(va == 0); 8593823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 8603823Ssaidi@eecs.umich.edu break; 8613823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8623823Ssaidi@eecs.umich.edu assert(va == 0); 8633823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 8643823Ssaidi@eecs.umich.edu break; 8653823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8663823Ssaidi@eecs.umich.edu assert(va == 0); 8673823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 8683823Ssaidi@eecs.umich.edu break; 8693826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 8703826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 8713826Ssaidi@eecs.umich.edu pkt->set(0); 8723826Ssaidi@eecs.umich.edu break; 8733823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 8743823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 8753823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 8763823Ssaidi@eecs.umich.edu break; 8773826Ssaidi@eecs.umich.edu case ASI_IMMU: 8783826Ssaidi@eecs.umich.edu switch (va) { 8793833Ssaidi@eecs.umich.edu case 0x0: 8803833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 8813833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 8823833Ssaidi@eecs.umich.edu break; 8833826Ssaidi@eecs.umich.edu case 0x30: 8843826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 8853826Ssaidi@eecs.umich.edu break; 8863826Ssaidi@eecs.umich.edu default: 8873826Ssaidi@eecs.umich.edu goto doMmuReadError; 8883826Ssaidi@eecs.umich.edu } 8893826Ssaidi@eecs.umich.edu break; 8903823Ssaidi@eecs.umich.edu case ASI_DMMU: 8913823Ssaidi@eecs.umich.edu switch (va) { 8923833Ssaidi@eecs.umich.edu case 0x0: 8933833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8943833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 8953833Ssaidi@eecs.umich.edu break; 8963826Ssaidi@eecs.umich.edu case 0x30: 8973826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 8983826Ssaidi@eecs.umich.edu break; 8993823Ssaidi@eecs.umich.edu case 0x80: 9003823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 9013823Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu default: 9033823Ssaidi@eecs.umich.edu goto doMmuReadError; 9043823Ssaidi@eecs.umich.edu } 9053823Ssaidi@eecs.umich.edu break; 9063833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9073833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9083833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9093833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 9103833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9113833Ssaidi@eecs.umich.edu } else { 9123833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 9133833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9143833Ssaidi@eecs.umich.edu } 9153833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9163833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9173833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9183833Ssaidi@eecs.umich.edu pkt->set(data); 9193833Ssaidi@eecs.umich.edu break; 9203833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9213833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9223833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 9233833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 9243833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 9253833Ssaidi@eecs.umich.edu } else { 9263833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 9273833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 9283833Ssaidi@eecs.umich.edu } 9293833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 9303833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 9313833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 9323833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 9333833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 9343833Ssaidi@eecs.umich.edu pkt->set(data); 9353833Ssaidi@eecs.umich.edu break; 9363833Ssaidi@eecs.umich.edu 9373823Ssaidi@eecs.umich.edu default: 9383823Ssaidi@eecs.umich.edudoMmuReadError: 9393823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 9403823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 9413823Ssaidi@eecs.umich.edu } 9423823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 9433823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 9443806Ssaidi@eecs.umich.edu} 9453806Ssaidi@eecs.umich.edu 9463806Ssaidi@eecs.umich.eduTick 9473806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 9483806Ssaidi@eecs.umich.edu{ 9493823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 9503823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 9513823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 9523823Ssaidi@eecs.umich.edu 9533826Ssaidi@eecs.umich.edu Addr ta_insert; 9543826Ssaidi@eecs.umich.edu Addr va_insert; 9553826Ssaidi@eecs.umich.edu Addr ct_insert; 9563826Ssaidi@eecs.umich.edu int part_insert; 9573826Ssaidi@eecs.umich.edu int entry_insert = -1; 9583826Ssaidi@eecs.umich.edu bool real_insert; 9593863Ssaidi@eecs.umich.edu bool ignore; 9603863Ssaidi@eecs.umich.edu int part_id; 9613863Ssaidi@eecs.umich.edu int ctx_id; 9623826Ssaidi@eecs.umich.edu PageTableEntry pte; 9633826Ssaidi@eecs.umich.edu 9643825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 9653823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 9663823Ssaidi@eecs.umich.edu 9673823Ssaidi@eecs.umich.edu switch (asi) { 9683823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 9693823Ssaidi@eecs.umich.edu assert(va == 0); 9703823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 9713823Ssaidi@eecs.umich.edu break; 9723823Ssaidi@eecs.umich.edu case ASI_MMU: 9733823Ssaidi@eecs.umich.edu switch (va) { 9743823Ssaidi@eecs.umich.edu case 0x8: 9753823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 9763823Ssaidi@eecs.umich.edu break; 9773823Ssaidi@eecs.umich.edu case 0x10: 9783823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 9793823Ssaidi@eecs.umich.edu break; 9803823Ssaidi@eecs.umich.edu default: 9813823Ssaidi@eecs.umich.edu goto doMmuWriteError; 9823823Ssaidi@eecs.umich.edu } 9833823Ssaidi@eecs.umich.edu break; 9843824Ssaidi@eecs.umich.edu case ASI_QUEUE: 9853825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 9863824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 9873824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 9883824Ssaidi@eecs.umich.edu break; 9893823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 9903823Ssaidi@eecs.umich.edu assert(va == 0); 9913823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 9923823Ssaidi@eecs.umich.edu break; 9933823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 9943823Ssaidi@eecs.umich.edu assert(va == 0); 9953823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 9963823Ssaidi@eecs.umich.edu break; 9973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9983823Ssaidi@eecs.umich.edu assert(va == 0); 9993823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 10003823Ssaidi@eecs.umich.edu break; 10013823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 10023823Ssaidi@eecs.umich.edu assert(va == 0); 10033823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 10043823Ssaidi@eecs.umich.edu break; 10053823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 10063823Ssaidi@eecs.umich.edu assert(va == 0); 10073823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 10083823Ssaidi@eecs.umich.edu break; 10093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 10103823Ssaidi@eecs.umich.edu assert(va == 0); 10113823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 10123823Ssaidi@eecs.umich.edu break; 10133823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 10143823Ssaidi@eecs.umich.edu assert(va == 0); 10153823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 10163823Ssaidi@eecs.umich.edu break; 10173823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 10183823Ssaidi@eecs.umich.edu assert(va == 0); 10193823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 10203823Ssaidi@eecs.umich.edu break; 10213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 10223823Ssaidi@eecs.umich.edu assert(va == 0); 10233823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 10243823Ssaidi@eecs.umich.edu break; 10253823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 10263823Ssaidi@eecs.umich.edu assert(va == 0); 10273823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 10283823Ssaidi@eecs.umich.edu break; 10293823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 10303823Ssaidi@eecs.umich.edu assert(va == 0); 10313823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 10323823Ssaidi@eecs.umich.edu break; 10333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 10343823Ssaidi@eecs.umich.edu assert(va == 0); 10353823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 10363823Ssaidi@eecs.umich.edu break; 10373825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 10383825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 10393825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 10403825Ssaidi@eecs.umich.edu break; 10413823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 10423823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 10433823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 10443823Ssaidi@eecs.umich.edu break; 10453826Ssaidi@eecs.umich.edu case ASI_IMMU: 10463826Ssaidi@eecs.umich.edu switch (va) { 10473826Ssaidi@eecs.umich.edu case 0x30: 10483826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 10493826Ssaidi@eecs.umich.edu break; 10503826Ssaidi@eecs.umich.edu default: 10513826Ssaidi@eecs.umich.edu goto doMmuWriteError; 10523826Ssaidi@eecs.umich.edu } 10533826Ssaidi@eecs.umich.edu break; 10543826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 10553826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 10563826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 10573826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 10583826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 10593826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 10603826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 10613826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10623826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 10633826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 10643826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 10653826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 10663826Ssaidi@eecs.umich.edu pte, entry_insert); 10673826Ssaidi@eecs.umich.edu break; 10683826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 10693826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 10703826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 10713826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 10723826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 10733826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 10743826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 10753826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10763826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 10773826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 10783826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 10793826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 10803826Ssaidi@eecs.umich.edu break; 10813863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 10823863Ssaidi@eecs.umich.edu ignore = false; 10833863Ssaidi@eecs.umich.edu ctx_id = -1; 10843863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 10853863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 10863863Ssaidi@eecs.umich.edu case 0: 10873863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 10883863Ssaidi@eecs.umich.edu break; 10893863Ssaidi@eecs.umich.edu case 1: 10903863Ssaidi@eecs.umich.edu ignore = true; 10913863Ssaidi@eecs.umich.edu break; 10923863Ssaidi@eecs.umich.edu case 3: 10933863Ssaidi@eecs.umich.edu ctx_id = 0; 10943863Ssaidi@eecs.umich.edu break; 10953863Ssaidi@eecs.umich.edu default: 10963863Ssaidi@eecs.umich.edu ignore = true; 10973863Ssaidi@eecs.umich.edu } 10983863Ssaidi@eecs.umich.edu 10993863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11003863Ssaidi@eecs.umich.edu case 0: // demap page 11013863Ssaidi@eecs.umich.edu if (!ignore) 11023863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 11033863Ssaidi@eecs.umich.edu bits(va,9,9), ctx_id); 11043863Ssaidi@eecs.umich.edu break; 11053863Ssaidi@eecs.umich.edu case 1: //demap context 11063863Ssaidi@eecs.umich.edu if (!ignore) 11073863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapContext(part_id, ctx_id); 11083863Ssaidi@eecs.umich.edu break; 11093863Ssaidi@eecs.umich.edu case 2: 11103863Ssaidi@eecs.umich.edu tc->getITBPtr()->demapAll(part_id); 11113863Ssaidi@eecs.umich.edu break; 11123863Ssaidi@eecs.umich.edu default: 11133863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11143863Ssaidi@eecs.umich.edu } 11153863Ssaidi@eecs.umich.edu break; 11163823Ssaidi@eecs.umich.edu case ASI_DMMU: 11173823Ssaidi@eecs.umich.edu switch (va) { 11183826Ssaidi@eecs.umich.edu case 0x30: 11193826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 11203826Ssaidi@eecs.umich.edu break; 11213823Ssaidi@eecs.umich.edu case 0x80: 11223823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 11233823Ssaidi@eecs.umich.edu break; 11243823Ssaidi@eecs.umich.edu default: 11253823Ssaidi@eecs.umich.edu goto doMmuWriteError; 11263823Ssaidi@eecs.umich.edu } 11273823Ssaidi@eecs.umich.edu break; 11283863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 11293863Ssaidi@eecs.umich.edu ignore = false; 11303863Ssaidi@eecs.umich.edu ctx_id = -1; 11313863Ssaidi@eecs.umich.edu part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 11323863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11333863Ssaidi@eecs.umich.edu case 0: 11343863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 11353863Ssaidi@eecs.umich.edu break; 11363863Ssaidi@eecs.umich.edu case 1: 11373863Ssaidi@eecs.umich.edu ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 11383863Ssaidi@eecs.umich.edu break; 11393863Ssaidi@eecs.umich.edu case 3: 11403863Ssaidi@eecs.umich.edu ctx_id = 0; 11413863Ssaidi@eecs.umich.edu break; 11423863Ssaidi@eecs.umich.edu default: 11433863Ssaidi@eecs.umich.edu ignore = true; 11443863Ssaidi@eecs.umich.edu } 11453863Ssaidi@eecs.umich.edu 11463863Ssaidi@eecs.umich.edu switch(bits(va,7,6)) { 11473863Ssaidi@eecs.umich.edu case 0: // demap page 11483863Ssaidi@eecs.umich.edu if (!ignore) 11493863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 11503863Ssaidi@eecs.umich.edu break; 11513863Ssaidi@eecs.umich.edu case 1: //demap context 11523863Ssaidi@eecs.umich.edu if (!ignore) 11533863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 11543863Ssaidi@eecs.umich.edu break; 11553863Ssaidi@eecs.umich.edu case 2: 11563863Ssaidi@eecs.umich.edu demapAll(part_id); 11573863Ssaidi@eecs.umich.edu break; 11583863Ssaidi@eecs.umich.edu default: 11593863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 11603863Ssaidi@eecs.umich.edu } 11613863Ssaidi@eecs.umich.edu break; 11623823Ssaidi@eecs.umich.edu default: 11633823Ssaidi@eecs.umich.edudoMmuWriteError: 11643823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 11653823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 11663823Ssaidi@eecs.umich.edu } 11673823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 11683823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 11693806Ssaidi@eecs.umich.edu} 11703806Ssaidi@eecs.umich.edu 11713804Ssaidi@eecs.umich.eduvoid 11723804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 11733804Ssaidi@eecs.umich.edu{ 11743804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 11753804Ssaidi@eecs.umich.edu} 11763804Ssaidi@eecs.umich.edu 11773804Ssaidi@eecs.umich.eduvoid 11783804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 11793804Ssaidi@eecs.umich.edu{ 11803804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 11813804Ssaidi@eecs.umich.edu} 11823804Ssaidi@eecs.umich.edu 11833804Ssaidi@eecs.umich.edu 11843804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 11853804Ssaidi@eecs.umich.edu 11863804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 11873804Ssaidi@eecs.umich.edu 11883804Ssaidi@eecs.umich.edu Param<int> size; 11893804Ssaidi@eecs.umich.edu 11903804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 11913804Ssaidi@eecs.umich.edu 11923804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 11933804Ssaidi@eecs.umich.edu 11943804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 11953804Ssaidi@eecs.umich.edu 11963804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 11973804Ssaidi@eecs.umich.edu 11983804Ssaidi@eecs.umich.edu 11993804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 12003804Ssaidi@eecs.umich.edu{ 12013804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 12023804Ssaidi@eecs.umich.edu} 12033804Ssaidi@eecs.umich.edu 12043804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 12053804Ssaidi@eecs.umich.edu 12063804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 12073804Ssaidi@eecs.umich.edu 12083804Ssaidi@eecs.umich.edu Param<int> size; 12093804Ssaidi@eecs.umich.edu 12103804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 12113804Ssaidi@eecs.umich.edu 12123804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 12133804Ssaidi@eecs.umich.edu 12143804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 12153804Ssaidi@eecs.umich.edu 12163804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 12173804Ssaidi@eecs.umich.edu 12183804Ssaidi@eecs.umich.edu 12193804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 12203804Ssaidi@eecs.umich.edu{ 12213804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 12223804Ssaidi@eecs.umich.edu} 12233804Ssaidi@eecs.umich.edu 12243804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 12253804Ssaidi@eecs.umich.edu} 1226