tlb.cc revision 3833
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483804Ssaidi@eecs.umich.edu : SimObject(name), size(s) 493804Ssaidi@eecs.umich.edu{ 503804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 513804Ssaidi@eecs.umich.edu if (size > 64) 523804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 533569Sgblack@eecs.umich.edu 543804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 553804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 563804Ssaidi@eecs.umich.edu} 573569Sgblack@eecs.umich.edu 583804Ssaidi@eecs.umich.eduvoid 593804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 603804Ssaidi@eecs.umich.edu{ 613804Ssaidi@eecs.umich.edu MapIter i; 623804Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end();) { 633804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 643804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 653804Ssaidi@eecs.umich.edu t->used = false; 663804Ssaidi@eecs.umich.edu usedEntries--; 673804Ssaidi@eecs.umich.edu } 683804Ssaidi@eecs.umich.edu } 693804Ssaidi@eecs.umich.edu} 703569Sgblack@eecs.umich.edu 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 743826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 753804Ssaidi@eecs.umich.edu{ 763569Sgblack@eecs.umich.edu 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.edu MapIter i; 793826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 803826Ssaidi@eecs.umich.edu int x; 813811Ssaidi@eecs.umich.edu 823826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 833826Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real); 843811Ssaidi@eecs.umich.edu 853826Ssaidi@eecs.umich.edu if (entry != -1) { 863826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 873826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 883826Ssaidi@eecs.umich.edu } else { 893826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 903826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 913826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 923826Ssaidi@eecs.umich.edu break; 933826Ssaidi@eecs.umich.edu } 943804Ssaidi@eecs.umich.edu } 953569Sgblack@eecs.umich.edu } 963569Sgblack@eecs.umich.edu 973804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 983826Ssaidi@eecs.umich.edu if (!new_entry) 993826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1003569Sgblack@eecs.umich.edu 1013804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1023804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1033804Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size(); 1043804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1053804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1063804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1073804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1083804Ssaidi@eecs.umich.edu new_entry->used = true;; 1093804Ssaidi@eecs.umich.edu new_entry->valid = true; 1103804Ssaidi@eecs.umich.edu usedEntries++; 1113569Sgblack@eecs.umich.edu 1123569Sgblack@eecs.umich.edu 1133804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1143804Ssaidi@eecs.umich.edu i = lookupTable.find(new_entry->range); 1153804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1163804Ssaidi@eecs.umich.edu i->second->valid = false; 1173804Ssaidi@eecs.umich.edu if (i->second->used) { 1183804Ssaidi@eecs.umich.edu i->second->used = false; 1193804Ssaidi@eecs.umich.edu usedEntries--; 1203804Ssaidi@eecs.umich.edu } 1213811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); 1223804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1233569Sgblack@eecs.umich.edu } 1243569Sgblack@eecs.umich.edu 1253804Ssaidi@eecs.umich.edu lookupTable.insert(new_entry->range, new_entry);; 1263804Ssaidi@eecs.umich.edu 1273804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1283804Ssaidi@eecs.umich.edu // one we just inserted 1293804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1303804Ssaidi@eecs.umich.edu clearUsedBits(); 1313804Ssaidi@eecs.umich.edu new_entry->used = true; 1323804Ssaidi@eecs.umich.edu usedEntries++; 1333804Ssaidi@eecs.umich.edu } 1343804Ssaidi@eecs.umich.edu 1353569Sgblack@eecs.umich.edu} 1363804Ssaidi@eecs.umich.edu 1373804Ssaidi@eecs.umich.edu 1383804Ssaidi@eecs.umich.eduTlbEntry* 1393804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1403804Ssaidi@eecs.umich.edu{ 1413804Ssaidi@eecs.umich.edu MapIter i; 1423804Ssaidi@eecs.umich.edu TlbRange tr; 1433804Ssaidi@eecs.umich.edu TlbEntry *t; 1443804Ssaidi@eecs.umich.edu 1453811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 1463811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 1473804Ssaidi@eecs.umich.edu // Assemble full address structure 1483804Ssaidi@eecs.umich.edu tr.va = va; 1493804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1503804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1513804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1523804Ssaidi@eecs.umich.edu tr.real = real; 1533804Ssaidi@eecs.umich.edu 1543804Ssaidi@eecs.umich.edu // Try to find the entry 1553804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1563804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1573811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 1583804Ssaidi@eecs.umich.edu return NULL; 1593804Ssaidi@eecs.umich.edu } 1603804Ssaidi@eecs.umich.edu 1613804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 1623804Ssaidi@eecs.umich.edu t = i->second; 1633826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 1643826Ssaidi@eecs.umich.edu t->pte.size()); 1653804Ssaidi@eecs.umich.edu if (!t->used) { 1663804Ssaidi@eecs.umich.edu t->used = true; 1673804Ssaidi@eecs.umich.edu usedEntries++; 1683804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1693804Ssaidi@eecs.umich.edu clearUsedBits(); 1703804Ssaidi@eecs.umich.edu t->used = true; 1713804Ssaidi@eecs.umich.edu usedEntries++; 1723804Ssaidi@eecs.umich.edu } 1733804Ssaidi@eecs.umich.edu } 1743804Ssaidi@eecs.umich.edu 1753804Ssaidi@eecs.umich.edu return t; 1763804Ssaidi@eecs.umich.edu} 1773804Ssaidi@eecs.umich.edu 1783826Ssaidi@eecs.umich.eduvoid 1793826Ssaidi@eecs.umich.eduTLB::dumpAll() 1803826Ssaidi@eecs.umich.edu{ 1813826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 1823826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1833826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 1843826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 1853826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 1863826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 1873826Ssaidi@eecs.umich.edu } 1883826Ssaidi@eecs.umich.edu } 1893826Ssaidi@eecs.umich.edu} 1903804Ssaidi@eecs.umich.edu 1913804Ssaidi@eecs.umich.eduvoid 1923804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 1933804Ssaidi@eecs.umich.edu{ 1943804Ssaidi@eecs.umich.edu TlbRange tr; 1953804Ssaidi@eecs.umich.edu MapIter i; 1963804Ssaidi@eecs.umich.edu 1973804Ssaidi@eecs.umich.edu // Assemble full address structure 1983804Ssaidi@eecs.umich.edu tr.va = va; 1993804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 2003804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2013804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2023804Ssaidi@eecs.umich.edu tr.real = real; 2033804Ssaidi@eecs.umich.edu 2043804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2053804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2063804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2073804Ssaidi@eecs.umich.edu i->second->valid = false; 2083804Ssaidi@eecs.umich.edu if (i->second->used) { 2093804Ssaidi@eecs.umich.edu i->second->used = false; 2103804Ssaidi@eecs.umich.edu usedEntries--; 2113804Ssaidi@eecs.umich.edu } 2123804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2133804Ssaidi@eecs.umich.edu } 2143804Ssaidi@eecs.umich.edu} 2153804Ssaidi@eecs.umich.edu 2163804Ssaidi@eecs.umich.eduvoid 2173804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2183804Ssaidi@eecs.umich.edu{ 2193804Ssaidi@eecs.umich.edu int x; 2203804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2213804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2223804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2233804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2243804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2253804Ssaidi@eecs.umich.edu tlb[x].used = false; 2263804Ssaidi@eecs.umich.edu usedEntries--; 2273804Ssaidi@eecs.umich.edu } 2283804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2293804Ssaidi@eecs.umich.edu } 2303804Ssaidi@eecs.umich.edu } 2313804Ssaidi@eecs.umich.edu} 2323804Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.eduvoid 2343804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2353804Ssaidi@eecs.umich.edu{ 2363804Ssaidi@eecs.umich.edu int x; 2373804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2383804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2393804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2403804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2413804Ssaidi@eecs.umich.edu tlb[x].used = false; 2423804Ssaidi@eecs.umich.edu usedEntries--; 2433804Ssaidi@eecs.umich.edu } 2443804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2453804Ssaidi@eecs.umich.edu } 2463804Ssaidi@eecs.umich.edu } 2473804Ssaidi@eecs.umich.edu} 2483804Ssaidi@eecs.umich.edu 2493804Ssaidi@eecs.umich.eduvoid 2503804Ssaidi@eecs.umich.eduTLB::invalidateAll() 2513804Ssaidi@eecs.umich.edu{ 2523804Ssaidi@eecs.umich.edu int x; 2533804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2543804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2553804Ssaidi@eecs.umich.edu } 2563804Ssaidi@eecs.umich.edu usedEntries = 0; 2573804Ssaidi@eecs.umich.edu} 2583804Ssaidi@eecs.umich.edu 2593804Ssaidi@eecs.umich.eduuint64_t 2603804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 2613804Ssaidi@eecs.umich.edu assert(entry < size); 2623804Ssaidi@eecs.umich.edu return tlb[entry].pte(); 2633804Ssaidi@eecs.umich.edu} 2643804Ssaidi@eecs.umich.edu 2653804Ssaidi@eecs.umich.eduuint64_t 2663804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 2673804Ssaidi@eecs.umich.edu assert(entry < size); 2683804Ssaidi@eecs.umich.edu uint64_t tag; 2693804Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId | tlb[entry].range.va | 2713804Ssaidi@eecs.umich.edu (uint64_t)tlb[entry].range.partitionId << 61; 2723804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 2733804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 2743804Ssaidi@eecs.umich.edu return tag; 2753804Ssaidi@eecs.umich.edu} 2763804Ssaidi@eecs.umich.edu 2773804Ssaidi@eecs.umich.edubool 2783804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 2793804Ssaidi@eecs.umich.edu{ 2803804Ssaidi@eecs.umich.edu if (am) 2813804Ssaidi@eecs.umich.edu return true; 2823804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 2833804Ssaidi@eecs.umich.edu return false; 2843804Ssaidi@eecs.umich.edu return true; 2853804Ssaidi@eecs.umich.edu} 2863804Ssaidi@eecs.umich.edu 2873804Ssaidi@eecs.umich.eduvoid 2883804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 2893804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2903804Ssaidi@eecs.umich.edu{ 2913804Ssaidi@eecs.umich.edu uint64_t sfsr; 2923804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 2933804Ssaidi@eecs.umich.edu 2943804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 2953804Ssaidi@eecs.umich.edu sfsr = 0x3; 2963804Ssaidi@eecs.umich.edu else 2973804Ssaidi@eecs.umich.edu sfsr = 1; 2983804Ssaidi@eecs.umich.edu 2993804Ssaidi@eecs.umich.edu if (write) 3003804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3013804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3023804Ssaidi@eecs.umich.edu if (se) 3033804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3043804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3053804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3063826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 3073804Ssaidi@eecs.umich.edu} 3083804Ssaidi@eecs.umich.edu 3093826Ssaidi@eecs.umich.eduvoid 3103826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 3113826Ssaidi@eecs.umich.edu{ 3123826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 3133826Ssaidi@eecs.umich.edu} 3143804Ssaidi@eecs.umich.edu 3153804Ssaidi@eecs.umich.eduvoid 3163804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 3173804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3183804Ssaidi@eecs.umich.edu{ 3193811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 3203811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 3213804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 3223804Ssaidi@eecs.umich.edu} 3233804Ssaidi@eecs.umich.edu 3243804Ssaidi@eecs.umich.eduvoid 3253826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3263826Ssaidi@eecs.umich.edu{ 3273826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 3283826Ssaidi@eecs.umich.edu} 3293826Ssaidi@eecs.umich.edu 3303826Ssaidi@eecs.umich.eduvoid 3313804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 3323804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3333804Ssaidi@eecs.umich.edu{ 3343811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 3353811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 3363804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 3373826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 3383804Ssaidi@eecs.umich.edu} 3393804Ssaidi@eecs.umich.edu 3403826Ssaidi@eecs.umich.edu void 3413826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3423826Ssaidi@eecs.umich.edu{ 3433826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 3443826Ssaidi@eecs.umich.edu} 3453826Ssaidi@eecs.umich.edu 3463826Ssaidi@eecs.umich.edu 3473804Ssaidi@eecs.umich.edu 3483804Ssaidi@eecs.umich.eduFault 3493804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3503804Ssaidi@eecs.umich.edu{ 3513833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 3523833Ssaidi@eecs.umich.edu 3533833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 3543833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 3553833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 3563833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 3573833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 3583833Ssaidi@eecs.umich.edu 3593833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 3603833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 3613833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 3623833Ssaidi@eecs.umich.edu 3633804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3643804Ssaidi@eecs.umich.edu int context; 3653804Ssaidi@eecs.umich.edu ContextType ct; 3663804Ssaidi@eecs.umich.edu int asi; 3673804Ssaidi@eecs.umich.edu bool real = false; 3683804Ssaidi@eecs.umich.edu TlbEntry *e; 3693804Ssaidi@eecs.umich.edu 3703811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 3713811Ssaidi@eecs.umich.edu vaddr, req->getSize()); 3723833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 3733833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 3743811Ssaidi@eecs.umich.edu 3753804Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 3763804Ssaidi@eecs.umich.edu 3773804Ssaidi@eecs.umich.edu if (tl > 0) { 3783804Ssaidi@eecs.umich.edu asi = ASI_N; 3793804Ssaidi@eecs.umich.edu ct = Nucleus; 3803804Ssaidi@eecs.umich.edu context = 0; 3813804Ssaidi@eecs.umich.edu } else { 3823804Ssaidi@eecs.umich.edu asi = ASI_P; 3833804Ssaidi@eecs.umich.edu ct = Primary; 3843833Ssaidi@eecs.umich.edu context = pri_context; 3853804Ssaidi@eecs.umich.edu } 3863804Ssaidi@eecs.umich.edu 3873833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 3883804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 3893804Ssaidi@eecs.umich.edu return NoFault; 3903804Ssaidi@eecs.umich.edu } 3913804Ssaidi@eecs.umich.edu 3923804Ssaidi@eecs.umich.edu // If the asi is unaligned trap 3933826Ssaidi@eecs.umich.edu if (vaddr & req->getSize()-1) { 3943804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 3953804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 3963804Ssaidi@eecs.umich.edu } 3973804Ssaidi@eecs.umich.edu 3983804Ssaidi@eecs.umich.edu if (addr_mask) 3993804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4003804Ssaidi@eecs.umich.edu 4013804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4023804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 4033804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4043804Ssaidi@eecs.umich.edu } 4053804Ssaidi@eecs.umich.edu 4063833Ssaidi@eecs.umich.edu if (!lsu_im) { 4073804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, true); 4083804Ssaidi@eecs.umich.edu real = true; 4093804Ssaidi@eecs.umich.edu context = 0; 4103804Ssaidi@eecs.umich.edu } else { 4113804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4123804Ssaidi@eecs.umich.edu } 4133804Ssaidi@eecs.umich.edu 4143804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4153804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 4163804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 4173804Ssaidi@eecs.umich.edu if (real) 4183804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 4193804Ssaidi@eecs.umich.edu else 4203804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 4213804Ssaidi@eecs.umich.edu } 4223804Ssaidi@eecs.umich.edu 4233804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 4243804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 4253804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 4263804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4273804Ssaidi@eecs.umich.edu } 4283804Ssaidi@eecs.umich.edu 4293826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 4303826Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()-1 ); 4313826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); 4323804Ssaidi@eecs.umich.edu return NoFault; 4333804Ssaidi@eecs.umich.edu} 4343804Ssaidi@eecs.umich.edu 4353804Ssaidi@eecs.umich.edu 4363804Ssaidi@eecs.umich.edu 4373804Ssaidi@eecs.umich.eduFault 4383804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4393804Ssaidi@eecs.umich.edu{ 4403804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 4413833Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 4423833Ssaidi@eecs.umich.edu 4433833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4443833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4453833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4463833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4473833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 4483833Ssaidi@eecs.umich.edu 4493833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4503833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4513833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4523833Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,47,32); 4533833Ssaidi@eecs.umich.edu 4543804Ssaidi@eecs.umich.edu bool implicit = false; 4553804Ssaidi@eecs.umich.edu bool real = false; 4563804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4573811Ssaidi@eecs.umich.edu Addr size = req->getSize(); 4583832Ssaidi@eecs.umich.edu ContextType ct = Primary; 4593832Ssaidi@eecs.umich.edu int context = 0; 4603804Ssaidi@eecs.umich.edu ASI asi; 4613804Ssaidi@eecs.umich.edu 4623804Ssaidi@eecs.umich.edu TlbEntry *e; 4633804Ssaidi@eecs.umich.edu 4643811Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 4653811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 4663811Ssaidi@eecs.umich.edu vaddr, size, asi); 4673833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 4683833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_dm, part_id); 4693804Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 4703804Ssaidi@eecs.umich.edu implicit = true; 4713804Ssaidi@eecs.umich.edu 4723804Ssaidi@eecs.umich.edu if (implicit) { 4733804Ssaidi@eecs.umich.edu if (tl > 0) { 4743804Ssaidi@eecs.umich.edu asi = ASI_N; 4753804Ssaidi@eecs.umich.edu ct = Nucleus; 4763804Ssaidi@eecs.umich.edu context = 0; 4773804Ssaidi@eecs.umich.edu } else { 4783804Ssaidi@eecs.umich.edu asi = ASI_P; 4793804Ssaidi@eecs.umich.edu ct = Primary; 4803833Ssaidi@eecs.umich.edu context = pri_context; 4813804Ssaidi@eecs.umich.edu } 4823804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 4833823Ssaidi@eecs.umich.edu if (tl > 0 || AsiIsNucleus(asi)) { 4843804Ssaidi@eecs.umich.edu ct = Nucleus; 4853804Ssaidi@eecs.umich.edu context = 0; 4863804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 4873804Ssaidi@eecs.umich.edu ct = Secondary; 4883833Ssaidi@eecs.umich.edu context = sec_context; 4893804Ssaidi@eecs.umich.edu } else { 4903833Ssaidi@eecs.umich.edu context = pri_context; 4913804Ssaidi@eecs.umich.edu ct = Primary; //??? 4923804Ssaidi@eecs.umich.edu } 4933804Ssaidi@eecs.umich.edu 4943804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 4953804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 4963804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 4973804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4983804Ssaidi@eecs.umich.edu return new PrivilegedAction; 4993804Ssaidi@eecs.umich.edu } 5003804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 5013804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 5023804Ssaidi@eecs.umich.edu return new DataAccessException; 5033804Ssaidi@eecs.umich.edu } 5043804Ssaidi@eecs.umich.edu 5053826Ssaidi@eecs.umich.edu } else if (hpriv) { 5063826Ssaidi@eecs.umich.edu if (asi == ASI_P) { 5073826Ssaidi@eecs.umich.edu ct = Primary; 5083833Ssaidi@eecs.umich.edu context = pri_context; 5093826Ssaidi@eecs.umich.edu goto continueDtbFlow; 5103826Ssaidi@eecs.umich.edu } 5113804Ssaidi@eecs.umich.edu } 5123804Ssaidi@eecs.umich.edu 5133804Ssaidi@eecs.umich.edu if (!implicit) { 5143804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 5153804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 5163804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 5173804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 5183804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 5193804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 5203832Ssaidi@eecs.umich.edu if (write && asi == ASI_LDTX_P) 5213832Ssaidi@eecs.umich.edu // block init store (like write hint64) 5223832Ssaidi@eecs.umich.edu goto continueDtbFlow; 5233804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 5243804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 5253804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 5263804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 5273824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 5283824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 5293823Ssaidi@eecs.umich.edu 5303804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 5313804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 5323804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 5333804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 5343824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 5353824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 5363825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 5373825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 5383823Ssaidi@eecs.umich.edu 5393823Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 5403823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 5413804Ssaidi@eecs.umich.edu } 5423804Ssaidi@eecs.umich.edu 5433826Ssaidi@eecs.umich.educontinueDtbFlow: 5443826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 5453826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 5463826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 5473826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5483826Ssaidi@eecs.umich.edu } 5493826Ssaidi@eecs.umich.edu 5503826Ssaidi@eecs.umich.edu if (addr_mask) 5513826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5523826Ssaidi@eecs.umich.edu 5533826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5543826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 5553826Ssaidi@eecs.umich.edu return new DataAccessException; 5563826Ssaidi@eecs.umich.edu } 5573826Ssaidi@eecs.umich.edu 5583826Ssaidi@eecs.umich.edu 5593833Ssaidi@eecs.umich.edu if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) { 5603804Ssaidi@eecs.umich.edu real = true; 5613804Ssaidi@eecs.umich.edu context = 0; 5623804Ssaidi@eecs.umich.edu }; 5633804Ssaidi@eecs.umich.edu 5643804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 5653804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5663804Ssaidi@eecs.umich.edu return NoFault; 5673804Ssaidi@eecs.umich.edu } 5683804Ssaidi@eecs.umich.edu 5693804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, real, context); 5703804Ssaidi@eecs.umich.edu 5713804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5723804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 5733804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 5743811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 5753804Ssaidi@eecs.umich.edu if (real) 5763804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 5773804Ssaidi@eecs.umich.edu else 5783804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 5793804Ssaidi@eecs.umich.edu 5803804Ssaidi@eecs.umich.edu } 5813804Ssaidi@eecs.umich.edu 5823804Ssaidi@eecs.umich.edu 5833804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 5843804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 5853804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 5863804Ssaidi@eecs.umich.edu } 5873804Ssaidi@eecs.umich.edu 5883804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 5893804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 5903804Ssaidi@eecs.umich.edu return new DataAccessException; 5913804Ssaidi@eecs.umich.edu } 5923804Ssaidi@eecs.umich.edu 5933804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 5943804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 5953804Ssaidi@eecs.umich.edu 5963804Ssaidi@eecs.umich.edu 5973804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5983804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 5993804Ssaidi@eecs.umich.edu return new DataAccessException; 6003804Ssaidi@eecs.umich.edu } 6013804Ssaidi@eecs.umich.edu 6023826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 6033826Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()-1); 6043826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); 6053804Ssaidi@eecs.umich.edu return NoFault; 6063806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 6073804Ssaidi@eecs.umich.edu 6083806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 6093806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 6103806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6113806Ssaidi@eecs.umich.edu return new DataAccessException; 6123806Ssaidi@eecs.umich.edu } 6133824Ssaidi@eecs.umich.edu goto regAccessOk; 6143824Ssaidi@eecs.umich.edu 6153824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 6163824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 6173824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6183824Ssaidi@eecs.umich.edu return new PrivilegedAction; 6193824Ssaidi@eecs.umich.edu } 6203824Ssaidi@eecs.umich.edu if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 6213824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6223824Ssaidi@eecs.umich.edu return new DataAccessException; 6233824Ssaidi@eecs.umich.edu } 6243824Ssaidi@eecs.umich.edu goto regAccessOk; 6253824Ssaidi@eecs.umich.edu 6263825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 6273825Ssaidi@eecs.umich.edu if (!hpriv) { 6283825Ssaidi@eecs.umich.edu if (priv) { 6293825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6303825Ssaidi@eecs.umich.edu return new DataAccessException; 6313825Ssaidi@eecs.umich.edu } else { 6323825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6333825Ssaidi@eecs.umich.edu return new PrivilegedAction; 6343825Ssaidi@eecs.umich.edu } 6353825Ssaidi@eecs.umich.edu } 6363825Ssaidi@eecs.umich.edu goto regAccessOk; 6373825Ssaidi@eecs.umich.edu 6383825Ssaidi@eecs.umich.edu 6393824Ssaidi@eecs.umich.eduregAccessOk: 6403804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 6413811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 6423806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 6433806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 6443806Ssaidi@eecs.umich.edu return NoFault; 6453804Ssaidi@eecs.umich.edu}; 6463804Ssaidi@eecs.umich.edu 6473806Ssaidi@eecs.umich.eduTick 6483806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 6493806Ssaidi@eecs.umich.edu{ 6503823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 6513823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 6523833Ssaidi@eecs.umich.edu uint64_t temp, data; 6533833Ssaidi@eecs.umich.edu uint64_t tsbtemp, cnftemp; 6543823Ssaidi@eecs.umich.edu 6553823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 6563823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 6573823Ssaidi@eecs.umich.edu 6583823Ssaidi@eecs.umich.edu switch (asi) { 6593823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 6603823Ssaidi@eecs.umich.edu assert(va == 0); 6613823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 6623823Ssaidi@eecs.umich.edu break; 6633823Ssaidi@eecs.umich.edu case ASI_MMU: 6643823Ssaidi@eecs.umich.edu switch (va) { 6653823Ssaidi@eecs.umich.edu case 0x8: 6663823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 6673823Ssaidi@eecs.umich.edu break; 6683823Ssaidi@eecs.umich.edu case 0x10: 6693823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 6703823Ssaidi@eecs.umich.edu break; 6713823Ssaidi@eecs.umich.edu default: 6723823Ssaidi@eecs.umich.edu goto doMmuReadError; 6733823Ssaidi@eecs.umich.edu } 6743823Ssaidi@eecs.umich.edu break; 6753824Ssaidi@eecs.umich.edu case ASI_QUEUE: 6763824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 6773824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 6783824Ssaidi@eecs.umich.edu break; 6793823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 6803823Ssaidi@eecs.umich.edu assert(va == 0); 6813823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 6823823Ssaidi@eecs.umich.edu break; 6833823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 6843823Ssaidi@eecs.umich.edu assert(va == 0); 6853823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 6863823Ssaidi@eecs.umich.edu break; 6873823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 6883823Ssaidi@eecs.umich.edu assert(va == 0); 6893823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 6903823Ssaidi@eecs.umich.edu break; 6913823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 6923823Ssaidi@eecs.umich.edu assert(va == 0); 6933823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 6943823Ssaidi@eecs.umich.edu break; 6953823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 6963823Ssaidi@eecs.umich.edu assert(va == 0); 6973823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 6983823Ssaidi@eecs.umich.edu break; 6993823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 7003823Ssaidi@eecs.umich.edu assert(va == 0); 7013823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 7023823Ssaidi@eecs.umich.edu break; 7033823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 7043823Ssaidi@eecs.umich.edu assert(va == 0); 7053823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 7063823Ssaidi@eecs.umich.edu break; 7073823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 7083823Ssaidi@eecs.umich.edu assert(va == 0); 7093823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 7103823Ssaidi@eecs.umich.edu break; 7113823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 7123823Ssaidi@eecs.umich.edu assert(va == 0); 7133823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 7143823Ssaidi@eecs.umich.edu break; 7153823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 7163823Ssaidi@eecs.umich.edu assert(va == 0); 7173823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 7183823Ssaidi@eecs.umich.edu break; 7193823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 7203823Ssaidi@eecs.umich.edu assert(va == 0); 7213823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 7223823Ssaidi@eecs.umich.edu break; 7233823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 7243823Ssaidi@eecs.umich.edu assert(va == 0); 7253823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 7263823Ssaidi@eecs.umich.edu break; 7273826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 7283826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 7293826Ssaidi@eecs.umich.edu pkt->set(0); 7303826Ssaidi@eecs.umich.edu break; 7313823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 7323823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 7333823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 7343823Ssaidi@eecs.umich.edu break; 7353826Ssaidi@eecs.umich.edu case ASI_IMMU: 7363826Ssaidi@eecs.umich.edu switch (va) { 7373833Ssaidi@eecs.umich.edu case 0x0: 7383833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 7393833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 7403833Ssaidi@eecs.umich.edu break; 7413826Ssaidi@eecs.umich.edu case 0x30: 7423826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 7433826Ssaidi@eecs.umich.edu break; 7443826Ssaidi@eecs.umich.edu default: 7453826Ssaidi@eecs.umich.edu goto doMmuReadError; 7463826Ssaidi@eecs.umich.edu } 7473826Ssaidi@eecs.umich.edu break; 7483823Ssaidi@eecs.umich.edu case ASI_DMMU: 7493823Ssaidi@eecs.umich.edu switch (va) { 7503833Ssaidi@eecs.umich.edu case 0x0: 7513833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 7523833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 7533833Ssaidi@eecs.umich.edu break; 7543826Ssaidi@eecs.umich.edu case 0x30: 7553826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 7563826Ssaidi@eecs.umich.edu break; 7573823Ssaidi@eecs.umich.edu case 0x80: 7583823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 7593823Ssaidi@eecs.umich.edu break; 7603823Ssaidi@eecs.umich.edu default: 7613823Ssaidi@eecs.umich.edu goto doMmuReadError; 7623823Ssaidi@eecs.umich.edu } 7633823Ssaidi@eecs.umich.edu break; 7643833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 7653833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 7663833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 7673833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 7683833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 7693833Ssaidi@eecs.umich.edu } else { 7703833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 7713833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 7723833Ssaidi@eecs.umich.edu } 7733833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 7743833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 7753833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 7763833Ssaidi@eecs.umich.edu warn("base addr: %#X tag access: %#X page size: %#X tsb size: %#X\n", 7773833Ssaidi@eecs.umich.edu bits(tsbtemp,63,13), temp, bits(cnftemp,2,0), bits(tsbtemp,3,0)); 7783833Ssaidi@eecs.umich.edu pkt->set(data); 7793833Ssaidi@eecs.umich.edu break; 7803833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 7813833Ssaidi@eecs.umich.edu temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 7823833Ssaidi@eecs.umich.edu if (bits(temp,12,0) == 0) { 7833833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 7843833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 7853833Ssaidi@eecs.umich.edu } else { 7863833Ssaidi@eecs.umich.edu tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 7873833Ssaidi@eecs.umich.edu cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 7883833Ssaidi@eecs.umich.edu } 7893833Ssaidi@eecs.umich.edu data = mbits(tsbtemp,63,13); 7903833Ssaidi@eecs.umich.edu if (bits(tsbtemp,12,12)) 7913833Ssaidi@eecs.umich.edu data |= ULL(1) << (13+bits(tsbtemp,3,0)); 7923833Ssaidi@eecs.umich.edu data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 7933833Ssaidi@eecs.umich.edu mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 7943833Ssaidi@eecs.umich.edu pkt->set(data); 7953833Ssaidi@eecs.umich.edu break; 7963833Ssaidi@eecs.umich.edu 7973823Ssaidi@eecs.umich.edu default: 7983823Ssaidi@eecs.umich.edudoMmuReadError: 7993823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 8003823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 8013823Ssaidi@eecs.umich.edu } 8023823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 8033823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 8043806Ssaidi@eecs.umich.edu} 8053806Ssaidi@eecs.umich.edu 8063806Ssaidi@eecs.umich.eduTick 8073806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 8083806Ssaidi@eecs.umich.edu{ 8093823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 8103823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8113823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 8123823Ssaidi@eecs.umich.edu 8133826Ssaidi@eecs.umich.edu Addr ta_insert; 8143826Ssaidi@eecs.umich.edu Addr va_insert; 8153826Ssaidi@eecs.umich.edu Addr ct_insert; 8163826Ssaidi@eecs.umich.edu int part_insert; 8173826Ssaidi@eecs.umich.edu int entry_insert = -1; 8183826Ssaidi@eecs.umich.edu bool real_insert; 8193826Ssaidi@eecs.umich.edu PageTableEntry pte; 8203826Ssaidi@eecs.umich.edu 8213825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 8223823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 8233823Ssaidi@eecs.umich.edu 8243823Ssaidi@eecs.umich.edu switch (asi) { 8253823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8263823Ssaidi@eecs.umich.edu assert(va == 0); 8273823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 8283823Ssaidi@eecs.umich.edu break; 8293823Ssaidi@eecs.umich.edu case ASI_MMU: 8303823Ssaidi@eecs.umich.edu switch (va) { 8313823Ssaidi@eecs.umich.edu case 0x8: 8323823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 8333823Ssaidi@eecs.umich.edu break; 8343823Ssaidi@eecs.umich.edu case 0x10: 8353823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 8363823Ssaidi@eecs.umich.edu break; 8373823Ssaidi@eecs.umich.edu default: 8383823Ssaidi@eecs.umich.edu goto doMmuWriteError; 8393823Ssaidi@eecs.umich.edu } 8403823Ssaidi@eecs.umich.edu break; 8413824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8423825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 8433824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 8443824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 8453824Ssaidi@eecs.umich.edu break; 8463823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8473823Ssaidi@eecs.umich.edu assert(va == 0); 8483823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 8493823Ssaidi@eecs.umich.edu break; 8503823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8513823Ssaidi@eecs.umich.edu assert(va == 0); 8523823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 8533823Ssaidi@eecs.umich.edu break; 8543823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8553823Ssaidi@eecs.umich.edu assert(va == 0); 8563823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 8573823Ssaidi@eecs.umich.edu break; 8583823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8593823Ssaidi@eecs.umich.edu assert(va == 0); 8603823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 8613823Ssaidi@eecs.umich.edu break; 8623823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8633823Ssaidi@eecs.umich.edu assert(va == 0); 8643823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 8653823Ssaidi@eecs.umich.edu break; 8663823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8673823Ssaidi@eecs.umich.edu assert(va == 0); 8683823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 8693823Ssaidi@eecs.umich.edu break; 8703823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8713823Ssaidi@eecs.umich.edu assert(va == 0); 8723823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 8733823Ssaidi@eecs.umich.edu break; 8743823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8753823Ssaidi@eecs.umich.edu assert(va == 0); 8763823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 8773823Ssaidi@eecs.umich.edu break; 8783823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8793823Ssaidi@eecs.umich.edu assert(va == 0); 8803823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8833823Ssaidi@eecs.umich.edu assert(va == 0); 8843823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 8853823Ssaidi@eecs.umich.edu break; 8863823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8873823Ssaidi@eecs.umich.edu assert(va == 0); 8883823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 8893823Ssaidi@eecs.umich.edu break; 8903823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8913823Ssaidi@eecs.umich.edu assert(va == 0); 8923823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 8933823Ssaidi@eecs.umich.edu break; 8943825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 8953825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 8963825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 8973825Ssaidi@eecs.umich.edu break; 8983823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 8993823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9003823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 9013823Ssaidi@eecs.umich.edu break; 9023826Ssaidi@eecs.umich.edu case ASI_IMMU: 9033826Ssaidi@eecs.umich.edu switch (va) { 9043826Ssaidi@eecs.umich.edu case 0x30: 9053826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 9063826Ssaidi@eecs.umich.edu break; 9073826Ssaidi@eecs.umich.edu default: 9083826Ssaidi@eecs.umich.edu goto doMmuWriteError; 9093826Ssaidi@eecs.umich.edu } 9103826Ssaidi@eecs.umich.edu break; 9113826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 9123826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 9133826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 9143826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 9153826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 9163826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 9173826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 9183826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 9193826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 9203826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 9213826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 9223826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 9233826Ssaidi@eecs.umich.edu pte, entry_insert); 9243826Ssaidi@eecs.umich.edu break; 9253826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 9263826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 9273826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 9283826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 9293826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 9303826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 9313826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 9323826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 9333826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 9343826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 9353826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 9363826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 9373826Ssaidi@eecs.umich.edu break; 9383823Ssaidi@eecs.umich.edu case ASI_DMMU: 9393823Ssaidi@eecs.umich.edu switch (va) { 9403826Ssaidi@eecs.umich.edu case 0x30: 9413826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 9423826Ssaidi@eecs.umich.edu break; 9433823Ssaidi@eecs.umich.edu case 0x80: 9443823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 9453823Ssaidi@eecs.umich.edu break; 9463823Ssaidi@eecs.umich.edu default: 9473823Ssaidi@eecs.umich.edu goto doMmuWriteError; 9483823Ssaidi@eecs.umich.edu } 9493823Ssaidi@eecs.umich.edu break; 9503823Ssaidi@eecs.umich.edu default: 9513823Ssaidi@eecs.umich.edudoMmuWriteError: 9523823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 9533823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 9543823Ssaidi@eecs.umich.edu } 9553823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 9563823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 9573806Ssaidi@eecs.umich.edu} 9583806Ssaidi@eecs.umich.edu 9593804Ssaidi@eecs.umich.eduvoid 9603804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 9613804Ssaidi@eecs.umich.edu{ 9623804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 9633804Ssaidi@eecs.umich.edu} 9643804Ssaidi@eecs.umich.edu 9653804Ssaidi@eecs.umich.eduvoid 9663804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 9673804Ssaidi@eecs.umich.edu{ 9683804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 9693804Ssaidi@eecs.umich.edu} 9703804Ssaidi@eecs.umich.edu 9713804Ssaidi@eecs.umich.edu 9723804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 9733804Ssaidi@eecs.umich.edu 9743804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 9753804Ssaidi@eecs.umich.edu 9763804Ssaidi@eecs.umich.edu Param<int> size; 9773804Ssaidi@eecs.umich.edu 9783804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 9793804Ssaidi@eecs.umich.edu 9803804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 9813804Ssaidi@eecs.umich.edu 9823804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 9833804Ssaidi@eecs.umich.edu 9843804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 9853804Ssaidi@eecs.umich.edu 9863804Ssaidi@eecs.umich.edu 9873804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 9883804Ssaidi@eecs.umich.edu{ 9893804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 9903804Ssaidi@eecs.umich.edu} 9913804Ssaidi@eecs.umich.edu 9923804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 9933804Ssaidi@eecs.umich.edu 9943804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 9953804Ssaidi@eecs.umich.edu 9963804Ssaidi@eecs.umich.edu Param<int> size; 9973804Ssaidi@eecs.umich.edu 9983804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 9993804Ssaidi@eecs.umich.edu 10003804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 10013804Ssaidi@eecs.umich.edu 10023804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 10033804Ssaidi@eecs.umich.edu 10043804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 10053804Ssaidi@eecs.umich.edu 10063804Ssaidi@eecs.umich.edu 10073804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 10083804Ssaidi@eecs.umich.edu{ 10093804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 10103804Ssaidi@eecs.umich.edu} 10113804Ssaidi@eecs.umich.edu 10123804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 10133804Ssaidi@eecs.umich.edu} 1014