tlb.cc revision 3832
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323811Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 333569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 343824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 353811Ssaidi@eecs.umich.edu#include "base/trace.hh" 363811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 373823Ssaidi@eecs.umich.edu#include "cpu/base.hh" 383823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 393823Ssaidi@eecs.umich.edu#include "mem/request.hh" 403569Sgblack@eecs.umich.edu#include "sim/builder.hh" 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 433804Ssaidi@eecs.umich.edu * */ 443569Sgblack@eecs.umich.edunamespace SparcISA 453569Sgblack@eecs.umich.edu{ 463569Sgblack@eecs.umich.edu 473804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 483804Ssaidi@eecs.umich.edu : SimObject(name), size(s) 493804Ssaidi@eecs.umich.edu{ 503804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 513804Ssaidi@eecs.umich.edu if (size > 64) 523804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 533569Sgblack@eecs.umich.edu 543804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 553804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 563804Ssaidi@eecs.umich.edu} 573569Sgblack@eecs.umich.edu 583804Ssaidi@eecs.umich.eduvoid 593804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 603804Ssaidi@eecs.umich.edu{ 613804Ssaidi@eecs.umich.edu MapIter i; 623804Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end();) { 633804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 643804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 653804Ssaidi@eecs.umich.edu t->used = false; 663804Ssaidi@eecs.umich.edu usedEntries--; 673804Ssaidi@eecs.umich.edu } 683804Ssaidi@eecs.umich.edu } 693804Ssaidi@eecs.umich.edu} 703569Sgblack@eecs.umich.edu 713569Sgblack@eecs.umich.edu 723804Ssaidi@eecs.umich.eduvoid 733804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 743826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 753804Ssaidi@eecs.umich.edu{ 763569Sgblack@eecs.umich.edu 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.edu MapIter i; 793826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 803826Ssaidi@eecs.umich.edu int x; 813811Ssaidi@eecs.umich.edu 823826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 833826Ssaidi@eecs.umich.edu va, PTE.paddr(), partition_id, context_id, (int)real); 843811Ssaidi@eecs.umich.edu 853826Ssaidi@eecs.umich.edu if (entry != -1) { 863826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 873826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 883826Ssaidi@eecs.umich.edu } else { 893826Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 903826Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 913826Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 923826Ssaidi@eecs.umich.edu break; 933826Ssaidi@eecs.umich.edu } 943804Ssaidi@eecs.umich.edu } 953569Sgblack@eecs.umich.edu } 963569Sgblack@eecs.umich.edu 973804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 983826Ssaidi@eecs.umich.edu if (!new_entry) 993826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1003569Sgblack@eecs.umich.edu 1013804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1023804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1033804Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size(); 1043804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1053804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1063804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1073804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1083804Ssaidi@eecs.umich.edu new_entry->used = true;; 1093804Ssaidi@eecs.umich.edu new_entry->valid = true; 1103804Ssaidi@eecs.umich.edu usedEntries++; 1113569Sgblack@eecs.umich.edu 1123569Sgblack@eecs.umich.edu 1133804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1143804Ssaidi@eecs.umich.edu i = lookupTable.find(new_entry->range); 1153804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1163804Ssaidi@eecs.umich.edu i->second->valid = false; 1173804Ssaidi@eecs.umich.edu if (i->second->used) { 1183804Ssaidi@eecs.umich.edu i->second->used = false; 1193804Ssaidi@eecs.umich.edu usedEntries--; 1203804Ssaidi@eecs.umich.edu } 1213811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); 1223804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1233569Sgblack@eecs.umich.edu } 1243569Sgblack@eecs.umich.edu 1253804Ssaidi@eecs.umich.edu lookupTable.insert(new_entry->range, new_entry);; 1263804Ssaidi@eecs.umich.edu 1273804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1283804Ssaidi@eecs.umich.edu // one we just inserted 1293804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1303804Ssaidi@eecs.umich.edu clearUsedBits(); 1313804Ssaidi@eecs.umich.edu new_entry->used = true; 1323804Ssaidi@eecs.umich.edu usedEntries++; 1333804Ssaidi@eecs.umich.edu } 1343804Ssaidi@eecs.umich.edu 1353569Sgblack@eecs.umich.edu} 1363804Ssaidi@eecs.umich.edu 1373804Ssaidi@eecs.umich.edu 1383804Ssaidi@eecs.umich.eduTlbEntry* 1393804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1403804Ssaidi@eecs.umich.edu{ 1413804Ssaidi@eecs.umich.edu MapIter i; 1423804Ssaidi@eecs.umich.edu TlbRange tr; 1433804Ssaidi@eecs.umich.edu TlbEntry *t; 1443804Ssaidi@eecs.umich.edu 1453811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 1463811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 1473804Ssaidi@eecs.umich.edu // Assemble full address structure 1483804Ssaidi@eecs.umich.edu tr.va = va; 1493804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1503804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1513804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1523804Ssaidi@eecs.umich.edu tr.real = real; 1533804Ssaidi@eecs.umich.edu 1543804Ssaidi@eecs.umich.edu // Try to find the entry 1553804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1563804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1573811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 1583804Ssaidi@eecs.umich.edu return NULL; 1593804Ssaidi@eecs.umich.edu } 1603804Ssaidi@eecs.umich.edu 1613804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 1623804Ssaidi@eecs.umich.edu t = i->second; 1633826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 1643826Ssaidi@eecs.umich.edu t->pte.size()); 1653804Ssaidi@eecs.umich.edu if (!t->used) { 1663804Ssaidi@eecs.umich.edu t->used = true; 1673804Ssaidi@eecs.umich.edu usedEntries++; 1683804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1693804Ssaidi@eecs.umich.edu clearUsedBits(); 1703804Ssaidi@eecs.umich.edu t->used = true; 1713804Ssaidi@eecs.umich.edu usedEntries++; 1723804Ssaidi@eecs.umich.edu } 1733804Ssaidi@eecs.umich.edu } 1743804Ssaidi@eecs.umich.edu 1753804Ssaidi@eecs.umich.edu return t; 1763804Ssaidi@eecs.umich.edu} 1773804Ssaidi@eecs.umich.edu 1783826Ssaidi@eecs.umich.eduvoid 1793826Ssaidi@eecs.umich.eduTLB::dumpAll() 1803826Ssaidi@eecs.umich.edu{ 1813826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 1823826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1833826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 1843826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 1853826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 1863826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 1873826Ssaidi@eecs.umich.edu } 1883826Ssaidi@eecs.umich.edu } 1893826Ssaidi@eecs.umich.edu} 1903804Ssaidi@eecs.umich.edu 1913804Ssaidi@eecs.umich.eduvoid 1923804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 1933804Ssaidi@eecs.umich.edu{ 1943804Ssaidi@eecs.umich.edu TlbRange tr; 1953804Ssaidi@eecs.umich.edu MapIter i; 1963804Ssaidi@eecs.umich.edu 1973804Ssaidi@eecs.umich.edu // Assemble full address structure 1983804Ssaidi@eecs.umich.edu tr.va = va; 1993804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 2003804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2013804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2023804Ssaidi@eecs.umich.edu tr.real = real; 2033804Ssaidi@eecs.umich.edu 2043804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2053804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2063804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2073804Ssaidi@eecs.umich.edu i->second->valid = false; 2083804Ssaidi@eecs.umich.edu if (i->second->used) { 2093804Ssaidi@eecs.umich.edu i->second->used = false; 2103804Ssaidi@eecs.umich.edu usedEntries--; 2113804Ssaidi@eecs.umich.edu } 2123804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2133804Ssaidi@eecs.umich.edu } 2143804Ssaidi@eecs.umich.edu} 2153804Ssaidi@eecs.umich.edu 2163804Ssaidi@eecs.umich.eduvoid 2173804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2183804Ssaidi@eecs.umich.edu{ 2193804Ssaidi@eecs.umich.edu int x; 2203804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2213804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2223804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 2233804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2243804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2253804Ssaidi@eecs.umich.edu tlb[x].used = false; 2263804Ssaidi@eecs.umich.edu usedEntries--; 2273804Ssaidi@eecs.umich.edu } 2283804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2293804Ssaidi@eecs.umich.edu } 2303804Ssaidi@eecs.umich.edu } 2313804Ssaidi@eecs.umich.edu} 2323804Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.eduvoid 2343804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2353804Ssaidi@eecs.umich.edu{ 2363804Ssaidi@eecs.umich.edu int x; 2373804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2383804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2393804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2403804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2413804Ssaidi@eecs.umich.edu tlb[x].used = false; 2423804Ssaidi@eecs.umich.edu usedEntries--; 2433804Ssaidi@eecs.umich.edu } 2443804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2453804Ssaidi@eecs.umich.edu } 2463804Ssaidi@eecs.umich.edu } 2473804Ssaidi@eecs.umich.edu} 2483804Ssaidi@eecs.umich.edu 2493804Ssaidi@eecs.umich.eduvoid 2503804Ssaidi@eecs.umich.eduTLB::invalidateAll() 2513804Ssaidi@eecs.umich.edu{ 2523804Ssaidi@eecs.umich.edu int x; 2533804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2543804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2553804Ssaidi@eecs.umich.edu } 2563804Ssaidi@eecs.umich.edu usedEntries = 0; 2573804Ssaidi@eecs.umich.edu} 2583804Ssaidi@eecs.umich.edu 2593804Ssaidi@eecs.umich.eduuint64_t 2603804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 2613804Ssaidi@eecs.umich.edu assert(entry < size); 2623804Ssaidi@eecs.umich.edu return tlb[entry].pte(); 2633804Ssaidi@eecs.umich.edu} 2643804Ssaidi@eecs.umich.edu 2653804Ssaidi@eecs.umich.eduuint64_t 2663804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 2673804Ssaidi@eecs.umich.edu assert(entry < size); 2683804Ssaidi@eecs.umich.edu uint64_t tag; 2693804Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId | tlb[entry].range.va | 2713804Ssaidi@eecs.umich.edu (uint64_t)tlb[entry].range.partitionId << 61; 2723804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 2733804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 2743804Ssaidi@eecs.umich.edu return tag; 2753804Ssaidi@eecs.umich.edu} 2763804Ssaidi@eecs.umich.edu 2773804Ssaidi@eecs.umich.edubool 2783804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 2793804Ssaidi@eecs.umich.edu{ 2803804Ssaidi@eecs.umich.edu if (am) 2813804Ssaidi@eecs.umich.edu return true; 2823804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 2833804Ssaidi@eecs.umich.edu return false; 2843804Ssaidi@eecs.umich.edu return true; 2853804Ssaidi@eecs.umich.edu} 2863804Ssaidi@eecs.umich.edu 2873804Ssaidi@eecs.umich.eduvoid 2883804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 2893804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2903804Ssaidi@eecs.umich.edu{ 2913804Ssaidi@eecs.umich.edu uint64_t sfsr; 2923804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 2933804Ssaidi@eecs.umich.edu 2943804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 2953804Ssaidi@eecs.umich.edu sfsr = 0x3; 2963804Ssaidi@eecs.umich.edu else 2973804Ssaidi@eecs.umich.edu sfsr = 1; 2983804Ssaidi@eecs.umich.edu 2993804Ssaidi@eecs.umich.edu if (write) 3003804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3013804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3023804Ssaidi@eecs.umich.edu if (se) 3033804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3043804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3053804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3063826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, sfsr); 3073804Ssaidi@eecs.umich.edu} 3083804Ssaidi@eecs.umich.edu 3093826Ssaidi@eecs.umich.eduvoid 3103826Ssaidi@eecs.umich.eduTLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 3113826Ssaidi@eecs.umich.edu{ 3123826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 3133826Ssaidi@eecs.umich.edu} 3143804Ssaidi@eecs.umich.edu 3153804Ssaidi@eecs.umich.eduvoid 3163804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 3173804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3183804Ssaidi@eecs.umich.edu{ 3193811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 3203811Ssaidi@eecs.umich.edu (int)write, ct, ft, asi); 3213804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 3223804Ssaidi@eecs.umich.edu} 3233804Ssaidi@eecs.umich.edu 3243804Ssaidi@eecs.umich.eduvoid 3253826Ssaidi@eecs.umich.eduITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3263826Ssaidi@eecs.umich.edu{ 3273826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 3283826Ssaidi@eecs.umich.edu} 3293826Ssaidi@eecs.umich.edu 3303826Ssaidi@eecs.umich.eduvoid 3313804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 3323804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 3333804Ssaidi@eecs.umich.edu{ 3343811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 3353811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 3363804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 3373826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 3383804Ssaidi@eecs.umich.edu} 3393804Ssaidi@eecs.umich.edu 3403826Ssaidi@eecs.umich.edu void 3413826Ssaidi@eecs.umich.eduDTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 3423826Ssaidi@eecs.umich.edu{ 3433826Ssaidi@eecs.umich.edu TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 3443826Ssaidi@eecs.umich.edu} 3453826Ssaidi@eecs.umich.edu 3463826Ssaidi@eecs.umich.edu 3473804Ssaidi@eecs.umich.edu 3483804Ssaidi@eecs.umich.eduFault 3493804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3503804Ssaidi@eecs.umich.edu{ 3513804Ssaidi@eecs.umich.edu uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 3523804Ssaidi@eecs.umich.edu uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 3533804Ssaidi@eecs.umich.edu bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1; 3543804Ssaidi@eecs.umich.edu uint64_t tl = tc->readMiscReg(MISCREG_TL); 3553804Ssaidi@eecs.umich.edu uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 3563804Ssaidi@eecs.umich.edu bool addr_mask = pstate >> 3 & 0x1; 3573804Ssaidi@eecs.umich.edu bool priv = pstate >> 2 & 0x1; 3583804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3593804Ssaidi@eecs.umich.edu int context; 3603804Ssaidi@eecs.umich.edu ContextType ct; 3613804Ssaidi@eecs.umich.edu int asi; 3623804Ssaidi@eecs.umich.edu bool real = false; 3633804Ssaidi@eecs.umich.edu TlbEntry *e; 3643804Ssaidi@eecs.umich.edu 3653811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 3663811Ssaidi@eecs.umich.edu vaddr, req->getSize()); 3673825Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n", 3683825Ssaidi@eecs.umich.edu pstate, hpstate, lsuIm, part_id); 3693811Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 3713804Ssaidi@eecs.umich.edu 3723804Ssaidi@eecs.umich.edu if (tl > 0) { 3733804Ssaidi@eecs.umich.edu asi = ASI_N; 3743804Ssaidi@eecs.umich.edu ct = Nucleus; 3753804Ssaidi@eecs.umich.edu context = 0; 3763804Ssaidi@eecs.umich.edu } else { 3773804Ssaidi@eecs.umich.edu asi = ASI_P; 3783804Ssaidi@eecs.umich.edu ct = Primary; 3793804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 3803804Ssaidi@eecs.umich.edu } 3813804Ssaidi@eecs.umich.edu 3823804Ssaidi@eecs.umich.edu if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) { 3833804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 3843804Ssaidi@eecs.umich.edu return NoFault; 3853804Ssaidi@eecs.umich.edu } 3863804Ssaidi@eecs.umich.edu 3873804Ssaidi@eecs.umich.edu // If the asi is unaligned trap 3883826Ssaidi@eecs.umich.edu if (vaddr & req->getSize()-1) { 3893804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 3903804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 3913804Ssaidi@eecs.umich.edu } 3923804Ssaidi@eecs.umich.edu 3933804Ssaidi@eecs.umich.edu if (addr_mask) 3943804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 3953804Ssaidi@eecs.umich.edu 3963804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 3973804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 3983804Ssaidi@eecs.umich.edu return new InstructionAccessException; 3993804Ssaidi@eecs.umich.edu } 4003804Ssaidi@eecs.umich.edu 4013825Ssaidi@eecs.umich.edu if (!lsuIm) { 4023804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, true); 4033804Ssaidi@eecs.umich.edu real = true; 4043804Ssaidi@eecs.umich.edu context = 0; 4053804Ssaidi@eecs.umich.edu } else { 4063804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4073804Ssaidi@eecs.umich.edu } 4083804Ssaidi@eecs.umich.edu 4093804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4103804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 4113804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 4123804Ssaidi@eecs.umich.edu if (real) 4133804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 4143804Ssaidi@eecs.umich.edu else 4153804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 4163804Ssaidi@eecs.umich.edu } 4173804Ssaidi@eecs.umich.edu 4183804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 4193804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 4203804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 4213804Ssaidi@eecs.umich.edu return new InstructionAccessException; 4223804Ssaidi@eecs.umich.edu } 4233804Ssaidi@eecs.umich.edu 4243826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 4253826Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()-1 ); 4263826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); 4273804Ssaidi@eecs.umich.edu return NoFault; 4283804Ssaidi@eecs.umich.edu} 4293804Ssaidi@eecs.umich.edu 4303804Ssaidi@eecs.umich.edu 4313804Ssaidi@eecs.umich.edu 4323804Ssaidi@eecs.umich.eduFault 4333804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4343804Ssaidi@eecs.umich.edu{ 4353804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 4363804Ssaidi@eecs.umich.edu uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 4373804Ssaidi@eecs.umich.edu uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 4383804Ssaidi@eecs.umich.edu bool lsuDm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 3 & 0x1; 4393804Ssaidi@eecs.umich.edu uint64_t tl = tc->readMiscReg(MISCREG_TL); 4403804Ssaidi@eecs.umich.edu uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 4413804Ssaidi@eecs.umich.edu bool hpriv = hpstate >> 2 & 0x1; 4423804Ssaidi@eecs.umich.edu bool red = hpstate >> 5 >> 0x1; 4433804Ssaidi@eecs.umich.edu bool addr_mask = pstate >> 3 & 0x1; 4443804Ssaidi@eecs.umich.edu bool priv = pstate >> 2 & 0x1; 4453804Ssaidi@eecs.umich.edu bool implicit = false; 4463804Ssaidi@eecs.umich.edu bool real = false; 4473804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4483811Ssaidi@eecs.umich.edu Addr size = req->getSize(); 4493832Ssaidi@eecs.umich.edu ContextType ct = Primary; 4503832Ssaidi@eecs.umich.edu int context = 0; 4513804Ssaidi@eecs.umich.edu ASI asi; 4523804Ssaidi@eecs.umich.edu 4533804Ssaidi@eecs.umich.edu TlbEntry *e; 4543804Ssaidi@eecs.umich.edu 4553811Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 4563811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 4573811Ssaidi@eecs.umich.edu vaddr, size, asi); 4583825Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n", 4593825Ssaidi@eecs.umich.edu pstate, hpstate, lsuDm, part_id); 4603804Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 4613804Ssaidi@eecs.umich.edu implicit = true; 4623804Ssaidi@eecs.umich.edu 4633804Ssaidi@eecs.umich.edu if (implicit) { 4643804Ssaidi@eecs.umich.edu if (tl > 0) { 4653804Ssaidi@eecs.umich.edu asi = ASI_N; 4663804Ssaidi@eecs.umich.edu ct = Nucleus; 4673804Ssaidi@eecs.umich.edu context = 0; 4683804Ssaidi@eecs.umich.edu } else { 4693804Ssaidi@eecs.umich.edu asi = ASI_P; 4703804Ssaidi@eecs.umich.edu ct = Primary; 4713804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 4723804Ssaidi@eecs.umich.edu } 4733804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 4743823Ssaidi@eecs.umich.edu if (tl > 0 || AsiIsNucleus(asi)) { 4753804Ssaidi@eecs.umich.edu ct = Nucleus; 4763804Ssaidi@eecs.umich.edu context = 0; 4773804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 4783804Ssaidi@eecs.umich.edu ct = Secondary; 4793804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 4803804Ssaidi@eecs.umich.edu } else { 4813804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 4823804Ssaidi@eecs.umich.edu ct = Primary; //??? 4833804Ssaidi@eecs.umich.edu } 4843804Ssaidi@eecs.umich.edu 4853804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 4863804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 4873804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 4883804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4893804Ssaidi@eecs.umich.edu return new PrivilegedAction; 4903804Ssaidi@eecs.umich.edu } 4913804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 4923804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4933804Ssaidi@eecs.umich.edu return new DataAccessException; 4943804Ssaidi@eecs.umich.edu } 4953804Ssaidi@eecs.umich.edu 4963826Ssaidi@eecs.umich.edu } else if (hpriv) { 4973826Ssaidi@eecs.umich.edu if (asi == ASI_P) { 4983826Ssaidi@eecs.umich.edu ct = Primary; 4993826Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 5003826Ssaidi@eecs.umich.edu goto continueDtbFlow; 5013826Ssaidi@eecs.umich.edu } 5023804Ssaidi@eecs.umich.edu } 5033804Ssaidi@eecs.umich.edu 5043804Ssaidi@eecs.umich.edu if (!implicit) { 5053804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 5063804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 5073804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 5083804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 5093804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 5103804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 5113832Ssaidi@eecs.umich.edu if (write && asi == ASI_LDTX_P) 5123832Ssaidi@eecs.umich.edu // block init store (like write hint64) 5133832Ssaidi@eecs.umich.edu goto continueDtbFlow; 5143804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 5153804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 5163804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 5173804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 5183824Ssaidi@eecs.umich.edu if (AsiIsInterrupt(asi)) 5193824Ssaidi@eecs.umich.edu panic("Interrupt ASIs not supported\n"); 5203823Ssaidi@eecs.umich.edu 5213804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 5223804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 5233804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 5243804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 5253824Ssaidi@eecs.umich.edu if (AsiIsQueue(asi)) 5263824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 5273825Ssaidi@eecs.umich.edu if (AsiIsSparcError(asi)) 5283825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 5293823Ssaidi@eecs.umich.edu 5303823Ssaidi@eecs.umich.edu if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 5313823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 5323804Ssaidi@eecs.umich.edu } 5333804Ssaidi@eecs.umich.edu 5343826Ssaidi@eecs.umich.educontinueDtbFlow: 5353826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 5363826Ssaidi@eecs.umich.edu if (vaddr & size-1) { 5373826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 5383826Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 5393826Ssaidi@eecs.umich.edu } 5403826Ssaidi@eecs.umich.edu 5413826Ssaidi@eecs.umich.edu if (addr_mask) 5423826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 5433826Ssaidi@eecs.umich.edu 5443826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 5453826Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 5463826Ssaidi@eecs.umich.edu return new DataAccessException; 5473826Ssaidi@eecs.umich.edu } 5483826Ssaidi@eecs.umich.edu 5493826Ssaidi@eecs.umich.edu 5503804Ssaidi@eecs.umich.edu if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { 5513804Ssaidi@eecs.umich.edu real = true; 5523804Ssaidi@eecs.umich.edu context = 0; 5533804Ssaidi@eecs.umich.edu }; 5543804Ssaidi@eecs.umich.edu 5553804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 5563804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5573804Ssaidi@eecs.umich.edu return NoFault; 5583804Ssaidi@eecs.umich.edu } 5593804Ssaidi@eecs.umich.edu 5603804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, real, context); 5613804Ssaidi@eecs.umich.edu 5623804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5633804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 5643804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 5653811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 5663804Ssaidi@eecs.umich.edu if (real) 5673804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 5683804Ssaidi@eecs.umich.edu else 5693804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 5703804Ssaidi@eecs.umich.edu 5713804Ssaidi@eecs.umich.edu } 5723804Ssaidi@eecs.umich.edu 5733804Ssaidi@eecs.umich.edu 5743804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 5753804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 5763804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 5773804Ssaidi@eecs.umich.edu } 5783804Ssaidi@eecs.umich.edu 5793804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 5803804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 5813804Ssaidi@eecs.umich.edu return new DataAccessException; 5823804Ssaidi@eecs.umich.edu } 5833804Ssaidi@eecs.umich.edu 5843804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 5853804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 5863804Ssaidi@eecs.umich.edu 5873804Ssaidi@eecs.umich.edu 5883804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5893804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 5903804Ssaidi@eecs.umich.edu return new DataAccessException; 5913804Ssaidi@eecs.umich.edu } 5923804Ssaidi@eecs.umich.edu 5933826Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 5943826Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()-1); 5953826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); 5963804Ssaidi@eecs.umich.edu return NoFault; 5973806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 5983804Ssaidi@eecs.umich.edu 5993806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 6003806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 6013806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6023806Ssaidi@eecs.umich.edu return new DataAccessException; 6033806Ssaidi@eecs.umich.edu } 6043824Ssaidi@eecs.umich.edu goto regAccessOk; 6053824Ssaidi@eecs.umich.edu 6063824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 6073824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 6083824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6093824Ssaidi@eecs.umich.edu return new PrivilegedAction; 6103824Ssaidi@eecs.umich.edu } 6113824Ssaidi@eecs.umich.edu if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 6123824Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6133824Ssaidi@eecs.umich.edu return new DataAccessException; 6143824Ssaidi@eecs.umich.edu } 6153824Ssaidi@eecs.umich.edu goto regAccessOk; 6163824Ssaidi@eecs.umich.edu 6173825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 6183825Ssaidi@eecs.umich.edu if (!hpriv) { 6193825Ssaidi@eecs.umich.edu if (priv) { 6203825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6213825Ssaidi@eecs.umich.edu return new DataAccessException; 6223825Ssaidi@eecs.umich.edu } else { 6233825Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 6243825Ssaidi@eecs.umich.edu return new PrivilegedAction; 6253825Ssaidi@eecs.umich.edu } 6263825Ssaidi@eecs.umich.edu } 6273825Ssaidi@eecs.umich.edu goto regAccessOk; 6283825Ssaidi@eecs.umich.edu 6293825Ssaidi@eecs.umich.edu 6303824Ssaidi@eecs.umich.eduregAccessOk: 6313804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 6323811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 6333806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 6343806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 6353806Ssaidi@eecs.umich.edu return NoFault; 6363804Ssaidi@eecs.umich.edu}; 6373804Ssaidi@eecs.umich.edu 6383806Ssaidi@eecs.umich.eduTick 6393806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 6403806Ssaidi@eecs.umich.edu{ 6413823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 6423823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 6433823Ssaidi@eecs.umich.edu 6443823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 6453823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 6463823Ssaidi@eecs.umich.edu 6473823Ssaidi@eecs.umich.edu switch (asi) { 6483823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 6493823Ssaidi@eecs.umich.edu assert(va == 0); 6503823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 6513823Ssaidi@eecs.umich.edu break; 6523823Ssaidi@eecs.umich.edu case ASI_MMU: 6533823Ssaidi@eecs.umich.edu switch (va) { 6543823Ssaidi@eecs.umich.edu case 0x8: 6553823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 6563823Ssaidi@eecs.umich.edu break; 6573823Ssaidi@eecs.umich.edu case 0x10: 6583823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 6593823Ssaidi@eecs.umich.edu break; 6603823Ssaidi@eecs.umich.edu default: 6613823Ssaidi@eecs.umich.edu goto doMmuReadError; 6623823Ssaidi@eecs.umich.edu } 6633823Ssaidi@eecs.umich.edu break; 6643824Ssaidi@eecs.umich.edu case ASI_QUEUE: 6653824Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 6663824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 6673824Ssaidi@eecs.umich.edu break; 6683823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 6693823Ssaidi@eecs.umich.edu assert(va == 0); 6703823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 6713823Ssaidi@eecs.umich.edu break; 6723823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 6733823Ssaidi@eecs.umich.edu assert(va == 0); 6743823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 6753823Ssaidi@eecs.umich.edu break; 6763823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 6773823Ssaidi@eecs.umich.edu assert(va == 0); 6783823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 6793823Ssaidi@eecs.umich.edu break; 6803823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 6813823Ssaidi@eecs.umich.edu assert(va == 0); 6823823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 6833823Ssaidi@eecs.umich.edu break; 6843823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 6853823Ssaidi@eecs.umich.edu assert(va == 0); 6863823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 6873823Ssaidi@eecs.umich.edu break; 6883823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 6893823Ssaidi@eecs.umich.edu assert(va == 0); 6903823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 6913823Ssaidi@eecs.umich.edu break; 6923823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 6933823Ssaidi@eecs.umich.edu assert(va == 0); 6943823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 6953823Ssaidi@eecs.umich.edu break; 6963823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 6973823Ssaidi@eecs.umich.edu assert(va == 0); 6983823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 6993823Ssaidi@eecs.umich.edu break; 7003823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 7013823Ssaidi@eecs.umich.edu assert(va == 0); 7023823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 7033823Ssaidi@eecs.umich.edu break; 7043823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 7053823Ssaidi@eecs.umich.edu assert(va == 0); 7063823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 7073823Ssaidi@eecs.umich.edu break; 7083823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 7093823Ssaidi@eecs.umich.edu assert(va == 0); 7103823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 7113823Ssaidi@eecs.umich.edu break; 7123823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 7133823Ssaidi@eecs.umich.edu assert(va == 0); 7143823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 7153823Ssaidi@eecs.umich.edu break; 7163826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 7173826Ssaidi@eecs.umich.edu warn("returning 0 for SPARC ERROR regsiter read\n"); 7183826Ssaidi@eecs.umich.edu pkt->set(0); 7193826Ssaidi@eecs.umich.edu break; 7203823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 7213823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 7223823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 7233823Ssaidi@eecs.umich.edu break; 7243826Ssaidi@eecs.umich.edu case ASI_IMMU: 7253826Ssaidi@eecs.umich.edu switch (va) { 7263826Ssaidi@eecs.umich.edu case 0x30: 7273826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 7283826Ssaidi@eecs.umich.edu break; 7293826Ssaidi@eecs.umich.edu default: 7303826Ssaidi@eecs.umich.edu goto doMmuReadError; 7313826Ssaidi@eecs.umich.edu } 7323826Ssaidi@eecs.umich.edu break; 7333823Ssaidi@eecs.umich.edu case ASI_DMMU: 7343823Ssaidi@eecs.umich.edu switch (va) { 7353826Ssaidi@eecs.umich.edu case 0x30: 7363826Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 7373826Ssaidi@eecs.umich.edu break; 7383823Ssaidi@eecs.umich.edu case 0x80: 7393823Ssaidi@eecs.umich.edu pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 7403823Ssaidi@eecs.umich.edu break; 7413823Ssaidi@eecs.umich.edu default: 7423823Ssaidi@eecs.umich.edu goto doMmuReadError; 7433823Ssaidi@eecs.umich.edu } 7443823Ssaidi@eecs.umich.edu break; 7453823Ssaidi@eecs.umich.edu default: 7463823Ssaidi@eecs.umich.edudoMmuReadError: 7473823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 7483823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 7493823Ssaidi@eecs.umich.edu } 7503823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 7513823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 7523806Ssaidi@eecs.umich.edu} 7533806Ssaidi@eecs.umich.edu 7543806Ssaidi@eecs.umich.eduTick 7553806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 7563806Ssaidi@eecs.umich.edu{ 7573823Ssaidi@eecs.umich.edu uint64_t data = gtoh(pkt->get<uint64_t>()); 7583823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 7593823Ssaidi@eecs.umich.edu ASI asi = (ASI)pkt->req->getAsi(); 7603823Ssaidi@eecs.umich.edu 7613826Ssaidi@eecs.umich.edu Addr ta_insert; 7623826Ssaidi@eecs.umich.edu Addr va_insert; 7633826Ssaidi@eecs.umich.edu Addr ct_insert; 7643826Ssaidi@eecs.umich.edu int part_insert; 7653826Ssaidi@eecs.umich.edu int entry_insert = -1; 7663826Ssaidi@eecs.umich.edu bool real_insert; 7673826Ssaidi@eecs.umich.edu PageTableEntry pte; 7683826Ssaidi@eecs.umich.edu 7693825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 7703823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 7713823Ssaidi@eecs.umich.edu 7723823Ssaidi@eecs.umich.edu switch (asi) { 7733823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 7743823Ssaidi@eecs.umich.edu assert(va == 0); 7753823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 7763823Ssaidi@eecs.umich.edu break; 7773823Ssaidi@eecs.umich.edu case ASI_MMU: 7783823Ssaidi@eecs.umich.edu switch (va) { 7793823Ssaidi@eecs.umich.edu case 0x8: 7803823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 7813823Ssaidi@eecs.umich.edu break; 7823823Ssaidi@eecs.umich.edu case 0x10: 7833823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 7843823Ssaidi@eecs.umich.edu break; 7853823Ssaidi@eecs.umich.edu default: 7863823Ssaidi@eecs.umich.edu goto doMmuWriteError; 7873823Ssaidi@eecs.umich.edu } 7883823Ssaidi@eecs.umich.edu break; 7893824Ssaidi@eecs.umich.edu case ASI_QUEUE: 7903825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 7913824Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 7923824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 7933824Ssaidi@eecs.umich.edu break; 7943823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 7953823Ssaidi@eecs.umich.edu assert(va == 0); 7963823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 7973823Ssaidi@eecs.umich.edu break; 7983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 7993823Ssaidi@eecs.umich.edu assert(va == 0); 8003823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 8013823Ssaidi@eecs.umich.edu break; 8023823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8033823Ssaidi@eecs.umich.edu assert(va == 0); 8043823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 8053823Ssaidi@eecs.umich.edu break; 8063823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 8073823Ssaidi@eecs.umich.edu assert(va == 0); 8083823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 8093823Ssaidi@eecs.umich.edu break; 8103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 8113823Ssaidi@eecs.umich.edu assert(va == 0); 8123823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 8133823Ssaidi@eecs.umich.edu break; 8143823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 8153823Ssaidi@eecs.umich.edu assert(va == 0); 8163823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 8173823Ssaidi@eecs.umich.edu break; 8183823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 8193823Ssaidi@eecs.umich.edu assert(va == 0); 8203823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 8213823Ssaidi@eecs.umich.edu break; 8223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 8233823Ssaidi@eecs.umich.edu assert(va == 0); 8243823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 8253823Ssaidi@eecs.umich.edu break; 8263823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 8273823Ssaidi@eecs.umich.edu assert(va == 0); 8283823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 8293823Ssaidi@eecs.umich.edu break; 8303823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 8313823Ssaidi@eecs.umich.edu assert(va == 0); 8323823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 8333823Ssaidi@eecs.umich.edu break; 8343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 8353823Ssaidi@eecs.umich.edu assert(va == 0); 8363823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 8373823Ssaidi@eecs.umich.edu break; 8383823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 8393823Ssaidi@eecs.umich.edu assert(va == 0); 8403823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 8413823Ssaidi@eecs.umich.edu break; 8423825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 8433825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 8443825Ssaidi@eecs.umich.edu warn("Ignoring write to SPARC ERROR regsiter\n"); 8453825Ssaidi@eecs.umich.edu break; 8463823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 8473823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 8483823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 8493823Ssaidi@eecs.umich.edu break; 8503826Ssaidi@eecs.umich.edu case ASI_IMMU: 8513826Ssaidi@eecs.umich.edu switch (va) { 8523826Ssaidi@eecs.umich.edu case 0x30: 8533826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 8543826Ssaidi@eecs.umich.edu break; 8553826Ssaidi@eecs.umich.edu default: 8563826Ssaidi@eecs.umich.edu goto doMmuWriteError; 8573826Ssaidi@eecs.umich.edu } 8583826Ssaidi@eecs.umich.edu break; 8593826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 8603826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 8613826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 8623826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 8633826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 8643826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 8653826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 8663826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 8673826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 8683826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 8693826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 8703826Ssaidi@eecs.umich.edu tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 8713826Ssaidi@eecs.umich.edu pte, entry_insert); 8723826Ssaidi@eecs.umich.edu break; 8733826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 8743826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 8753826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 8763826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 8773826Ssaidi@eecs.umich.edu ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 8783826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 8793826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 8803826Ssaidi@eecs.umich.edu part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 8813826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 8823826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 8833826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 8843826Ssaidi@eecs.umich.edu insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 8853826Ssaidi@eecs.umich.edu break; 8863823Ssaidi@eecs.umich.edu case ASI_DMMU: 8873823Ssaidi@eecs.umich.edu switch (va) { 8883826Ssaidi@eecs.umich.edu case 0x30: 8893826Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 8903826Ssaidi@eecs.umich.edu break; 8913823Ssaidi@eecs.umich.edu case 0x80: 8923823Ssaidi@eecs.umich.edu tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 8933823Ssaidi@eecs.umich.edu break; 8943823Ssaidi@eecs.umich.edu default: 8953823Ssaidi@eecs.umich.edu goto doMmuWriteError; 8963823Ssaidi@eecs.umich.edu } 8973823Ssaidi@eecs.umich.edu break; 8983823Ssaidi@eecs.umich.edu default: 8993823Ssaidi@eecs.umich.edudoMmuWriteError: 9003823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 9013823Ssaidi@eecs.umich.edu (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 9023823Ssaidi@eecs.umich.edu } 9033823Ssaidi@eecs.umich.edu pkt->result = Packet::Success; 9043823Ssaidi@eecs.umich.edu return tc->getCpuPtr()->cycles(1); 9053806Ssaidi@eecs.umich.edu} 9063806Ssaidi@eecs.umich.edu 9073804Ssaidi@eecs.umich.eduvoid 9083804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 9093804Ssaidi@eecs.umich.edu{ 9103804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 9113804Ssaidi@eecs.umich.edu} 9123804Ssaidi@eecs.umich.edu 9133804Ssaidi@eecs.umich.eduvoid 9143804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 9153804Ssaidi@eecs.umich.edu{ 9163804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 9173804Ssaidi@eecs.umich.edu} 9183804Ssaidi@eecs.umich.edu 9193804Ssaidi@eecs.umich.edu 9203804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 9213804Ssaidi@eecs.umich.edu 9223804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 9233804Ssaidi@eecs.umich.edu 9243804Ssaidi@eecs.umich.edu Param<int> size; 9253804Ssaidi@eecs.umich.edu 9263804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 9273804Ssaidi@eecs.umich.edu 9283804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 9293804Ssaidi@eecs.umich.edu 9303804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 9313804Ssaidi@eecs.umich.edu 9323804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 9333804Ssaidi@eecs.umich.edu 9343804Ssaidi@eecs.umich.edu 9353804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 9363804Ssaidi@eecs.umich.edu{ 9373804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 9383804Ssaidi@eecs.umich.edu} 9393804Ssaidi@eecs.umich.edu 9403804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 9413804Ssaidi@eecs.umich.edu 9423804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 9433804Ssaidi@eecs.umich.edu 9443804Ssaidi@eecs.umich.edu Param<int> size; 9453804Ssaidi@eecs.umich.edu 9463804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 9473804Ssaidi@eecs.umich.edu 9483804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 9493804Ssaidi@eecs.umich.edu 9503804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 9513804Ssaidi@eecs.umich.edu 9523804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 9533804Ssaidi@eecs.umich.edu 9543804Ssaidi@eecs.umich.edu 9553804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 9563804Ssaidi@eecs.umich.edu{ 9573804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 9583804Ssaidi@eecs.umich.edu} 9593804Ssaidi@eecs.umich.edu 9603804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 9613804Ssaidi@eecs.umich.edu} 962