tlb.cc revision 3806
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 313804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 323569Sgblack@eecs.umich.edu#include "arch/sparc/tlb.hh" 333569Sgblack@eecs.umich.edu#include "sim/builder.hh" 343804Ssaidi@eecs.umich.edu#include "arch/sparc/miscregfile.hh" 353804Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 363569Sgblack@eecs.umich.edu 373804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 383804Ssaidi@eecs.umich.edu * */ 393569Sgblack@eecs.umich.edunamespace SparcISA 403569Sgblack@eecs.umich.edu{ 413569Sgblack@eecs.umich.edu 423804Ssaidi@eecs.umich.eduTLB::TLB(const std::string &name, int s) 433804Ssaidi@eecs.umich.edu : SimObject(name), size(s) 443804Ssaidi@eecs.umich.edu{ 453804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 463804Ssaidi@eecs.umich.edu if (size > 64) 473804Ssaidi@eecs.umich.edu fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 483569Sgblack@eecs.umich.edu 493804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 503804Ssaidi@eecs.umich.edu memset(tlb, 0, sizeof(TlbEntry) * size); 513804Ssaidi@eecs.umich.edu} 523569Sgblack@eecs.umich.edu 533804Ssaidi@eecs.umich.eduvoid 543804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 553804Ssaidi@eecs.umich.edu{ 563804Ssaidi@eecs.umich.edu MapIter i; 573804Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end();) { 583804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 593804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 603804Ssaidi@eecs.umich.edu t->used = false; 613804Ssaidi@eecs.umich.edu usedEntries--; 623804Ssaidi@eecs.umich.edu } 633804Ssaidi@eecs.umich.edu } 643804Ssaidi@eecs.umich.edu} 653569Sgblack@eecs.umich.edu 663569Sgblack@eecs.umich.edu 673804Ssaidi@eecs.umich.eduvoid 683804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 693804Ssaidi@eecs.umich.edu const PageTableEntry& PTE) 703804Ssaidi@eecs.umich.edu{ 713569Sgblack@eecs.umich.edu 723569Sgblack@eecs.umich.edu 733804Ssaidi@eecs.umich.edu MapIter i; 743804Ssaidi@eecs.umich.edu TlbEntry *new_entry; 753804Ssaidi@eecs.umich.edu int x = -1; 763804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 773804Ssaidi@eecs.umich.edu if (!tlb[x].valid || !tlb[x].used) { 783804Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 793804Ssaidi@eecs.umich.edu break; 803804Ssaidi@eecs.umich.edu } 813569Sgblack@eecs.umich.edu } 823569Sgblack@eecs.umich.edu 833804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 843804Ssaidi@eecs.umich.edu if (x == -1) 853804Ssaidi@eecs.umich.edu x = size - 1; 863569Sgblack@eecs.umich.edu 873804Ssaidi@eecs.umich.edu assert(PTE.valid()); 883804Ssaidi@eecs.umich.edu new_entry->range.va = va; 893804Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size(); 903804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 913804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 923804Ssaidi@eecs.umich.edu new_entry->range.real = real; 933804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 943804Ssaidi@eecs.umich.edu new_entry->used = true;; 953804Ssaidi@eecs.umich.edu new_entry->valid = true; 963804Ssaidi@eecs.umich.edu usedEntries++; 973569Sgblack@eecs.umich.edu 983569Sgblack@eecs.umich.edu 993804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1003804Ssaidi@eecs.umich.edu i = lookupTable.find(new_entry->range); 1013804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1023804Ssaidi@eecs.umich.edu i->second->valid = false; 1033804Ssaidi@eecs.umich.edu if (i->second->used) { 1043804Ssaidi@eecs.umich.edu i->second->used = false; 1053804Ssaidi@eecs.umich.edu usedEntries--; 1063804Ssaidi@eecs.umich.edu } 1073804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1083569Sgblack@eecs.umich.edu } 1093569Sgblack@eecs.umich.edu 1103804Ssaidi@eecs.umich.edu lookupTable.insert(new_entry->range, new_entry);; 1113804Ssaidi@eecs.umich.edu 1123804Ssaidi@eecs.umich.edu // If all entries have there used bit set, clear it on them all, but the 1133804Ssaidi@eecs.umich.edu // one we just inserted 1143804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1153804Ssaidi@eecs.umich.edu clearUsedBits(); 1163804Ssaidi@eecs.umich.edu new_entry->used = true; 1173804Ssaidi@eecs.umich.edu usedEntries++; 1183804Ssaidi@eecs.umich.edu } 1193804Ssaidi@eecs.umich.edu 1203569Sgblack@eecs.umich.edu} 1213804Ssaidi@eecs.umich.edu 1223804Ssaidi@eecs.umich.edu 1233804Ssaidi@eecs.umich.eduTlbEntry* 1243804Ssaidi@eecs.umich.eduTLB::lookup(Addr va, int partition_id, bool real, int context_id) 1253804Ssaidi@eecs.umich.edu{ 1263804Ssaidi@eecs.umich.edu MapIter i; 1273804Ssaidi@eecs.umich.edu TlbRange tr; 1283804Ssaidi@eecs.umich.edu TlbEntry *t; 1293804Ssaidi@eecs.umich.edu 1303804Ssaidi@eecs.umich.edu // Assemble full address structure 1313804Ssaidi@eecs.umich.edu tr.va = va; 1323804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1333804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1343804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1353804Ssaidi@eecs.umich.edu tr.real = real; 1363804Ssaidi@eecs.umich.edu 1373804Ssaidi@eecs.umich.edu // Try to find the entry 1383804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1393804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 1403804Ssaidi@eecs.umich.edu return NULL; 1413804Ssaidi@eecs.umich.edu } 1423804Ssaidi@eecs.umich.edu 1433804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 1443804Ssaidi@eecs.umich.edu t = i->second; 1453804Ssaidi@eecs.umich.edu if (!t->used) { 1463804Ssaidi@eecs.umich.edu t->used = true; 1473804Ssaidi@eecs.umich.edu usedEntries++; 1483804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1493804Ssaidi@eecs.umich.edu clearUsedBits(); 1503804Ssaidi@eecs.umich.edu t->used = true; 1513804Ssaidi@eecs.umich.edu usedEntries++; 1523804Ssaidi@eecs.umich.edu } 1533804Ssaidi@eecs.umich.edu } 1543804Ssaidi@eecs.umich.edu 1553804Ssaidi@eecs.umich.edu return t; 1563804Ssaidi@eecs.umich.edu} 1573804Ssaidi@eecs.umich.edu 1583804Ssaidi@eecs.umich.edu 1593804Ssaidi@eecs.umich.eduvoid 1603804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 1613804Ssaidi@eecs.umich.edu{ 1623804Ssaidi@eecs.umich.edu TlbRange tr; 1633804Ssaidi@eecs.umich.edu MapIter i; 1643804Ssaidi@eecs.umich.edu 1653804Ssaidi@eecs.umich.edu // Assemble full address structure 1663804Ssaidi@eecs.umich.edu tr.va = va; 1673804Ssaidi@eecs.umich.edu tr.size = va + MachineBytes; 1683804Ssaidi@eecs.umich.edu tr.contextId = context_id; 1693804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1703804Ssaidi@eecs.umich.edu tr.real = real; 1713804Ssaidi@eecs.umich.edu 1723804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1733804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 1743804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 1753804Ssaidi@eecs.umich.edu i->second->valid = false; 1763804Ssaidi@eecs.umich.edu if (i->second->used) { 1773804Ssaidi@eecs.umich.edu i->second->used = false; 1783804Ssaidi@eecs.umich.edu usedEntries--; 1793804Ssaidi@eecs.umich.edu } 1803804Ssaidi@eecs.umich.edu lookupTable.erase(i); 1813804Ssaidi@eecs.umich.edu } 1823804Ssaidi@eecs.umich.edu} 1833804Ssaidi@eecs.umich.edu 1843804Ssaidi@eecs.umich.eduvoid 1853804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 1863804Ssaidi@eecs.umich.edu{ 1873804Ssaidi@eecs.umich.edu int x; 1883804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1893804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 1903804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 1913804Ssaidi@eecs.umich.edu tlb[x].valid = false; 1923804Ssaidi@eecs.umich.edu if (tlb[x].used) { 1933804Ssaidi@eecs.umich.edu tlb[x].used = false; 1943804Ssaidi@eecs.umich.edu usedEntries--; 1953804Ssaidi@eecs.umich.edu } 1963804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1973804Ssaidi@eecs.umich.edu } 1983804Ssaidi@eecs.umich.edu } 1993804Ssaidi@eecs.umich.edu} 2003804Ssaidi@eecs.umich.edu 2013804Ssaidi@eecs.umich.eduvoid 2023804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 2033804Ssaidi@eecs.umich.edu{ 2043804Ssaidi@eecs.umich.edu int x; 2053804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2063804Ssaidi@eecs.umich.edu if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 2073804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2083804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2093804Ssaidi@eecs.umich.edu tlb[x].used = false; 2103804Ssaidi@eecs.umich.edu usedEntries--; 2113804Ssaidi@eecs.umich.edu } 2123804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 2133804Ssaidi@eecs.umich.edu } 2143804Ssaidi@eecs.umich.edu } 2153804Ssaidi@eecs.umich.edu} 2163804Ssaidi@eecs.umich.edu 2173804Ssaidi@eecs.umich.eduvoid 2183804Ssaidi@eecs.umich.eduTLB::invalidateAll() 2193804Ssaidi@eecs.umich.edu{ 2203804Ssaidi@eecs.umich.edu int x; 2213804Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 2223804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2233804Ssaidi@eecs.umich.edu } 2243804Ssaidi@eecs.umich.edu usedEntries = 0; 2253804Ssaidi@eecs.umich.edu} 2263804Ssaidi@eecs.umich.edu 2273804Ssaidi@eecs.umich.eduuint64_t 2283804Ssaidi@eecs.umich.eduTLB::TteRead(int entry) { 2293804Ssaidi@eecs.umich.edu assert(entry < size); 2303804Ssaidi@eecs.umich.edu return tlb[entry].pte(); 2313804Ssaidi@eecs.umich.edu} 2323804Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.eduuint64_t 2343804Ssaidi@eecs.umich.eduTLB::TagRead(int entry) { 2353804Ssaidi@eecs.umich.edu assert(entry < size); 2363804Ssaidi@eecs.umich.edu uint64_t tag; 2373804Ssaidi@eecs.umich.edu 2383804Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId | tlb[entry].range.va | 2393804Ssaidi@eecs.umich.edu (uint64_t)tlb[entry].range.partitionId << 61; 2403804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 2413804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 2423804Ssaidi@eecs.umich.edu return tag; 2433804Ssaidi@eecs.umich.edu} 2443804Ssaidi@eecs.umich.edu 2453804Ssaidi@eecs.umich.edubool 2463804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 2473804Ssaidi@eecs.umich.edu{ 2483804Ssaidi@eecs.umich.edu if (am) 2493804Ssaidi@eecs.umich.edu return true; 2503804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 2513804Ssaidi@eecs.umich.edu return false; 2523804Ssaidi@eecs.umich.edu return true; 2533804Ssaidi@eecs.umich.edu} 2543804Ssaidi@eecs.umich.edu 2553804Ssaidi@eecs.umich.eduvoid 2563804Ssaidi@eecs.umich.eduTLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 2573804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2583804Ssaidi@eecs.umich.edu{ 2593804Ssaidi@eecs.umich.edu uint64_t sfsr; 2603804Ssaidi@eecs.umich.edu sfsr = tc->readMiscReg(reg); 2613804Ssaidi@eecs.umich.edu 2623804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 2633804Ssaidi@eecs.umich.edu sfsr = 0x3; 2643804Ssaidi@eecs.umich.edu else 2653804Ssaidi@eecs.umich.edu sfsr = 1; 2663804Ssaidi@eecs.umich.edu 2673804Ssaidi@eecs.umich.edu if (write) 2683804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 2693804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 2703804Ssaidi@eecs.umich.edu if (se) 2713804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 2723804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 2733804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 2743804Ssaidi@eecs.umich.edu tc->setMiscReg(reg, sfsr); 2753804Ssaidi@eecs.umich.edu} 2763804Ssaidi@eecs.umich.edu 2773804Ssaidi@eecs.umich.edu 2783804Ssaidi@eecs.umich.eduvoid 2793804Ssaidi@eecs.umich.eduITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 2803804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2813804Ssaidi@eecs.umich.edu{ 2823804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 2833804Ssaidi@eecs.umich.edu} 2843804Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.eduvoid 2863804Ssaidi@eecs.umich.eduDTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 2873804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 2883804Ssaidi@eecs.umich.edu{ 2893804Ssaidi@eecs.umich.edu TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 2903804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); 2913804Ssaidi@eecs.umich.edu} 2923804Ssaidi@eecs.umich.edu 2933804Ssaidi@eecs.umich.edu 2943804Ssaidi@eecs.umich.eduFault 2953804Ssaidi@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 2963804Ssaidi@eecs.umich.edu{ 2973804Ssaidi@eecs.umich.edu uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 2983804Ssaidi@eecs.umich.edu uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 2993804Ssaidi@eecs.umich.edu bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1; 3003804Ssaidi@eecs.umich.edu uint64_t tl = tc->readMiscReg(MISCREG_TL); 3013804Ssaidi@eecs.umich.edu uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 3023804Ssaidi@eecs.umich.edu bool addr_mask = pstate >> 3 & 0x1; 3033804Ssaidi@eecs.umich.edu bool priv = pstate >> 2 & 0x1; 3043804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3053804Ssaidi@eecs.umich.edu int context; 3063804Ssaidi@eecs.umich.edu ContextType ct; 3073804Ssaidi@eecs.umich.edu int asi; 3083804Ssaidi@eecs.umich.edu bool real = false; 3093804Ssaidi@eecs.umich.edu TlbEntry *e; 3103804Ssaidi@eecs.umich.edu 3113804Ssaidi@eecs.umich.edu assert(req->getAsi() == ASI_IMPLICIT); 3123804Ssaidi@eecs.umich.edu 3133804Ssaidi@eecs.umich.edu if (tl > 0) { 3143804Ssaidi@eecs.umich.edu asi = ASI_N; 3153804Ssaidi@eecs.umich.edu ct = Nucleus; 3163804Ssaidi@eecs.umich.edu context = 0; 3173804Ssaidi@eecs.umich.edu } else { 3183804Ssaidi@eecs.umich.edu asi = ASI_P; 3193804Ssaidi@eecs.umich.edu ct = Primary; 3203804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 3213804Ssaidi@eecs.umich.edu } 3223804Ssaidi@eecs.umich.edu 3233804Ssaidi@eecs.umich.edu if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) { 3243804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 3253804Ssaidi@eecs.umich.edu return NoFault; 3263804Ssaidi@eecs.umich.edu } 3273804Ssaidi@eecs.umich.edu 3283804Ssaidi@eecs.umich.edu // If the asi is unaligned trap 3293804Ssaidi@eecs.umich.edu if (vaddr & 0x7) { 3303804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, OtherFault, asi); 3313804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 3323804Ssaidi@eecs.umich.edu } 3333804Ssaidi@eecs.umich.edu 3343804Ssaidi@eecs.umich.edu if (addr_mask) 3353804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 3363804Ssaidi@eecs.umich.edu 3373804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 3383804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 3393804Ssaidi@eecs.umich.edu return new InstructionAccessException; 3403804Ssaidi@eecs.umich.edu } 3413804Ssaidi@eecs.umich.edu 3423804Ssaidi@eecs.umich.edu if (lsuIm) { 3433804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, true); 3443804Ssaidi@eecs.umich.edu real = true; 3453804Ssaidi@eecs.umich.edu context = 0; 3463804Ssaidi@eecs.umich.edu } else { 3473804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 3483804Ssaidi@eecs.umich.edu } 3493804Ssaidi@eecs.umich.edu 3503804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 3513804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, 3523804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 3533804Ssaidi@eecs.umich.edu if (real) 3543804Ssaidi@eecs.umich.edu return new InstructionRealTranslationMiss; 3553804Ssaidi@eecs.umich.edu else 3563804Ssaidi@eecs.umich.edu return new FastInstructionAccessMMUMiss; 3573804Ssaidi@eecs.umich.edu } 3583804Ssaidi@eecs.umich.edu 3593804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 3603804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 3613804Ssaidi@eecs.umich.edu writeSfsr(tc, false, ct, false, PrivViolation, asi); 3623804Ssaidi@eecs.umich.edu return new InstructionAccessException; 3633804Ssaidi@eecs.umich.edu } 3643804Ssaidi@eecs.umich.edu 3653804Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~e->pte.size() | 3663804Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()); 3673804Ssaidi@eecs.umich.edu return NoFault; 3683804Ssaidi@eecs.umich.edu} 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edu 3713804Ssaidi@eecs.umich.edu 3723804Ssaidi@eecs.umich.eduFault 3733804Ssaidi@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 3743804Ssaidi@eecs.umich.edu{ 3753804Ssaidi@eecs.umich.edu /* @todo this could really use some profiling and fixing to make it faster! */ 3763804Ssaidi@eecs.umich.edu uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 3773804Ssaidi@eecs.umich.edu uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 3783804Ssaidi@eecs.umich.edu bool lsuDm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 3 & 0x1; 3793804Ssaidi@eecs.umich.edu uint64_t tl = tc->readMiscReg(MISCREG_TL); 3803804Ssaidi@eecs.umich.edu uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 3813804Ssaidi@eecs.umich.edu bool hpriv = hpstate >> 2 & 0x1; 3823804Ssaidi@eecs.umich.edu bool red = hpstate >> 5 >> 0x1; 3833804Ssaidi@eecs.umich.edu bool addr_mask = pstate >> 3 & 0x1; 3843804Ssaidi@eecs.umich.edu bool priv = pstate >> 2 & 0x1; 3853804Ssaidi@eecs.umich.edu bool implicit = false; 3863804Ssaidi@eecs.umich.edu bool real = false; 3873804Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 3883804Ssaidi@eecs.umich.edu ContextType ct; 3893804Ssaidi@eecs.umich.edu int context; 3903804Ssaidi@eecs.umich.edu ASI asi; 3913804Ssaidi@eecs.umich.edu 3923804Ssaidi@eecs.umich.edu TlbEntry *e; 3933804Ssaidi@eecs.umich.edu 3943804Ssaidi@eecs.umich.edu 3953804Ssaidi@eecs.umich.edu asi = (ASI)req->getAsi(); 3963804Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 3973804Ssaidi@eecs.umich.edu implicit = true; 3983804Ssaidi@eecs.umich.edu 3993804Ssaidi@eecs.umich.edu if (implicit) { 4003804Ssaidi@eecs.umich.edu if (tl > 0) { 4013804Ssaidi@eecs.umich.edu asi = ASI_N; 4023804Ssaidi@eecs.umich.edu ct = Nucleus; 4033804Ssaidi@eecs.umich.edu context = 0; 4043804Ssaidi@eecs.umich.edu } else { 4053804Ssaidi@eecs.umich.edu asi = ASI_P; 4063804Ssaidi@eecs.umich.edu ct = Primary; 4073804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 4083804Ssaidi@eecs.umich.edu } 4093804Ssaidi@eecs.umich.edu } else if (!hpriv && !red) { 4103804Ssaidi@eecs.umich.edu if (tl > 0) { 4113804Ssaidi@eecs.umich.edu ct = Nucleus; 4123804Ssaidi@eecs.umich.edu context = 0; 4133804Ssaidi@eecs.umich.edu } else if (AsiIsSecondary(asi)) { 4143804Ssaidi@eecs.umich.edu ct = Secondary; 4153804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 4163804Ssaidi@eecs.umich.edu } else { 4173804Ssaidi@eecs.umich.edu context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 4183804Ssaidi@eecs.umich.edu ct = Primary; //??? 4193804Ssaidi@eecs.umich.edu } 4203804Ssaidi@eecs.umich.edu 4213804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 4223804Ssaidi@eecs.umich.edu if (!priv && !AsiIsUnPriv(asi)) { 4233804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 4243804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4253804Ssaidi@eecs.umich.edu return new PrivilegedAction; 4263804Ssaidi@eecs.umich.edu } 4273804Ssaidi@eecs.umich.edu if (priv && AsiIsHPriv(asi)) { 4283804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 4293804Ssaidi@eecs.umich.edu return new DataAccessException; 4303804Ssaidi@eecs.umich.edu } 4313804Ssaidi@eecs.umich.edu 4323804Ssaidi@eecs.umich.edu } 4333804Ssaidi@eecs.umich.edu 4343804Ssaidi@eecs.umich.edu // If the asi is unaligned trap 4353804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi) && vaddr & 0x3f || vaddr & 0x7) { 4363804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 4373804Ssaidi@eecs.umich.edu return new MemAddressNotAligned; 4383804Ssaidi@eecs.umich.edu } 4393804Ssaidi@eecs.umich.edu 4403804Ssaidi@eecs.umich.edu if (addr_mask) 4413804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4423804Ssaidi@eecs.umich.edu 4433804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4443804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 4453804Ssaidi@eecs.umich.edu return new DataAccessException; 4463804Ssaidi@eecs.umich.edu } 4473804Ssaidi@eecs.umich.edu 4483804Ssaidi@eecs.umich.edu if (!implicit) { 4493804Ssaidi@eecs.umich.edu if (AsiIsLittle(asi)) 4503804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 4513804Ssaidi@eecs.umich.edu if (AsiIsBlock(asi)) 4523804Ssaidi@eecs.umich.edu panic("Block ASIs not supported\n"); 4533804Ssaidi@eecs.umich.edu if (AsiIsNoFault(asi)) 4543804Ssaidi@eecs.umich.edu panic("No Fault ASIs not supported\n"); 4553804Ssaidi@eecs.umich.edu if (AsiIsTwin(asi)) 4563804Ssaidi@eecs.umich.edu panic("Twin ASIs not supported\n"); 4573804Ssaidi@eecs.umich.edu if (AsiIsPartialStore(asi)) 4583804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 4593804Ssaidi@eecs.umich.edu if (AsiIsMmu(asi)) 4603804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 4613804Ssaidi@eecs.umich.edu 4623804Ssaidi@eecs.umich.edu if (AsiIsScratchPad(asi)) 4633804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 4643804Ssaidi@eecs.umich.edu } 4653804Ssaidi@eecs.umich.edu 4663804Ssaidi@eecs.umich.edu if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { 4673804Ssaidi@eecs.umich.edu real = true; 4683804Ssaidi@eecs.umich.edu context = 0; 4693804Ssaidi@eecs.umich.edu }; 4703804Ssaidi@eecs.umich.edu 4713804Ssaidi@eecs.umich.edu if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 4723804Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 4733804Ssaidi@eecs.umich.edu return NoFault; 4743804Ssaidi@eecs.umich.edu } 4753804Ssaidi@eecs.umich.edu 4763804Ssaidi@eecs.umich.edu e = lookup(req->getVaddr(), part_id, real, context); 4773804Ssaidi@eecs.umich.edu 4783804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 4793804Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 4803804Ssaidi@eecs.umich.edu vaddr & ~BytesInPageMask | context); 4813804Ssaidi@eecs.umich.edu if (real) 4823804Ssaidi@eecs.umich.edu return new DataRealTranslationMiss; 4833804Ssaidi@eecs.umich.edu else 4843804Ssaidi@eecs.umich.edu return new FastDataAccessMMUMiss; 4853804Ssaidi@eecs.umich.edu 4863804Ssaidi@eecs.umich.edu } 4873804Ssaidi@eecs.umich.edu 4883804Ssaidi@eecs.umich.edu 4893804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 4903804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 4913804Ssaidi@eecs.umich.edu return new FastDataAccessProtection; 4923804Ssaidi@eecs.umich.edu } 4933804Ssaidi@eecs.umich.edu 4943804Ssaidi@eecs.umich.edu if (e->pte.nofault() && !AsiIsNoFault(asi)) { 4953804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 4963804Ssaidi@eecs.umich.edu return new DataAccessException; 4973804Ssaidi@eecs.umich.edu } 4983804Ssaidi@eecs.umich.edu 4993804Ssaidi@eecs.umich.edu if (e->pte.sideffect()) 5003804Ssaidi@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 5013804Ssaidi@eecs.umich.edu 5023804Ssaidi@eecs.umich.edu 5033804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5043804Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 5053804Ssaidi@eecs.umich.edu return new DataAccessException; 5063804Ssaidi@eecs.umich.edu } 5073804Ssaidi@eecs.umich.edu 5083804Ssaidi@eecs.umich.edu req->setPaddr(e->pte.paddr() & ~e->pte.size() | 5093804Ssaidi@eecs.umich.edu req->getVaddr() & e->pte.size()); 5103804Ssaidi@eecs.umich.edu return NoFault; 5113806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 5123804Ssaidi@eecs.umich.edu 5133806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 5143806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 5153806Ssaidi@eecs.umich.edu writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 5163806Ssaidi@eecs.umich.edu return new DataAccessException; 5173806Ssaidi@eecs.umich.edu } 5183804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 5193806Ssaidi@eecs.umich.edu req->setMmapedIpr(true); 5203806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 5213806Ssaidi@eecs.umich.edu return NoFault; 5223804Ssaidi@eecs.umich.edu}; 5233804Ssaidi@eecs.umich.edu 5243806Ssaidi@eecs.umich.eduTick 5253806Ssaidi@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 5263806Ssaidi@eecs.umich.edu{ 5273806Ssaidi@eecs.umich.edu panic("need to implement DTB::doMmuRegRead()\n"); 5283806Ssaidi@eecs.umich.edu} 5293806Ssaidi@eecs.umich.edu 5303806Ssaidi@eecs.umich.eduTick 5313806Ssaidi@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 5323806Ssaidi@eecs.umich.edu{ 5333806Ssaidi@eecs.umich.edu panic("need to implement DTB::doMmuRegWrite()\n"); 5343806Ssaidi@eecs.umich.edu} 5353806Ssaidi@eecs.umich.edu 5363804Ssaidi@eecs.umich.eduvoid 5373804Ssaidi@eecs.umich.eduTLB::serialize(std::ostream &os) 5383804Ssaidi@eecs.umich.edu{ 5393804Ssaidi@eecs.umich.edu panic("Need to implement serialize tlb for SPARC\n"); 5403804Ssaidi@eecs.umich.edu} 5413804Ssaidi@eecs.umich.edu 5423804Ssaidi@eecs.umich.eduvoid 5433804Ssaidi@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 5443804Ssaidi@eecs.umich.edu{ 5453804Ssaidi@eecs.umich.edu panic("Need to implement unserialize tlb for SPARC\n"); 5463804Ssaidi@eecs.umich.edu} 5473804Ssaidi@eecs.umich.edu 5483804Ssaidi@eecs.umich.edu 5493804Ssaidi@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 5503804Ssaidi@eecs.umich.edu 5513804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 5523804Ssaidi@eecs.umich.edu 5533804Ssaidi@eecs.umich.edu Param<int> size; 5543804Ssaidi@eecs.umich.edu 5553804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 5563804Ssaidi@eecs.umich.edu 5573804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 5583804Ssaidi@eecs.umich.edu 5593804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 5603804Ssaidi@eecs.umich.edu 5613804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 5623804Ssaidi@eecs.umich.edu 5633804Ssaidi@eecs.umich.edu 5643804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 5653804Ssaidi@eecs.umich.edu{ 5663804Ssaidi@eecs.umich.edu return new ITB(getInstanceName(), size); 5673804Ssaidi@eecs.umich.edu} 5683804Ssaidi@eecs.umich.edu 5693804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcITB", ITB) 5703804Ssaidi@eecs.umich.edu 5713804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 5723804Ssaidi@eecs.umich.edu 5733804Ssaidi@eecs.umich.edu Param<int> size; 5743804Ssaidi@eecs.umich.edu 5753804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 5763804Ssaidi@eecs.umich.edu 5773804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 5783804Ssaidi@eecs.umich.edu 5793804Ssaidi@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 5803804Ssaidi@eecs.umich.edu 5813804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 5823804Ssaidi@eecs.umich.edu 5833804Ssaidi@eecs.umich.edu 5843804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 5853804Ssaidi@eecs.umich.edu{ 5863804Ssaidi@eecs.umich.edu return new DTB(getInstanceName(), size); 5873804Ssaidi@eecs.umich.edu} 5883804Ssaidi@eecs.umich.edu 5893804Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("SparcDTB", DTB) 5903804Ssaidi@eecs.umich.edu} 591