tlb.cc revision 13912
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "arch/sparc/tlb.hh" 3211793Sbrandon.potter@amd.com 333918Ssaidi@eecs.umich.edu#include <cstring> 343918Ssaidi@eecs.umich.edu 353804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 367678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 3713912Sgabeblack@google.com#include "arch/sparc/interrupts.hh" 386335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 393824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 4012620Sgabeblack@google.com#include "base/compiler.hh" 413811Ssaidi@eecs.umich.edu#include "base/trace.hh" 428229Snate@binkert.org#include "cpu/base.hh" 433811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 448232Snate@binkert.org#include "debug/IPR.hh" 458232Snate@binkert.org#include "debug/TLB.hh" 463823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 473823Ssaidi@eecs.umich.edu#include "mem/request.hh" 488751Sgblack@eecs.umich.edu#include "sim/full_system.hh" 494103Ssaidi@eecs.umich.edu#include "sim/system.hh" 503569Sgblack@eecs.umich.edu 513804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 523804Ssaidi@eecs.umich.edu * */ 534088Sbinkertn@umich.edunamespace SparcISA { 543569Sgblack@eecs.umich.edu 555034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 565358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 578374Sksewell@umich.edu cacheState(0), cacheValid(false) 583804Ssaidi@eecs.umich.edu{ 593804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 603804Ssaidi@eecs.umich.edu if (size > 64) 615555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 623569Sgblack@eecs.umich.edu 633804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 643918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 653881Ssaidi@eecs.umich.edu 663881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 673881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 684990Sgblack@eecs.umich.edu 694990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 704990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 714990Sgblack@eecs.umich.edu c0_config = 0; 724990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 734990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 744990Sgblack@eecs.umich.edu cx_config = 0; 754990Sgblack@eecs.umich.edu sfsr = 0; 764990Sgblack@eecs.umich.edu tag_access = 0; 776022Sgblack@eecs.umich.edu sfar = 0; 786022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 796022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 803804Ssaidi@eecs.umich.edu} 813569Sgblack@eecs.umich.edu 823804Ssaidi@eecs.umich.eduvoid 833804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 843804Ssaidi@eecs.umich.edu{ 853804Ssaidi@eecs.umich.edu MapIter i; 863881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 873804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 883804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 893804Ssaidi@eecs.umich.edu t->used = false; 903804Ssaidi@eecs.umich.edu usedEntries--; 913804Ssaidi@eecs.umich.edu } 923804Ssaidi@eecs.umich.edu } 933804Ssaidi@eecs.umich.edu} 943569Sgblack@eecs.umich.edu 953569Sgblack@eecs.umich.edu 963804Ssaidi@eecs.umich.eduvoid 973804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 983826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 993804Ssaidi@eecs.umich.edu{ 1003804Ssaidi@eecs.umich.edu MapIter i; 1013826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 1023907Ssaidi@eecs.umich.edu// TlbRange tr; 1033826Ssaidi@eecs.umich.edu int x; 1043811Ssaidi@eecs.umich.edu 1053836Ssaidi@eecs.umich.edu cacheValid = false; 1063915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1073907Ssaidi@eecs.umich.edu /* tr.va = va; 1083881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1093881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1103881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1113881Ssaidi@eecs.umich.edu tr.real = real; 1123907Ssaidi@eecs.umich.edu*/ 1133881Ssaidi@eecs.umich.edu 1145555Snate@binkert.org DPRINTF(TLB, 1155555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1165555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1173881Ssaidi@eecs.umich.edu 1183881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1193907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1203907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1213907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1223907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1233907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1243907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1253907Ssaidi@eecs.umich.edu { 1263907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1273907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1283907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1293907Ssaidi@eecs.umich.edu 1303907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1313907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1323907Ssaidi@eecs.umich.edu tlb[x].used = false; 1333907Ssaidi@eecs.umich.edu usedEntries--; 1343907Ssaidi@eecs.umich.edu } 1353907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1363907Ssaidi@eecs.umich.edu } 1373907Ssaidi@eecs.umich.edu } 1383907Ssaidi@eecs.umich.edu } 1393907Ssaidi@eecs.umich.edu 1403826Ssaidi@eecs.umich.edu if (entry != -1) { 1413826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1423826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1433826Ssaidi@eecs.umich.edu } else { 1443881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1453881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1463881Ssaidi@eecs.umich.edu } else { 1473881Ssaidi@eecs.umich.edu x = lastReplaced; 1483881Ssaidi@eecs.umich.edu do { 1493881Ssaidi@eecs.umich.edu ++x; 1503881Ssaidi@eecs.umich.edu if (x == size) 1513881Ssaidi@eecs.umich.edu x = 0; 1523881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1533881Ssaidi@eecs.umich.edu goto insertAllLocked; 1543881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1553881Ssaidi@eecs.umich.edu lastReplaced = x; 1563881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1573881Ssaidi@eecs.umich.edu } 1583569Sgblack@eecs.umich.edu } 1593569Sgblack@eecs.umich.edu 1603881Ssaidi@eecs.umich.eduinsertAllLocked: 1613804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1623881Ssaidi@eecs.umich.edu if (!new_entry) { 1633826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1643881Ssaidi@eecs.umich.edu } 1653881Ssaidi@eecs.umich.edu 1663881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1673907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1683907Ssaidi@eecs.umich.edu usedEntries--; 1693929Ssaidi@eecs.umich.edu if (new_entry->valid) 1703929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1713907Ssaidi@eecs.umich.edu 1723907Ssaidi@eecs.umich.edu 1733804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1743804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1753881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1763804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1773804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1783804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1793804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1803804Ssaidi@eecs.umich.edu new_entry->used = true;; 1813804Ssaidi@eecs.umich.edu new_entry->valid = true; 1823804Ssaidi@eecs.umich.edu usedEntries++; 1833569Sgblack@eecs.umich.edu 1843863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1853863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1863804Ssaidi@eecs.umich.edu 1875555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 1885555Snate@binkert.org // but the one we just inserted 1893804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1903804Ssaidi@eecs.umich.edu clearUsedBits(); 1913804Ssaidi@eecs.umich.edu new_entry->used = true; 1923804Ssaidi@eecs.umich.edu usedEntries++; 1933804Ssaidi@eecs.umich.edu } 1943569Sgblack@eecs.umich.edu} 1953804Ssaidi@eecs.umich.edu 1963804Ssaidi@eecs.umich.edu 1973804Ssaidi@eecs.umich.eduTlbEntry* 1985555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 1995555Snate@binkert.org bool update_used) 2003804Ssaidi@eecs.umich.edu{ 2013804Ssaidi@eecs.umich.edu MapIter i; 2023804Ssaidi@eecs.umich.edu TlbRange tr; 2033804Ssaidi@eecs.umich.edu TlbEntry *t; 2043804Ssaidi@eecs.umich.edu 2053811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2063811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2073804Ssaidi@eecs.umich.edu // Assemble full address structure 2083804Ssaidi@eecs.umich.edu tr.va = va; 2095312Sgblack@eecs.umich.edu tr.size = 1; 2103804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2113804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2123804Ssaidi@eecs.umich.edu tr.real = real; 2133804Ssaidi@eecs.umich.edu 2143804Ssaidi@eecs.umich.edu // Try to find the entry 2153804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2163804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2173811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2183804Ssaidi@eecs.umich.edu return NULL; 2193804Ssaidi@eecs.umich.edu } 2203804Ssaidi@eecs.umich.edu 2213804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2223804Ssaidi@eecs.umich.edu t = i->second; 2233826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2243826Ssaidi@eecs.umich.edu t->pte.size()); 2254070Ssaidi@eecs.umich.edu 2265555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2275555Snate@binkert.org // one from virttophys() 2284070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2293804Ssaidi@eecs.umich.edu t->used = true; 2303804Ssaidi@eecs.umich.edu usedEntries++; 2313804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2323804Ssaidi@eecs.umich.edu clearUsedBits(); 2333804Ssaidi@eecs.umich.edu t->used = true; 2343804Ssaidi@eecs.umich.edu usedEntries++; 2353804Ssaidi@eecs.umich.edu } 2363804Ssaidi@eecs.umich.edu } 2373804Ssaidi@eecs.umich.edu 2383804Ssaidi@eecs.umich.edu return t; 2393804Ssaidi@eecs.umich.edu} 2403804Ssaidi@eecs.umich.edu 2413826Ssaidi@eecs.umich.eduvoid 2423826Ssaidi@eecs.umich.eduTLB::dumpAll() 2433826Ssaidi@eecs.umich.edu{ 2443863Ssaidi@eecs.umich.edu MapIter i; 2453826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2463826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2473826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2483826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2493826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2503826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2513826Ssaidi@eecs.umich.edu } 2523826Ssaidi@eecs.umich.edu } 2533826Ssaidi@eecs.umich.edu} 2543804Ssaidi@eecs.umich.edu 2553804Ssaidi@eecs.umich.eduvoid 2563804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2573804Ssaidi@eecs.umich.edu{ 2583804Ssaidi@eecs.umich.edu TlbRange tr; 2593804Ssaidi@eecs.umich.edu MapIter i; 2603804Ssaidi@eecs.umich.edu 2613863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2623863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2633863Ssaidi@eecs.umich.edu 2643836Ssaidi@eecs.umich.edu cacheValid = false; 2653836Ssaidi@eecs.umich.edu 2663804Ssaidi@eecs.umich.edu // Assemble full address structure 2673804Ssaidi@eecs.umich.edu tr.va = va; 2685312Sgblack@eecs.umich.edu tr.size = 1; 2693804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2703804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2713804Ssaidi@eecs.umich.edu tr.real = real; 2723804Ssaidi@eecs.umich.edu 2733804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2743804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2753804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2763863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2773804Ssaidi@eecs.umich.edu i->second->valid = false; 2783804Ssaidi@eecs.umich.edu if (i->second->used) { 2793804Ssaidi@eecs.umich.edu i->second->used = false; 2803804Ssaidi@eecs.umich.edu usedEntries--; 2813804Ssaidi@eecs.umich.edu } 2823881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2833804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2843804Ssaidi@eecs.umich.edu } 2853804Ssaidi@eecs.umich.edu} 2863804Ssaidi@eecs.umich.edu 2873804Ssaidi@eecs.umich.eduvoid 2883804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2893804Ssaidi@eecs.umich.edu{ 2903863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2913863Ssaidi@eecs.umich.edu partition_id, context_id); 2923836Ssaidi@eecs.umich.edu cacheValid = false; 2935555Snate@binkert.org for (int x = 0; x < size; x++) { 2943804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2953804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 29610231Ssteve.reinhardt@amd.com if (tlb[x].valid) { 2973881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2983881Ssaidi@eecs.umich.edu } 2993804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3003804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3013804Ssaidi@eecs.umich.edu tlb[x].used = false; 3023804Ssaidi@eecs.umich.edu usedEntries--; 3033804Ssaidi@eecs.umich.edu } 3043804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3053804Ssaidi@eecs.umich.edu } 3063804Ssaidi@eecs.umich.edu } 3073804Ssaidi@eecs.umich.edu} 3083804Ssaidi@eecs.umich.edu 3093804Ssaidi@eecs.umich.eduvoid 3103804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3113804Ssaidi@eecs.umich.edu{ 3123863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3133836Ssaidi@eecs.umich.edu cacheValid = false; 3145555Snate@binkert.org for (int x = 0; x < size; x++) { 3155288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3165288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3175288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3183804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3193804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3203804Ssaidi@eecs.umich.edu tlb[x].used = false; 3213804Ssaidi@eecs.umich.edu usedEntries--; 3223804Ssaidi@eecs.umich.edu } 3233804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3243804Ssaidi@eecs.umich.edu } 3253804Ssaidi@eecs.umich.edu } 3263804Ssaidi@eecs.umich.edu} 3273804Ssaidi@eecs.umich.edu 3283804Ssaidi@eecs.umich.eduvoid 3299423SAndreas.Sandberg@arm.comTLB::flushAll() 3303804Ssaidi@eecs.umich.edu{ 3313836Ssaidi@eecs.umich.edu cacheValid = false; 3325555Snate@binkert.org lookupTable.clear(); 3333836Ssaidi@eecs.umich.edu 3345555Snate@binkert.org for (int x = 0; x < size; x++) { 33510231Ssteve.reinhardt@amd.com if (tlb[x].valid) 3363881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3373804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3383907Ssaidi@eecs.umich.edu tlb[x].used = false; 3393804Ssaidi@eecs.umich.edu } 3403804Ssaidi@eecs.umich.edu usedEntries = 0; 3413804Ssaidi@eecs.umich.edu} 3423804Ssaidi@eecs.umich.edu 3433804Ssaidi@eecs.umich.eduuint64_t 3445555Snate@binkert.orgTLB::TteRead(int entry) 3455555Snate@binkert.org{ 3463881Ssaidi@eecs.umich.edu if (entry >= size) 3473881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3483881Ssaidi@eecs.umich.edu 3493804Ssaidi@eecs.umich.edu assert(entry < size); 3503881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3513881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3523881Ssaidi@eecs.umich.edu else 3533881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3543804Ssaidi@eecs.umich.edu} 3553804Ssaidi@eecs.umich.edu 3563804Ssaidi@eecs.umich.eduuint64_t 3575555Snate@binkert.orgTLB::TagRead(int entry) 3585555Snate@binkert.org{ 3593804Ssaidi@eecs.umich.edu assert(entry < size); 3603804Ssaidi@eecs.umich.edu uint64_t tag; 3613881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3623881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3633804Ssaidi@eecs.umich.edu 3643881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3653881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3663881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3673804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3683804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3693804Ssaidi@eecs.umich.edu return tag; 3703804Ssaidi@eecs.umich.edu} 3713804Ssaidi@eecs.umich.edu 3723804Ssaidi@eecs.umich.edubool 3733804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3743804Ssaidi@eecs.umich.edu{ 3753804Ssaidi@eecs.umich.edu if (am) 3763804Ssaidi@eecs.umich.edu return true; 3773804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3783804Ssaidi@eecs.umich.edu return false; 3793804Ssaidi@eecs.umich.edu return true; 3803804Ssaidi@eecs.umich.edu} 3813804Ssaidi@eecs.umich.edu 3823804Ssaidi@eecs.umich.eduvoid 3834990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3843804Ssaidi@eecs.umich.edu{ 3853804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3863804Ssaidi@eecs.umich.edu sfsr = 0x3; 3873804Ssaidi@eecs.umich.edu else 3883804Ssaidi@eecs.umich.edu sfsr = 1; 3893804Ssaidi@eecs.umich.edu 3903804Ssaidi@eecs.umich.edu if (write) 3913804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3923804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3933804Ssaidi@eecs.umich.edu if (se) 3943804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3953804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3963804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3973804Ssaidi@eecs.umich.edu} 3983804Ssaidi@eecs.umich.edu 3993826Ssaidi@eecs.umich.eduvoid 4004990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 4013826Ssaidi@eecs.umich.edu{ 4023916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4033916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4043916Ssaidi@eecs.umich.edu 4054990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4063826Ssaidi@eecs.umich.edu} 4073804Ssaidi@eecs.umich.edu 4083804Ssaidi@eecs.umich.eduvoid 4096022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4103804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4113804Ssaidi@eecs.umich.edu{ 4126022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4133811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4144990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4154990Sgblack@eecs.umich.edu sfar = a; 4163804Ssaidi@eecs.umich.edu} 4173804Ssaidi@eecs.umich.edu 4183804Ssaidi@eecs.umich.eduFault 41912749Sgiacomo.travaglini@arm.comTLB::translateInst(const RequestPtr &req, ThreadContext *tc) 4203804Ssaidi@eecs.umich.edu{ 4214172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4223833Ssaidi@eecs.umich.edu 4233836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4243836Ssaidi@eecs.umich.edu TlbEntry *e; 4253836Ssaidi@eecs.umich.edu 4269912Sandreas@sandberg.pp.se assert(req->getArchFlags() == ASI_IMPLICIT); 4273836Ssaidi@eecs.umich.edu 4283836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4293836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4303836Ssaidi@eecs.umich.edu 4313836Ssaidi@eecs.umich.edu // Be fast if we can! 4323836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4336022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4346022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4356022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4366022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4375555Snate@binkert.org return NoFault; 4383836Ssaidi@eecs.umich.edu } 4393836Ssaidi@eecs.umich.edu } else { 4403836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4413836Ssaidi@eecs.umich.edu return NoFault; 4423836Ssaidi@eecs.umich.edu } 4433836Ssaidi@eecs.umich.edu } 4443836Ssaidi@eecs.umich.edu 4453833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4463833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4473833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4483833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4493833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4503833Ssaidi@eecs.umich.edu 4513833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4523833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4533833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4543804Ssaidi@eecs.umich.edu int context; 4553804Ssaidi@eecs.umich.edu ContextType ct; 4563804Ssaidi@eecs.umich.edu int asi; 4573804Ssaidi@eecs.umich.edu bool real = false; 4583804Ssaidi@eecs.umich.edu 4593833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4603833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4613811Ssaidi@eecs.umich.edu 4623804Ssaidi@eecs.umich.edu if (tl > 0) { 4633804Ssaidi@eecs.umich.edu asi = ASI_N; 4643804Ssaidi@eecs.umich.edu ct = Nucleus; 4653804Ssaidi@eecs.umich.edu context = 0; 4663804Ssaidi@eecs.umich.edu } else { 4673804Ssaidi@eecs.umich.edu asi = ASI_P; 4683804Ssaidi@eecs.umich.edu ct = Primary; 4693833Ssaidi@eecs.umich.edu context = pri_context; 4703804Ssaidi@eecs.umich.edu } 4713804Ssaidi@eecs.umich.edu 4723833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4733836Ssaidi@eecs.umich.edu cacheValid = true; 4743836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4756022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4763836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4773804Ssaidi@eecs.umich.edu return NoFault; 4783804Ssaidi@eecs.umich.edu } 4793804Ssaidi@eecs.umich.edu 4803836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4813836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4824990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 48310474Sandreas.hansson@arm.com return std::make_shared<MemAddressNotAligned>(); 4843804Ssaidi@eecs.umich.edu } 4853804Ssaidi@eecs.umich.edu 4863804Ssaidi@eecs.umich.edu if (addr_mask) 4873804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4883804Ssaidi@eecs.umich.edu 4893804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4904990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 49110474Sandreas.hansson@arm.com return std::make_shared<InstructionAccessException>(); 4923804Ssaidi@eecs.umich.edu } 4933804Ssaidi@eecs.umich.edu 4943833Ssaidi@eecs.umich.edu if (!lsu_im) { 4953836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4963804Ssaidi@eecs.umich.edu real = true; 4973804Ssaidi@eecs.umich.edu context = 0; 4983804Ssaidi@eecs.umich.edu } else { 4993804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 5003804Ssaidi@eecs.umich.edu } 5013804Ssaidi@eecs.umich.edu 5023804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5034990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5048751Sgblack@eecs.umich.edu if (real) { 50510474Sandreas.hansson@arm.com return std::make_shared<InstructionRealTranslationMiss>(); 5068751Sgblack@eecs.umich.edu } else { 5078751Sgblack@eecs.umich.edu if (FullSystem) 50810474Sandreas.hansson@arm.com return std::make_shared<FastInstructionAccessMMUMiss>(); 5098751Sgblack@eecs.umich.edu else 51010474Sandreas.hansson@arm.com return std::make_shared<FastInstructionAccessMMUMiss>( 51110474Sandreas.hansson@arm.com req->getVaddr()); 5128751Sgblack@eecs.umich.edu } 5133804Ssaidi@eecs.umich.edu } 5143804Ssaidi@eecs.umich.edu 5153804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5163804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5174990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5184990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 51910474Sandreas.hansson@arm.com return std::make_shared<InstructionAccessException>(); 5203804Ssaidi@eecs.umich.edu } 5213804Ssaidi@eecs.umich.edu 5223836Ssaidi@eecs.umich.edu // cache translation date for next translation 5233836Ssaidi@eecs.umich.edu cacheValid = true; 5243836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5256022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5263836Ssaidi@eecs.umich.edu 5275555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5283836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5293804Ssaidi@eecs.umich.edu return NoFault; 5303804Ssaidi@eecs.umich.edu} 5313804Ssaidi@eecs.umich.edu 5323804Ssaidi@eecs.umich.eduFault 53312749Sgiacomo.travaglini@arm.comTLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 5343804Ssaidi@eecs.umich.edu{ 5355555Snate@binkert.org /* 5365555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5375555Snate@binkert.org * it faster! 5385555Snate@binkert.org */ 5394172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5403836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5413836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5423836Ssaidi@eecs.umich.edu ASI asi; 5439912Sandreas@sandberg.pp.se asi = (ASI)req->getArchFlags(); 5443836Ssaidi@eecs.umich.edu bool implicit = false; 5453836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5465570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5473833Ssaidi@eecs.umich.edu 5483836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5493836Ssaidi@eecs.umich.edu vaddr, size, asi); 5503836Ssaidi@eecs.umich.edu 5513929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5523929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5533929Ssaidi@eecs.umich.edu freeList.size()); 5543836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5553836Ssaidi@eecs.umich.edu implicit = true; 5563836Ssaidi@eecs.umich.edu 5574996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5584996Sgblack@eecs.umich.edu // trap later 5594996Sgblack@eecs.umich.edu if (!unaligned) { 5604996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5614996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5624996Sgblack@eecs.umich.edu return NoFault; 5634996Sgblack@eecs.umich.edu } 5644996Sgblack@eecs.umich.edu 5654996Sgblack@eecs.umich.edu // Be fast if we can! 5664996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5674996Sgblack@eecs.umich.edu 5684996Sgblack@eecs.umich.edu 5694996Sgblack@eecs.umich.edu 5704996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5714996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5724996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5734996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5744996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5754996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5765555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 57710824SAndreas.Sandberg@ARM.com if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 57810824SAndreas.Sandberg@ARM.com req->setFlags( 57910824SAndreas.Sandberg@ARM.com Request::UNCACHEABLE | Request::STRICT_ORDER); 58010824SAndreas.Sandberg@ARM.com } 5815555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5825555Snate@binkert.org return NoFault; 5834996Sgblack@eecs.umich.edu } // if matched 5844996Sgblack@eecs.umich.edu } // if cache entry valid 5854996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5864996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5874996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5884996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 5894996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5904996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5915555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 59210824SAndreas.Sandberg@ARM.com if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 59310824SAndreas.Sandberg@ARM.com req->setFlags( 59410824SAndreas.Sandberg@ARM.com Request::UNCACHEABLE | Request::STRICT_ORDER); 59510824SAndreas.Sandberg@ARM.com } 5965555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5975555Snate@binkert.org return NoFault; 5984996Sgblack@eecs.umich.edu } // if matched 5994996Sgblack@eecs.umich.edu } // if cache entry valid 6004996Sgblack@eecs.umich.edu } 6013836Ssaidi@eecs.umich.edu } 6023836Ssaidi@eecs.umich.edu 6033833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6043833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6053833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6063833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6073833Ssaidi@eecs.umich.edu 6083833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6093833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6103833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6113916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6123833Ssaidi@eecs.umich.edu 6133804Ssaidi@eecs.umich.edu bool real = false; 6143832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6153832Ssaidi@eecs.umich.edu int context = 0; 6163804Ssaidi@eecs.umich.edu 6173804Ssaidi@eecs.umich.edu TlbEntry *e; 6183804Ssaidi@eecs.umich.edu 6193833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6205555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6213804Ssaidi@eecs.umich.edu 6223804Ssaidi@eecs.umich.edu if (implicit) { 6233804Ssaidi@eecs.umich.edu if (tl > 0) { 6243804Ssaidi@eecs.umich.edu asi = ASI_N; 6253804Ssaidi@eecs.umich.edu ct = Nucleus; 6263804Ssaidi@eecs.umich.edu context = 0; 6273804Ssaidi@eecs.umich.edu } else { 6283804Ssaidi@eecs.umich.edu asi = ASI_P; 6293804Ssaidi@eecs.umich.edu ct = Primary; 6303833Ssaidi@eecs.umich.edu context = pri_context; 6313804Ssaidi@eecs.umich.edu } 6323910Ssaidi@eecs.umich.edu } else { 6333804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6347741Sgblack@eecs.umich.edu if (!priv && !hpriv && !asiIsUnPriv(asi)) { 6353804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6364990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 63710474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 6383804Ssaidi@eecs.umich.edu } 6393910Ssaidi@eecs.umich.edu 6407741Sgblack@eecs.umich.edu if (!hpriv && asiIsHPriv(asi)) { 6414990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 64210474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 6433804Ssaidi@eecs.umich.edu } 6443804Ssaidi@eecs.umich.edu 6457741Sgblack@eecs.umich.edu if (asiIsPrimary(asi)) { 6463910Ssaidi@eecs.umich.edu context = pri_context; 6473910Ssaidi@eecs.umich.edu ct = Primary; 6487741Sgblack@eecs.umich.edu } else if (asiIsSecondary(asi)) { 6493910Ssaidi@eecs.umich.edu context = sec_context; 6503910Ssaidi@eecs.umich.edu ct = Secondary; 6517741Sgblack@eecs.umich.edu } else if (asiIsNucleus(asi)) { 6523910Ssaidi@eecs.umich.edu ct = Nucleus; 6533910Ssaidi@eecs.umich.edu context = 0; 6543910Ssaidi@eecs.umich.edu } else { // ???? 6553910Ssaidi@eecs.umich.edu ct = Primary; 6563910Ssaidi@eecs.umich.edu context = pri_context; 6573910Ssaidi@eecs.umich.edu } 6583902Ssaidi@eecs.umich.edu } 6593804Ssaidi@eecs.umich.edu 6603926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6617741Sgblack@eecs.umich.edu if (asiIsLittle(asi)) 6623804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6634989Sgblack@eecs.umich.edu 6644989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6657741Sgblack@eecs.umich.edu // load differs from a regular one, other than what happens concerning 6667741Sgblack@eecs.umich.edu // nfo and e bits in the TTE 6677741Sgblack@eecs.umich.edu// if (asiIsNoFault(asi)) 6684989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6693856Ssaidi@eecs.umich.edu 6707741Sgblack@eecs.umich.edu if (asiIsPartialStore(asi)) 6713804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6724103Ssaidi@eecs.umich.edu 6737741Sgblack@eecs.umich.edu if (asiIsCmt(asi)) 6744191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6754191Ssaidi@eecs.umich.edu 6767741Sgblack@eecs.umich.edu if (asiIsInterrupt(asi)) 6774103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6787741Sgblack@eecs.umich.edu if (asiIsMmu(asi)) 6793804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6807741Sgblack@eecs.umich.edu if (asiIsScratchPad(asi)) 6813804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6827741Sgblack@eecs.umich.edu if (asiIsQueue(asi)) 6833824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6847741Sgblack@eecs.umich.edu if (asiIsSparcError(asi)) 6853825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6863823Ssaidi@eecs.umich.edu 6877741Sgblack@eecs.umich.edu if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 6887741Sgblack@eecs.umich.edu !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 6893823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6903804Ssaidi@eecs.umich.edu } 6913804Ssaidi@eecs.umich.edu 6923826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6934996Sgblack@eecs.umich.edu if (unaligned) { 6944990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 69510474Sandreas.hansson@arm.com return std::make_shared<MemAddressNotAligned>(); 6963826Ssaidi@eecs.umich.edu } 6973826Ssaidi@eecs.umich.edu 6983826Ssaidi@eecs.umich.edu if (addr_mask) 6993826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 7003826Ssaidi@eecs.umich.edu 7013826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7024990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 70310474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7043826Ssaidi@eecs.umich.edu } 7053826Ssaidi@eecs.umich.edu 7067741Sgblack@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 7073804Ssaidi@eecs.umich.edu real = true; 7083804Ssaidi@eecs.umich.edu context = 0; 7095555Snate@binkert.org } 7103804Ssaidi@eecs.umich.edu 7117741Sgblack@eecs.umich.edu if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 7123836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7133804Ssaidi@eecs.umich.edu return NoFault; 7143804Ssaidi@eecs.umich.edu } 7153804Ssaidi@eecs.umich.edu 7163836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7173804Ssaidi@eecs.umich.edu 7183804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7194990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7203811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7218751Sgblack@eecs.umich.edu if (real) { 72210474Sandreas.hansson@arm.com return std::make_shared<DataRealTranslationMiss>(); 7238751Sgblack@eecs.umich.edu } else { 7248751Sgblack@eecs.umich.edu if (FullSystem) 72510474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessMMUMiss>(); 7268751Sgblack@eecs.umich.edu else 72710474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessMMUMiss>( 72810474Sandreas.hansson@arm.com req->getVaddr()); 7298751Sgblack@eecs.umich.edu } 7303804Ssaidi@eecs.umich.edu 7313804Ssaidi@eecs.umich.edu } 7323804Ssaidi@eecs.umich.edu 7333928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7344990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7354990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 73610474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7373928Ssaidi@eecs.umich.edu } 7383804Ssaidi@eecs.umich.edu 7393804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7404990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7414990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 74210474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessProtection>(); 7433804Ssaidi@eecs.umich.edu } 7443804Ssaidi@eecs.umich.edu 7457741Sgblack@eecs.umich.edu if (e->pte.nofault() && !asiIsNoFault(asi)) { 7464990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7474990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 74810474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7493804Ssaidi@eecs.umich.edu } 7503804Ssaidi@eecs.umich.edu 7517741Sgblack@eecs.umich.edu if (e->pte.sideffect() && asiIsNoFault(asi)) { 7524990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7534990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 75410474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7553928Ssaidi@eecs.umich.edu } 7563928Ssaidi@eecs.umich.edu 7574090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 75810824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 7593804Ssaidi@eecs.umich.edu 7603836Ssaidi@eecs.umich.edu // cache translation date for next translation 7613836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7623881Ssaidi@eecs.umich.edu if (!cacheValid) { 7633881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7643881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7653881Ssaidi@eecs.umich.edu } 7663881Ssaidi@eecs.umich.edu 7673836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7683836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7693836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7703836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7713836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7723836Ssaidi@eecs.umich.edu if (implicit) 7733836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7743836Ssaidi@eecs.umich.edu } 7753881Ssaidi@eecs.umich.edu cacheValid = true; 7765555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7773836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7783804Ssaidi@eecs.umich.edu return NoFault; 7794103Ssaidi@eecs.umich.edu 7803806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7814103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7824103Ssaidi@eecs.umich.edu if (!hpriv) { 7834990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7844103Ssaidi@eecs.umich.edu if (priv) 78510474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7864103Ssaidi@eecs.umich.edu else 78710474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 7884103Ssaidi@eecs.umich.edu } 7894103Ssaidi@eecs.umich.edu 7905570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 7915570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 7924990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 79310474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7944103Ssaidi@eecs.umich.edu } 7954103Ssaidi@eecs.umich.edu 7964103Ssaidi@eecs.umich.edu goto regAccessOk; 7974103Ssaidi@eecs.umich.edu 7983804Ssaidi@eecs.umich.edu 7993806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 8003806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 8014990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 80210474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8033806Ssaidi@eecs.umich.edu } 8043824Ssaidi@eecs.umich.edu goto regAccessOk; 8053824Ssaidi@eecs.umich.edu 8063824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8073824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8084990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 80910474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 8103824Ssaidi@eecs.umich.edu } 8115570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8124990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 81310474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8143824Ssaidi@eecs.umich.edu } 8153824Ssaidi@eecs.umich.edu goto regAccessOk; 8163824Ssaidi@eecs.umich.edu 8173825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8183825Ssaidi@eecs.umich.edu if (!hpriv) { 8194990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8204070Ssaidi@eecs.umich.edu if (priv) 82110474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8224070Ssaidi@eecs.umich.edu else 82310474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 8243825Ssaidi@eecs.umich.edu } 8253825Ssaidi@eecs.umich.edu goto regAccessOk; 8263825Ssaidi@eecs.umich.edu 8273825Ssaidi@eecs.umich.edu 8283824Ssaidi@eecs.umich.eduregAccessOk: 8293804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8303811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8318105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 8323806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8333806Ssaidi@eecs.umich.edu return NoFault; 8343804Ssaidi@eecs.umich.edu}; 8353804Ssaidi@eecs.umich.edu 8366022Sgblack@eecs.umich.eduFault 83712749Sgiacomo.travaglini@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 8386022Sgblack@eecs.umich.edu{ 8396023Snate@binkert.org if (mode == Execute) 8406022Sgblack@eecs.umich.edu return translateInst(req, tc); 8416022Sgblack@eecs.umich.edu else 8426023Snate@binkert.org return translateData(req, tc, mode == Write); 8436022Sgblack@eecs.umich.edu} 8446022Sgblack@eecs.umich.edu 8455894Sgblack@eecs.umich.eduvoid 84612749Sgiacomo.travaglini@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 8476023Snate@binkert.org Translation *translation, Mode mode) 8485894Sgblack@eecs.umich.edu{ 8495894Sgblack@eecs.umich.edu assert(translation); 8506023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8515894Sgblack@eecs.umich.edu} 8525894Sgblack@eecs.umich.edu 8538888Sgeoffrey.blake@arm.comFault 85412749Sgiacomo.travaglini@arm.comTLB::finalizePhysical(const RequestPtr &req, 85512749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const 8569738Sandreas@sandberg.pp.se{ 8579738Sandreas@sandberg.pp.se return NoFault; 8589738Sandreas@sandberg.pp.se} 8599738Sandreas@sandberg.pp.se 8609180Sandreas.hansson@arm.comCycles 8616022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8623806Ssaidi@eecs.umich.edu{ 8633823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8649912Sandreas@sandberg.pp.se ASI asi = (ASI)pkt->req->getArchFlags(); 8654070Ssaidi@eecs.umich.edu uint64_t temp; 8663823Ssaidi@eecs.umich.edu 8673823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8689912Sandreas@sandberg.pp.se (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); 8693823Ssaidi@eecs.umich.edu 87012406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 8714990Sgblack@eecs.umich.edu 8723823Ssaidi@eecs.umich.edu switch (asi) { 8733823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8743823Ssaidi@eecs.umich.edu assert(va == 0); 87513231Sgabeblack@google.com pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8763823Ssaidi@eecs.umich.edu break; 8773823Ssaidi@eecs.umich.edu case ASI_MMU: 8783823Ssaidi@eecs.umich.edu switch (va) { 8793823Ssaidi@eecs.umich.edu case 0x8: 88013231Sgabeblack@google.com pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu case 0x10: 88313231Sgabeblack@google.com pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8843823Ssaidi@eecs.umich.edu break; 8853823Ssaidi@eecs.umich.edu default: 8863823Ssaidi@eecs.umich.edu goto doMmuReadError; 8873823Ssaidi@eecs.umich.edu } 8883823Ssaidi@eecs.umich.edu break; 8893824Ssaidi@eecs.umich.edu case ASI_QUEUE: 89013231Sgabeblack@google.com pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8913824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8923824Ssaidi@eecs.umich.edu break; 8933823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8943823Ssaidi@eecs.umich.edu assert(va == 0); 89513231Sgabeblack@google.com pkt->setBE(c0_tsb_ps0); 8963823Ssaidi@eecs.umich.edu break; 8973823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8983823Ssaidi@eecs.umich.edu assert(va == 0); 89913231Sgabeblack@google.com pkt->setBE(c0_tsb_ps1); 9003823Ssaidi@eecs.umich.edu break; 9013823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 9023823Ssaidi@eecs.umich.edu assert(va == 0); 90313231Sgabeblack@google.com pkt->setBE(c0_config); 9043823Ssaidi@eecs.umich.edu break; 9053823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9063823Ssaidi@eecs.umich.edu assert(va == 0); 90713231Sgabeblack@google.com pkt->setBE(itb->c0_tsb_ps0); 9083823Ssaidi@eecs.umich.edu break; 9093823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9103823Ssaidi@eecs.umich.edu assert(va == 0); 91113231Sgabeblack@google.com pkt->setBE(itb->c0_tsb_ps1); 9123823Ssaidi@eecs.umich.edu break; 9133823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9143823Ssaidi@eecs.umich.edu assert(va == 0); 91513231Sgabeblack@google.com pkt->setBE(itb->c0_config); 9163823Ssaidi@eecs.umich.edu break; 9173823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9183823Ssaidi@eecs.umich.edu assert(va == 0); 91913231Sgabeblack@google.com pkt->setBE(cx_tsb_ps0); 9203823Ssaidi@eecs.umich.edu break; 9213823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9223823Ssaidi@eecs.umich.edu assert(va == 0); 92313231Sgabeblack@google.com pkt->setBE(cx_tsb_ps1); 9243823Ssaidi@eecs.umich.edu break; 9253823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9263823Ssaidi@eecs.umich.edu assert(va == 0); 92713231Sgabeblack@google.com pkt->setBE(cx_config); 9283823Ssaidi@eecs.umich.edu break; 9293823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9303823Ssaidi@eecs.umich.edu assert(va == 0); 93113231Sgabeblack@google.com pkt->setBE(itb->cx_tsb_ps0); 9323823Ssaidi@eecs.umich.edu break; 9333823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9343823Ssaidi@eecs.umich.edu assert(va == 0); 93513231Sgabeblack@google.com pkt->setBE(itb->cx_tsb_ps1); 9363823Ssaidi@eecs.umich.edu break; 9373823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9383823Ssaidi@eecs.umich.edu assert(va == 0); 93913231Sgabeblack@google.com pkt->setBE(itb->cx_config); 9403823Ssaidi@eecs.umich.edu break; 9413826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 94213231Sgabeblack@google.com pkt->setBE((uint64_t)0); 9433826Ssaidi@eecs.umich.edu break; 9443823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9453823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 94613231Sgabeblack@google.com pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9473823Ssaidi@eecs.umich.edu break; 9483826Ssaidi@eecs.umich.edu case ASI_IMMU: 9493826Ssaidi@eecs.umich.edu switch (va) { 9503833Ssaidi@eecs.umich.edu case 0x0: 9514990Sgblack@eecs.umich.edu temp = itb->tag_access; 95213231Sgabeblack@google.com pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48); 9533833Ssaidi@eecs.umich.edu break; 9543906Ssaidi@eecs.umich.edu case 0x18: 95513231Sgabeblack@google.com pkt->setBE(itb->sfsr); 9563906Ssaidi@eecs.umich.edu break; 9573826Ssaidi@eecs.umich.edu case 0x30: 95813231Sgabeblack@google.com pkt->setBE(itb->tag_access); 9593826Ssaidi@eecs.umich.edu break; 9603826Ssaidi@eecs.umich.edu default: 9613826Ssaidi@eecs.umich.edu goto doMmuReadError; 9623826Ssaidi@eecs.umich.edu } 9633826Ssaidi@eecs.umich.edu break; 9643823Ssaidi@eecs.umich.edu case ASI_DMMU: 9653823Ssaidi@eecs.umich.edu switch (va) { 9663833Ssaidi@eecs.umich.edu case 0x0: 9674990Sgblack@eecs.umich.edu temp = tag_access; 96813231Sgabeblack@google.com pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48); 9693833Ssaidi@eecs.umich.edu break; 9703906Ssaidi@eecs.umich.edu case 0x18: 97113231Sgabeblack@google.com pkt->setBE(sfsr); 9723906Ssaidi@eecs.umich.edu break; 9733906Ssaidi@eecs.umich.edu case 0x20: 97413231Sgabeblack@google.com pkt->setBE(sfar); 9753906Ssaidi@eecs.umich.edu break; 9763826Ssaidi@eecs.umich.edu case 0x30: 97713231Sgabeblack@google.com pkt->setBE(tag_access); 9783826Ssaidi@eecs.umich.edu break; 9793823Ssaidi@eecs.umich.edu case 0x80: 98013231Sgabeblack@google.com pkt->setBE(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9813823Ssaidi@eecs.umich.edu break; 9823823Ssaidi@eecs.umich.edu default: 9833823Ssaidi@eecs.umich.edu goto doMmuReadError; 9843823Ssaidi@eecs.umich.edu } 9853823Ssaidi@eecs.umich.edu break; 9863833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 98713231Sgabeblack@google.com pkt->setBE(MakeTsbPtr(Ps0, 9884990Sgblack@eecs.umich.edu tag_access, 9894990Sgblack@eecs.umich.edu c0_tsb_ps0, 9904990Sgblack@eecs.umich.edu c0_config, 9914990Sgblack@eecs.umich.edu cx_tsb_ps0, 9924990Sgblack@eecs.umich.edu cx_config)); 9933833Ssaidi@eecs.umich.edu break; 9943833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 99513231Sgabeblack@google.com pkt->setBE(MakeTsbPtr(Ps1, 9964990Sgblack@eecs.umich.edu tag_access, 9974990Sgblack@eecs.umich.edu c0_tsb_ps1, 9984990Sgblack@eecs.umich.edu c0_config, 9994990Sgblack@eecs.umich.edu cx_tsb_ps1, 10004990Sgblack@eecs.umich.edu cx_config)); 10013833Ssaidi@eecs.umich.edu break; 10023899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 100313231Sgabeblack@google.com pkt->setBE(MakeTsbPtr(Ps0, 10044990Sgblack@eecs.umich.edu itb->tag_access, 10054990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10064990Sgblack@eecs.umich.edu itb->c0_config, 10074990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10084990Sgblack@eecs.umich.edu itb->cx_config)); 10093899Ssaidi@eecs.umich.edu break; 10103899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 101113231Sgabeblack@google.com pkt->setBE(MakeTsbPtr(Ps1, 10124990Sgblack@eecs.umich.edu itb->tag_access, 10134990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10144990Sgblack@eecs.umich.edu itb->c0_config, 10154990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10164990Sgblack@eecs.umich.edu itb->cx_config)); 10173899Ssaidi@eecs.umich.edu break; 10184103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10195646Sgblack@eecs.umich.edu { 10205646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10215646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 102211150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 102313231Sgabeblack@google.com pkt->setBE(interrupts->get_vec(IT_INT_VEC)); 10245646Sgblack@eecs.umich.edu } 10254103Ssaidi@eecs.umich.edu break; 10264103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10275646Sgblack@eecs.umich.edu { 10285646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10295646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 103011150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 10315646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 103211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp); 103313231Sgabeblack@google.com pkt->setBE(temp); 10345646Sgblack@eecs.umich.edu } 10354103Ssaidi@eecs.umich.edu break; 10363823Ssaidi@eecs.umich.edu default: 10373823Ssaidi@eecs.umich.edudoMmuReadError: 10383823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10393823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10403823Ssaidi@eecs.umich.edu } 10414870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10429180Sandreas.hansson@arm.com return Cycles(1); 10433806Ssaidi@eecs.umich.edu} 10443806Ssaidi@eecs.umich.edu 10459180Sandreas.hansson@arm.comCycles 10466022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10473806Ssaidi@eecs.umich.edu{ 104813231Sgabeblack@google.com uint64_t data = pkt->getBE<uint64_t>(); 10493823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10509912Sandreas@sandberg.pp.se ASI asi = (ASI)pkt->req->getArchFlags(); 10513823Ssaidi@eecs.umich.edu 10523826Ssaidi@eecs.umich.edu Addr ta_insert; 10533826Ssaidi@eecs.umich.edu Addr va_insert; 10543826Ssaidi@eecs.umich.edu Addr ct_insert; 10553826Ssaidi@eecs.umich.edu int part_insert; 10563826Ssaidi@eecs.umich.edu int entry_insert = -1; 10573826Ssaidi@eecs.umich.edu bool real_insert; 10583863Ssaidi@eecs.umich.edu bool ignore; 10593863Ssaidi@eecs.umich.edu int part_id; 10603863Ssaidi@eecs.umich.edu int ctx_id; 10613826Ssaidi@eecs.umich.edu PageTableEntry pte; 10623826Ssaidi@eecs.umich.edu 10633825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10643823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10653823Ssaidi@eecs.umich.edu 106612406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 10674990Sgblack@eecs.umich.edu 10683823Ssaidi@eecs.umich.edu switch (asi) { 10693823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10703823Ssaidi@eecs.umich.edu assert(va == 0); 10714172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10723823Ssaidi@eecs.umich.edu break; 10733823Ssaidi@eecs.umich.edu case ASI_MMU: 10743823Ssaidi@eecs.umich.edu switch (va) { 10753823Ssaidi@eecs.umich.edu case 0x8: 10764172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10773823Ssaidi@eecs.umich.edu break; 10783823Ssaidi@eecs.umich.edu case 0x10: 10794172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10803823Ssaidi@eecs.umich.edu break; 10813823Ssaidi@eecs.umich.edu default: 10823823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10833823Ssaidi@eecs.umich.edu } 10843823Ssaidi@eecs.umich.edu break; 10853824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10863825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10874172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10883824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10893824Ssaidi@eecs.umich.edu break; 10903823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10913823Ssaidi@eecs.umich.edu assert(va == 0); 10924990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10933823Ssaidi@eecs.umich.edu break; 10943823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10953823Ssaidi@eecs.umich.edu assert(va == 0); 10964990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10973823Ssaidi@eecs.umich.edu break; 10983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10993823Ssaidi@eecs.umich.edu assert(va == 0); 11004990Sgblack@eecs.umich.edu c0_config = data; 11013823Ssaidi@eecs.umich.edu break; 11023823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 11033823Ssaidi@eecs.umich.edu assert(va == 0); 11044990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 11053823Ssaidi@eecs.umich.edu break; 11063823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11073823Ssaidi@eecs.umich.edu assert(va == 0); 11084990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11093823Ssaidi@eecs.umich.edu break; 11103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11113823Ssaidi@eecs.umich.edu assert(va == 0); 11124990Sgblack@eecs.umich.edu itb->c0_config = data; 11133823Ssaidi@eecs.umich.edu break; 11143823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11153823Ssaidi@eecs.umich.edu assert(va == 0); 11164990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11173823Ssaidi@eecs.umich.edu break; 11183823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11193823Ssaidi@eecs.umich.edu assert(va == 0); 11204990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11213823Ssaidi@eecs.umich.edu break; 11223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11233823Ssaidi@eecs.umich.edu assert(va == 0); 11244990Sgblack@eecs.umich.edu cx_config = data; 11253823Ssaidi@eecs.umich.edu break; 11263823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11273823Ssaidi@eecs.umich.edu assert(va == 0); 11284990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11293823Ssaidi@eecs.umich.edu break; 11303823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11313823Ssaidi@eecs.umich.edu assert(va == 0); 11324990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11333823Ssaidi@eecs.umich.edu break; 11343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11353823Ssaidi@eecs.umich.edu assert(va == 0); 11364990Sgblack@eecs.umich.edu itb->cx_config = data; 11373823Ssaidi@eecs.umich.edu break; 11383825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11393825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11405823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11413825Ssaidi@eecs.umich.edu break; 11423823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11433823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11444172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11453823Ssaidi@eecs.umich.edu break; 11463826Ssaidi@eecs.umich.edu case ASI_IMMU: 11473826Ssaidi@eecs.umich.edu switch (va) { 11483906Ssaidi@eecs.umich.edu case 0x18: 11494990Sgblack@eecs.umich.edu itb->sfsr = data; 11503906Ssaidi@eecs.umich.edu break; 11513826Ssaidi@eecs.umich.edu case 0x30: 11523916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11534990Sgblack@eecs.umich.edu itb->tag_access = data; 11543826Ssaidi@eecs.umich.edu break; 11553826Ssaidi@eecs.umich.edu default: 11563826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11573826Ssaidi@eecs.umich.edu } 11583826Ssaidi@eecs.umich.edu break; 11593826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11603826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 116112620Sgabeblack@google.com M5_FALLTHROUGH; 11623826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11633826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11644990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11653826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11663826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11674172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11683826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11693826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11703826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 117112406Sgabeblack@google.com itb->insert(va_insert, part_insert, ct_insert, real_insert, 117212406Sgabeblack@google.com pte, entry_insert); 11733826Ssaidi@eecs.umich.edu break; 11743826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11753826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 117612620Sgabeblack@google.com M5_FALLTHROUGH; 11773826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11783826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11794990Sgblack@eecs.umich.edu ta_insert = tag_access; 11803826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11813826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11824172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11833826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11843826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11853826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11865555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11875555Snate@binkert.org entry_insert); 11883826Ssaidi@eecs.umich.edu break; 11893863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11903863Ssaidi@eecs.umich.edu ignore = false; 11913863Ssaidi@eecs.umich.edu ctx_id = -1; 11924172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11933863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11943863Ssaidi@eecs.umich.edu case 0: 11954172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11963863Ssaidi@eecs.umich.edu break; 11973863Ssaidi@eecs.umich.edu case 1: 11983863Ssaidi@eecs.umich.edu ignore = true; 11993863Ssaidi@eecs.umich.edu break; 12003863Ssaidi@eecs.umich.edu case 3: 12013863Ssaidi@eecs.umich.edu ctx_id = 0; 12023863Ssaidi@eecs.umich.edu break; 12033863Ssaidi@eecs.umich.edu default: 12043863Ssaidi@eecs.umich.edu ignore = true; 12053863Ssaidi@eecs.umich.edu } 12063863Ssaidi@eecs.umich.edu 12077741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12083863Ssaidi@eecs.umich.edu case 0: // demap page 12093863Ssaidi@eecs.umich.edu if (!ignore) 121012406Sgabeblack@google.com itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12113863Ssaidi@eecs.umich.edu break; 12127741Sgblack@eecs.umich.edu case 1: // demap context 12133863Ssaidi@eecs.umich.edu if (!ignore) 121412406Sgabeblack@google.com itb->demapContext(part_id, ctx_id); 12153863Ssaidi@eecs.umich.edu break; 12163863Ssaidi@eecs.umich.edu case 2: 121712406Sgabeblack@google.com itb->demapAll(part_id); 12183863Ssaidi@eecs.umich.edu break; 12193863Ssaidi@eecs.umich.edu default: 12203863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12213863Ssaidi@eecs.umich.edu } 12223863Ssaidi@eecs.umich.edu break; 12233823Ssaidi@eecs.umich.edu case ASI_DMMU: 12243823Ssaidi@eecs.umich.edu switch (va) { 12253906Ssaidi@eecs.umich.edu case 0x18: 12264990Sgblack@eecs.umich.edu sfsr = data; 12273906Ssaidi@eecs.umich.edu break; 12283826Ssaidi@eecs.umich.edu case 0x30: 12293916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12304990Sgblack@eecs.umich.edu tag_access = data; 12313826Ssaidi@eecs.umich.edu break; 12323823Ssaidi@eecs.umich.edu case 0x80: 12334172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12343823Ssaidi@eecs.umich.edu break; 12353823Ssaidi@eecs.umich.edu default: 12363823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12373823Ssaidi@eecs.umich.edu } 12383823Ssaidi@eecs.umich.edu break; 12393863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12403863Ssaidi@eecs.umich.edu ignore = false; 12413863Ssaidi@eecs.umich.edu ctx_id = -1; 12424172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12433863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12443863Ssaidi@eecs.umich.edu case 0: 12454172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12463863Ssaidi@eecs.umich.edu break; 12473863Ssaidi@eecs.umich.edu case 1: 12484172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12493863Ssaidi@eecs.umich.edu break; 12503863Ssaidi@eecs.umich.edu case 3: 12513863Ssaidi@eecs.umich.edu ctx_id = 0; 12523863Ssaidi@eecs.umich.edu break; 12533863Ssaidi@eecs.umich.edu default: 12543863Ssaidi@eecs.umich.edu ignore = true; 12553863Ssaidi@eecs.umich.edu } 12563863Ssaidi@eecs.umich.edu 12577741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12583863Ssaidi@eecs.umich.edu case 0: // demap page 12593863Ssaidi@eecs.umich.edu if (!ignore) 12603863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12613863Ssaidi@eecs.umich.edu break; 12627741Sgblack@eecs.umich.edu case 1: // demap context 12633863Ssaidi@eecs.umich.edu if (!ignore) 12643863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12653863Ssaidi@eecs.umich.edu break; 12663863Ssaidi@eecs.umich.edu case 2: 12673863Ssaidi@eecs.umich.edu demapAll(part_id); 12683863Ssaidi@eecs.umich.edu break; 12693863Ssaidi@eecs.umich.edu default: 12703863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12713863Ssaidi@eecs.umich.edu } 12723863Ssaidi@eecs.umich.edu break; 12734103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12745646Sgblack@eecs.umich.edu { 12755646Sgblack@eecs.umich.edu int msb; 12765646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12775646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12785646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 127911150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 12805704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12815646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 128211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb); 12835646Sgblack@eecs.umich.edu } 12844103Ssaidi@eecs.umich.edu } 12854103Ssaidi@eecs.umich.edu break; 12864103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12874103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 128811150Smitch.hayenga@arm.com postInterrupt(0, bits(data, 5, 0), 0); 12894103Ssaidi@eecs.umich.edu break; 12905555Snate@binkert.org default: 12913823Ssaidi@eecs.umich.edudoMmuWriteError: 12923823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12939912Sandreas@sandberg.pp.se (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data); 12943823Ssaidi@eecs.umich.edu } 12954870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12969180Sandreas.hansson@arm.com return Cycles(1); 12973806Ssaidi@eecs.umich.edu} 12983806Ssaidi@eecs.umich.edu 12993804Ssaidi@eecs.umich.eduvoid 13006022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 13014070Ssaidi@eecs.umich.edu{ 13024070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 130312406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 13044070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 13054990Sgblack@eecs.umich.edu c0_tsb_ps0, 13064990Sgblack@eecs.umich.edu c0_config, 13074990Sgblack@eecs.umich.edu cx_tsb_ps0, 13084990Sgblack@eecs.umich.edu cx_config); 13094070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13104990Sgblack@eecs.umich.edu c0_tsb_ps1, 13114990Sgblack@eecs.umich.edu c0_config, 13124990Sgblack@eecs.umich.edu cx_tsb_ps1, 13134990Sgblack@eecs.umich.edu cx_config); 13144070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13154990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13164990Sgblack@eecs.umich.edu itb->c0_config, 13174990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13184990Sgblack@eecs.umich.edu itb->cx_config); 13194070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13204990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13214990Sgblack@eecs.umich.edu itb->c0_config, 13224990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13234990Sgblack@eecs.umich.edu itb->cx_config); 13244070Ssaidi@eecs.umich.edu} 13254070Ssaidi@eecs.umich.edu 13264070Ssaidi@eecs.umich.eduuint64_t 13276022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13284070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13294070Ssaidi@eecs.umich.edu{ 13304070Ssaidi@eecs.umich.edu uint64_t tsb; 13314070Ssaidi@eecs.umich.edu uint64_t config; 13324070Ssaidi@eecs.umich.edu 13334070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13344070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13354070Ssaidi@eecs.umich.edu config = c0_config; 13364070Ssaidi@eecs.umich.edu } else { 13374070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13384070Ssaidi@eecs.umich.edu config = cX_config; 13394070Ssaidi@eecs.umich.edu } 13404070Ssaidi@eecs.umich.edu 13414070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13424070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13434070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13444070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13454070Ssaidi@eecs.umich.edu 13464070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13474070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13484070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13494070Ssaidi@eecs.umich.edu 13504070Ssaidi@eecs.umich.edu return ptr; 13514070Ssaidi@eecs.umich.edu} 13524070Ssaidi@eecs.umich.edu 13534070Ssaidi@eecs.umich.eduvoid 135410905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 13553804Ssaidi@eecs.umich.edu{ 13564000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13574000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13584000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13594000Ssaidi@eecs.umich.edu 13604000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 136110905Sandreas.sandberg@arm.com std::vector<int> free_list; 136210905Sandreas.sandberg@arm.com for (const TlbEntry *entry : freeList) 136310905Sandreas.sandberg@arm.com free_list.push_back(entry - tlb); 136410905Sandreas.sandberg@arm.com 136510905Sandreas.sandberg@arm.com SERIALIZE_CONTAINER(free_list); 13664000Ssaidi@eecs.umich.edu 13674990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13684990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13694990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13704990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13714990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13724990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13734990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13744990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 137512544Skhalique913@gmail.com SERIALIZE_SCALAR(sfar); 13765276Ssaidi@eecs.umich.edu 13775276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 137810905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 137910905Sandreas.sandberg@arm.com tlb[x].serialize(cp); 13805276Ssaidi@eecs.umich.edu } 13813804Ssaidi@eecs.umich.edu} 13823804Ssaidi@eecs.umich.edu 13833804Ssaidi@eecs.umich.eduvoid 138410905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 13853804Ssaidi@eecs.umich.edu{ 13864000Ssaidi@eecs.umich.edu int oldSize; 13874000Ssaidi@eecs.umich.edu 138810905Sandreas.sandberg@arm.com paramIn(cp, "size", oldSize); 13894000Ssaidi@eecs.umich.edu if (oldSize != size) 13904000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13914000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13924000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13934000Ssaidi@eecs.umich.edu 139410905Sandreas.sandberg@arm.com std::vector<int> free_list; 139510905Sandreas.sandberg@arm.com UNSERIALIZE_CONTAINER(free_list); 13964000Ssaidi@eecs.umich.edu freeList.clear(); 139710905Sandreas.sandberg@arm.com for (int idx : free_list) 139810905Sandreas.sandberg@arm.com freeList.push_back(&tlb[idx]); 13994000Ssaidi@eecs.umich.edu 14004990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 14014990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 14024990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 14034990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 14044990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14054990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14064990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14074990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14085276Ssaidi@eecs.umich.edu 14095276Ssaidi@eecs.umich.edu lookupTable.clear(); 14105276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 141110905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 141210905Sandreas.sandberg@arm.com tlb[x].unserialize(cp); 14135276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14145276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14155276Ssaidi@eecs.umich.edu 14165276Ssaidi@eecs.umich.edu } 14174990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14183804Ssaidi@eecs.umich.edu} 14193804Ssaidi@eecs.umich.edu 14207811Ssteve.reinhardt@amd.com} // namespace SparcISA 14214088Sbinkertn@umich.edu 14226022Sgblack@eecs.umich.eduSparcISA::TLB * 14236022Sgblack@eecs.umich.eduSparcTLBParams::create() 14243804Ssaidi@eecs.umich.edu{ 14256022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14263804Ssaidi@eecs.umich.edu} 1427