tlb.cc revision 12544
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 33569Sgblack@eecs.umich.edu * All rights reserved. 43569Sgblack@eecs.umich.edu * 53569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu * this software without specific prior written permission. 153569Sgblack@eecs.umich.edu * 163569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu * 283804Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293569Sgblack@eecs.umich.edu */ 303569Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "arch/sparc/tlb.hh" 3211793Sbrandon.potter@amd.com 333918Ssaidi@eecs.umich.edu#include <cstring> 343918Ssaidi@eecs.umich.edu 353804Ssaidi@eecs.umich.edu#include "arch/sparc/asi.hh" 367678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 376335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 383824Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 393811Ssaidi@eecs.umich.edu#include "base/trace.hh" 408229Snate@binkert.org#include "cpu/base.hh" 413811Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 428232Snate@binkert.org#include "debug/IPR.hh" 438232Snate@binkert.org#include "debug/TLB.hh" 443823Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 453823Ssaidi@eecs.umich.edu#include "mem/request.hh" 468751Sgblack@eecs.umich.edu#include "sim/full_system.hh" 474103Ssaidi@eecs.umich.edu#include "sim/system.hh" 483569Sgblack@eecs.umich.edu 493804Ssaidi@eecs.umich.edu/* @todo remove some of the magic constants. -- ali 503804Ssaidi@eecs.umich.edu * */ 514088Sbinkertn@umich.edunamespace SparcISA { 523569Sgblack@eecs.umich.edu 535034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 545358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), 558374Sksewell@umich.edu cacheState(0), cacheValid(false) 563804Ssaidi@eecs.umich.edu{ 573804Ssaidi@eecs.umich.edu // To make this work you'll have to change the hypervisor and OS 583804Ssaidi@eecs.umich.edu if (size > 64) 595555Snate@binkert.org fatal("SPARC T1 TLB registers don't support more than 64 TLB entries"); 603569Sgblack@eecs.umich.edu 613804Ssaidi@eecs.umich.edu tlb = new TlbEntry[size]; 623918Ssaidi@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 633881Ssaidi@eecs.umich.edu 643881Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) 653881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 664990Sgblack@eecs.umich.edu 674990Sgblack@eecs.umich.edu c0_tsb_ps0 = 0; 684990Sgblack@eecs.umich.edu c0_tsb_ps1 = 0; 694990Sgblack@eecs.umich.edu c0_config = 0; 704990Sgblack@eecs.umich.edu cx_tsb_ps0 = 0; 714990Sgblack@eecs.umich.edu cx_tsb_ps1 = 0; 724990Sgblack@eecs.umich.edu cx_config = 0; 734990Sgblack@eecs.umich.edu sfsr = 0; 744990Sgblack@eecs.umich.edu tag_access = 0; 756022Sgblack@eecs.umich.edu sfar = 0; 766022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 776022Sgblack@eecs.umich.edu cacheEntry[1] = NULL; 783804Ssaidi@eecs.umich.edu} 793569Sgblack@eecs.umich.edu 803804Ssaidi@eecs.umich.eduvoid 813804Ssaidi@eecs.umich.eduTLB::clearUsedBits() 823804Ssaidi@eecs.umich.edu{ 833804Ssaidi@eecs.umich.edu MapIter i; 843881Ssaidi@eecs.umich.edu for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 853804Ssaidi@eecs.umich.edu TlbEntry *t = i->second; 863804Ssaidi@eecs.umich.edu if (!t->pte.locked()) { 873804Ssaidi@eecs.umich.edu t->used = false; 883804Ssaidi@eecs.umich.edu usedEntries--; 893804Ssaidi@eecs.umich.edu } 903804Ssaidi@eecs.umich.edu } 913804Ssaidi@eecs.umich.edu} 923569Sgblack@eecs.umich.edu 933569Sgblack@eecs.umich.edu 943804Ssaidi@eecs.umich.eduvoid 953804Ssaidi@eecs.umich.eduTLB::insert(Addr va, int partition_id, int context_id, bool real, 963826Ssaidi@eecs.umich.edu const PageTableEntry& PTE, int entry) 973804Ssaidi@eecs.umich.edu{ 983804Ssaidi@eecs.umich.edu MapIter i; 993826Ssaidi@eecs.umich.edu TlbEntry *new_entry = NULL; 1003907Ssaidi@eecs.umich.edu// TlbRange tr; 1013826Ssaidi@eecs.umich.edu int x; 1023811Ssaidi@eecs.umich.edu 1033836Ssaidi@eecs.umich.edu cacheValid = false; 1043915Ssaidi@eecs.umich.edu va &= ~(PTE.size()-1); 1053907Ssaidi@eecs.umich.edu /* tr.va = va; 1063881Ssaidi@eecs.umich.edu tr.size = PTE.size() - 1; 1073881Ssaidi@eecs.umich.edu tr.contextId = context_id; 1083881Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 1093881Ssaidi@eecs.umich.edu tr.real = real; 1103907Ssaidi@eecs.umich.edu*/ 1113881Ssaidi@eecs.umich.edu 1125555Snate@binkert.org DPRINTF(TLB, 1135555Snate@binkert.org "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 1145555Snate@binkert.org va, PTE.paddr(), partition_id, context_id, (int)real, entry); 1153881Ssaidi@eecs.umich.edu 1163881Ssaidi@eecs.umich.edu // Demap any entry that conflicts 1173907Ssaidi@eecs.umich.edu for (x = 0; x < size; x++) { 1183907Ssaidi@eecs.umich.edu if (tlb[x].range.real == real && 1193907Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id && 1203907Ssaidi@eecs.umich.edu tlb[x].range.va < va + PTE.size() - 1 && 1213907Ssaidi@eecs.umich.edu tlb[x].range.va + tlb[x].range.size >= va && 1223907Ssaidi@eecs.umich.edu (real || tlb[x].range.contextId == context_id )) 1233907Ssaidi@eecs.umich.edu { 1243907Ssaidi@eecs.umich.edu if (tlb[x].valid) { 1253907Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 1263907Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 1273907Ssaidi@eecs.umich.edu 1283907Ssaidi@eecs.umich.edu tlb[x].valid = false; 1293907Ssaidi@eecs.umich.edu if (tlb[x].used) { 1303907Ssaidi@eecs.umich.edu tlb[x].used = false; 1313907Ssaidi@eecs.umich.edu usedEntries--; 1323907Ssaidi@eecs.umich.edu } 1333907Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 1343907Ssaidi@eecs.umich.edu } 1353907Ssaidi@eecs.umich.edu } 1363907Ssaidi@eecs.umich.edu } 1373907Ssaidi@eecs.umich.edu 1383826Ssaidi@eecs.umich.edu if (entry != -1) { 1393826Ssaidi@eecs.umich.edu assert(entry < size && entry >= 0); 1403826Ssaidi@eecs.umich.edu new_entry = &tlb[entry]; 1413826Ssaidi@eecs.umich.edu } else { 1423881Ssaidi@eecs.umich.edu if (!freeList.empty()) { 1433881Ssaidi@eecs.umich.edu new_entry = freeList.front(); 1443881Ssaidi@eecs.umich.edu } else { 1453881Ssaidi@eecs.umich.edu x = lastReplaced; 1463881Ssaidi@eecs.umich.edu do { 1473881Ssaidi@eecs.umich.edu ++x; 1483881Ssaidi@eecs.umich.edu if (x == size) 1493881Ssaidi@eecs.umich.edu x = 0; 1503881Ssaidi@eecs.umich.edu if (x == lastReplaced) 1513881Ssaidi@eecs.umich.edu goto insertAllLocked; 1523881Ssaidi@eecs.umich.edu } while (tlb[x].pte.locked()); 1533881Ssaidi@eecs.umich.edu lastReplaced = x; 1543881Ssaidi@eecs.umich.edu new_entry = &tlb[x]; 1553881Ssaidi@eecs.umich.edu } 1563569Sgblack@eecs.umich.edu } 1573569Sgblack@eecs.umich.edu 1583881Ssaidi@eecs.umich.eduinsertAllLocked: 1593804Ssaidi@eecs.umich.edu // Update the last ently if their all locked 1603881Ssaidi@eecs.umich.edu if (!new_entry) { 1613826Ssaidi@eecs.umich.edu new_entry = &tlb[size-1]; 1623881Ssaidi@eecs.umich.edu } 1633881Ssaidi@eecs.umich.edu 1643881Ssaidi@eecs.umich.edu freeList.remove(new_entry); 1653907Ssaidi@eecs.umich.edu if (new_entry->valid && new_entry->used) 1663907Ssaidi@eecs.umich.edu usedEntries--; 1673929Ssaidi@eecs.umich.edu if (new_entry->valid) 1683929Ssaidi@eecs.umich.edu lookupTable.erase(new_entry->range); 1693907Ssaidi@eecs.umich.edu 1703907Ssaidi@eecs.umich.edu 1713804Ssaidi@eecs.umich.edu assert(PTE.valid()); 1723804Ssaidi@eecs.umich.edu new_entry->range.va = va; 1733881Ssaidi@eecs.umich.edu new_entry->range.size = PTE.size() - 1; 1743804Ssaidi@eecs.umich.edu new_entry->range.partitionId = partition_id; 1753804Ssaidi@eecs.umich.edu new_entry->range.contextId = context_id; 1763804Ssaidi@eecs.umich.edu new_entry->range.real = real; 1773804Ssaidi@eecs.umich.edu new_entry->pte = PTE; 1783804Ssaidi@eecs.umich.edu new_entry->used = true;; 1793804Ssaidi@eecs.umich.edu new_entry->valid = true; 1803804Ssaidi@eecs.umich.edu usedEntries++; 1813569Sgblack@eecs.umich.edu 1823863Ssaidi@eecs.umich.edu i = lookupTable.insert(new_entry->range, new_entry); 1833863Ssaidi@eecs.umich.edu assert(i != lookupTable.end()); 1843804Ssaidi@eecs.umich.edu 1855555Snate@binkert.org // If all entries have their used bit set, clear it on them all, 1865555Snate@binkert.org // but the one we just inserted 1873804Ssaidi@eecs.umich.edu if (usedEntries == size) { 1883804Ssaidi@eecs.umich.edu clearUsedBits(); 1893804Ssaidi@eecs.umich.edu new_entry->used = true; 1903804Ssaidi@eecs.umich.edu usedEntries++; 1913804Ssaidi@eecs.umich.edu } 1923569Sgblack@eecs.umich.edu} 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.edu 1953804Ssaidi@eecs.umich.eduTlbEntry* 1965555Snate@binkert.orgTLB::lookup(Addr va, int partition_id, bool real, int context_id, 1975555Snate@binkert.org bool update_used) 1983804Ssaidi@eecs.umich.edu{ 1993804Ssaidi@eecs.umich.edu MapIter i; 2003804Ssaidi@eecs.umich.edu TlbRange tr; 2013804Ssaidi@eecs.umich.edu TlbEntry *t; 2023804Ssaidi@eecs.umich.edu 2033811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 2043811Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2053804Ssaidi@eecs.umich.edu // Assemble full address structure 2063804Ssaidi@eecs.umich.edu tr.va = va; 2075312Sgblack@eecs.umich.edu tr.size = 1; 2083804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2093804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2103804Ssaidi@eecs.umich.edu tr.real = real; 2113804Ssaidi@eecs.umich.edu 2123804Ssaidi@eecs.umich.edu // Try to find the entry 2133804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2143804Ssaidi@eecs.umich.edu if (i == lookupTable.end()) { 2153811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: No valid entry found\n"); 2163804Ssaidi@eecs.umich.edu return NULL; 2173804Ssaidi@eecs.umich.edu } 2183804Ssaidi@eecs.umich.edu 2193804Ssaidi@eecs.umich.edu // Mark the entries used bit and clear other used bits in needed 2203804Ssaidi@eecs.umich.edu t = i->second; 2213826Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 2223826Ssaidi@eecs.umich.edu t->pte.size()); 2234070Ssaidi@eecs.umich.edu 2245555Snate@binkert.org // Update the used bits only if this is a real access (not a fake 2255555Snate@binkert.org // one from virttophys() 2264070Ssaidi@eecs.umich.edu if (!t->used && update_used) { 2273804Ssaidi@eecs.umich.edu t->used = true; 2283804Ssaidi@eecs.umich.edu usedEntries++; 2293804Ssaidi@eecs.umich.edu if (usedEntries == size) { 2303804Ssaidi@eecs.umich.edu clearUsedBits(); 2313804Ssaidi@eecs.umich.edu t->used = true; 2323804Ssaidi@eecs.umich.edu usedEntries++; 2333804Ssaidi@eecs.umich.edu } 2343804Ssaidi@eecs.umich.edu } 2353804Ssaidi@eecs.umich.edu 2363804Ssaidi@eecs.umich.edu return t; 2373804Ssaidi@eecs.umich.edu} 2383804Ssaidi@eecs.umich.edu 2393826Ssaidi@eecs.umich.eduvoid 2403826Ssaidi@eecs.umich.eduTLB::dumpAll() 2413826Ssaidi@eecs.umich.edu{ 2423863Ssaidi@eecs.umich.edu MapIter i; 2433826Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 2443826Ssaidi@eecs.umich.edu if (tlb[x].valid) { 2453826Ssaidi@eecs.umich.edu DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 2463826Ssaidi@eecs.umich.edu x, tlb[x].range.partitionId, tlb[x].range.contextId, 2473826Ssaidi@eecs.umich.edu tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 2483826Ssaidi@eecs.umich.edu tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 2493826Ssaidi@eecs.umich.edu } 2503826Ssaidi@eecs.umich.edu } 2513826Ssaidi@eecs.umich.edu} 2523804Ssaidi@eecs.umich.edu 2533804Ssaidi@eecs.umich.eduvoid 2543804Ssaidi@eecs.umich.eduTLB::demapPage(Addr va, int partition_id, bool real, int context_id) 2553804Ssaidi@eecs.umich.edu{ 2563804Ssaidi@eecs.umich.edu TlbRange tr; 2573804Ssaidi@eecs.umich.edu MapIter i; 2583804Ssaidi@eecs.umich.edu 2593863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 2603863Ssaidi@eecs.umich.edu va, partition_id, context_id, real); 2613863Ssaidi@eecs.umich.edu 2623836Ssaidi@eecs.umich.edu cacheValid = false; 2633836Ssaidi@eecs.umich.edu 2643804Ssaidi@eecs.umich.edu // Assemble full address structure 2653804Ssaidi@eecs.umich.edu tr.va = va; 2665312Sgblack@eecs.umich.edu tr.size = 1; 2673804Ssaidi@eecs.umich.edu tr.contextId = context_id; 2683804Ssaidi@eecs.umich.edu tr.partitionId = partition_id; 2693804Ssaidi@eecs.umich.edu tr.real = real; 2703804Ssaidi@eecs.umich.edu 2713804Ssaidi@eecs.umich.edu // Demap any entry that conflicts 2723804Ssaidi@eecs.umich.edu i = lookupTable.find(tr); 2733804Ssaidi@eecs.umich.edu if (i != lookupTable.end()) { 2743863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapped page\n"); 2753804Ssaidi@eecs.umich.edu i->second->valid = false; 2763804Ssaidi@eecs.umich.edu if (i->second->used) { 2773804Ssaidi@eecs.umich.edu i->second->used = false; 2783804Ssaidi@eecs.umich.edu usedEntries--; 2793804Ssaidi@eecs.umich.edu } 2803881Ssaidi@eecs.umich.edu freeList.push_front(i->second); 2813804Ssaidi@eecs.umich.edu lookupTable.erase(i); 2823804Ssaidi@eecs.umich.edu } 2833804Ssaidi@eecs.umich.edu} 2843804Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.eduvoid 2863804Ssaidi@eecs.umich.eduTLB::demapContext(int partition_id, int context_id) 2873804Ssaidi@eecs.umich.edu{ 2883863Ssaidi@eecs.umich.edu DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 2893863Ssaidi@eecs.umich.edu partition_id, context_id); 2903836Ssaidi@eecs.umich.edu cacheValid = false; 2915555Snate@binkert.org for (int x = 0; x < size; x++) { 2923804Ssaidi@eecs.umich.edu if (tlb[x].range.contextId == context_id && 2933804Ssaidi@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 29410231Ssteve.reinhardt@amd.com if (tlb[x].valid) { 2953881Ssaidi@eecs.umich.edu freeList.push_front(&tlb[x]); 2963881Ssaidi@eecs.umich.edu } 2973804Ssaidi@eecs.umich.edu tlb[x].valid = false; 2983804Ssaidi@eecs.umich.edu if (tlb[x].used) { 2993804Ssaidi@eecs.umich.edu tlb[x].used = false; 3003804Ssaidi@eecs.umich.edu usedEntries--; 3013804Ssaidi@eecs.umich.edu } 3023804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3033804Ssaidi@eecs.umich.edu } 3043804Ssaidi@eecs.umich.edu } 3053804Ssaidi@eecs.umich.edu} 3063804Ssaidi@eecs.umich.edu 3073804Ssaidi@eecs.umich.eduvoid 3083804Ssaidi@eecs.umich.eduTLB::demapAll(int partition_id) 3093804Ssaidi@eecs.umich.edu{ 3103863Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 3113836Ssaidi@eecs.umich.edu cacheValid = false; 3125555Snate@binkert.org for (int x = 0; x < size; x++) { 3135288Sgblack@eecs.umich.edu if (tlb[x].valid && !tlb[x].pte.locked() && 3145288Sgblack@eecs.umich.edu tlb[x].range.partitionId == partition_id) { 3155288Sgblack@eecs.umich.edu freeList.push_front(&tlb[x]); 3163804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3173804Ssaidi@eecs.umich.edu if (tlb[x].used) { 3183804Ssaidi@eecs.umich.edu tlb[x].used = false; 3193804Ssaidi@eecs.umich.edu usedEntries--; 3203804Ssaidi@eecs.umich.edu } 3213804Ssaidi@eecs.umich.edu lookupTable.erase(tlb[x].range); 3223804Ssaidi@eecs.umich.edu } 3233804Ssaidi@eecs.umich.edu } 3243804Ssaidi@eecs.umich.edu} 3253804Ssaidi@eecs.umich.edu 3263804Ssaidi@eecs.umich.eduvoid 3279423SAndreas.Sandberg@arm.comTLB::flushAll() 3283804Ssaidi@eecs.umich.edu{ 3293836Ssaidi@eecs.umich.edu cacheValid = false; 3305555Snate@binkert.org lookupTable.clear(); 3313836Ssaidi@eecs.umich.edu 3325555Snate@binkert.org for (int x = 0; x < size; x++) { 33310231Ssteve.reinhardt@amd.com if (tlb[x].valid) 3343881Ssaidi@eecs.umich.edu freeList.push_back(&tlb[x]); 3353804Ssaidi@eecs.umich.edu tlb[x].valid = false; 3363907Ssaidi@eecs.umich.edu tlb[x].used = false; 3373804Ssaidi@eecs.umich.edu } 3383804Ssaidi@eecs.umich.edu usedEntries = 0; 3393804Ssaidi@eecs.umich.edu} 3403804Ssaidi@eecs.umich.edu 3413804Ssaidi@eecs.umich.eduuint64_t 3425555Snate@binkert.orgTLB::TteRead(int entry) 3435555Snate@binkert.org{ 3443881Ssaidi@eecs.umich.edu if (entry >= size) 3453881Ssaidi@eecs.umich.edu panic("entry: %d\n", entry); 3463881Ssaidi@eecs.umich.edu 3473804Ssaidi@eecs.umich.edu assert(entry < size); 3483881Ssaidi@eecs.umich.edu if (tlb[entry].valid) 3493881Ssaidi@eecs.umich.edu return tlb[entry].pte(); 3503881Ssaidi@eecs.umich.edu else 3513881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3523804Ssaidi@eecs.umich.edu} 3533804Ssaidi@eecs.umich.edu 3543804Ssaidi@eecs.umich.eduuint64_t 3555555Snate@binkert.orgTLB::TagRead(int entry) 3565555Snate@binkert.org{ 3573804Ssaidi@eecs.umich.edu assert(entry < size); 3583804Ssaidi@eecs.umich.edu uint64_t tag; 3593881Ssaidi@eecs.umich.edu if (!tlb[entry].valid) 3603881Ssaidi@eecs.umich.edu return (uint64_t)-1ll; 3613804Ssaidi@eecs.umich.edu 3623881Ssaidi@eecs.umich.edu tag = tlb[entry].range.contextId; 3633881Ssaidi@eecs.umich.edu tag |= tlb[entry].range.va; 3643881Ssaidi@eecs.umich.edu tag |= (uint64_t)tlb[entry].range.partitionId << 61; 3653804Ssaidi@eecs.umich.edu tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 3663804Ssaidi@eecs.umich.edu tag |= (uint64_t)~tlb[entry].pte._size() << 56; 3673804Ssaidi@eecs.umich.edu return tag; 3683804Ssaidi@eecs.umich.edu} 3693804Ssaidi@eecs.umich.edu 3703804Ssaidi@eecs.umich.edubool 3713804Ssaidi@eecs.umich.eduTLB::validVirtualAddress(Addr va, bool am) 3723804Ssaidi@eecs.umich.edu{ 3733804Ssaidi@eecs.umich.edu if (am) 3743804Ssaidi@eecs.umich.edu return true; 3753804Ssaidi@eecs.umich.edu if (va >= StartVAddrHole && va <= EndVAddrHole) 3763804Ssaidi@eecs.umich.edu return false; 3773804Ssaidi@eecs.umich.edu return true; 3783804Ssaidi@eecs.umich.edu} 3793804Ssaidi@eecs.umich.edu 3803804Ssaidi@eecs.umich.eduvoid 3814990Sgblack@eecs.umich.eduTLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) 3823804Ssaidi@eecs.umich.edu{ 3833804Ssaidi@eecs.umich.edu if (sfsr & 0x1) 3843804Ssaidi@eecs.umich.edu sfsr = 0x3; 3853804Ssaidi@eecs.umich.edu else 3863804Ssaidi@eecs.umich.edu sfsr = 1; 3873804Ssaidi@eecs.umich.edu 3883804Ssaidi@eecs.umich.edu if (write) 3893804Ssaidi@eecs.umich.edu sfsr |= 1 << 2; 3903804Ssaidi@eecs.umich.edu sfsr |= ct << 4; 3913804Ssaidi@eecs.umich.edu if (se) 3923804Ssaidi@eecs.umich.edu sfsr |= 1 << 6; 3933804Ssaidi@eecs.umich.edu sfsr |= ft << 7; 3943804Ssaidi@eecs.umich.edu sfsr |= asi << 16; 3953804Ssaidi@eecs.umich.edu} 3963804Ssaidi@eecs.umich.edu 3973826Ssaidi@eecs.umich.eduvoid 3984990Sgblack@eecs.umich.eduTLB::writeTagAccess(Addr va, int context) 3993826Ssaidi@eecs.umich.edu{ 4003916Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 4013916Ssaidi@eecs.umich.edu va, context, mbits(va, 63,13) | mbits(context,12,0)); 4023916Ssaidi@eecs.umich.edu 4034990Sgblack@eecs.umich.edu tag_access = mbits(va, 63,13) | mbits(context,12,0); 4043826Ssaidi@eecs.umich.edu} 4053804Ssaidi@eecs.umich.edu 4063804Ssaidi@eecs.umich.eduvoid 4076022Sgblack@eecs.umich.eduTLB::writeSfsr(Addr a, bool write, ContextType ct, 4083804Ssaidi@eecs.umich.edu bool se, FaultTypes ft, int asi) 4093804Ssaidi@eecs.umich.edu{ 4106022Sgblack@eecs.umich.edu DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 4113811Ssaidi@eecs.umich.edu a, (int)write, ct, ft, asi); 4124990Sgblack@eecs.umich.edu TLB::writeSfsr(write, ct, se, ft, asi); 4134990Sgblack@eecs.umich.edu sfar = a; 4143804Ssaidi@eecs.umich.edu} 4153804Ssaidi@eecs.umich.edu 4163804Ssaidi@eecs.umich.eduFault 4176022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 4183804Ssaidi@eecs.umich.edu{ 4194172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 4203833Ssaidi@eecs.umich.edu 4213836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 4223836Ssaidi@eecs.umich.edu TlbEntry *e; 4233836Ssaidi@eecs.umich.edu 4249912Sandreas@sandberg.pp.se assert(req->getArchFlags() == ASI_IMPLICIT); 4253836Ssaidi@eecs.umich.edu 4263836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 4273836Ssaidi@eecs.umich.edu vaddr, req->getSize()); 4283836Ssaidi@eecs.umich.edu 4293836Ssaidi@eecs.umich.edu // Be fast if we can! 4303836Ssaidi@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 4316022Sgblack@eecs.umich.edu if (cacheEntry[0]) { 4326022Sgblack@eecs.umich.edu if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && 4336022Sgblack@eecs.umich.edu cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 4346022Sgblack@eecs.umich.edu req->setPaddr(cacheEntry[0]->pte.translate(vaddr)); 4355555Snate@binkert.org return NoFault; 4363836Ssaidi@eecs.umich.edu } 4373836Ssaidi@eecs.umich.edu } else { 4383836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4393836Ssaidi@eecs.umich.edu return NoFault; 4403836Ssaidi@eecs.umich.edu } 4413836Ssaidi@eecs.umich.edu } 4423836Ssaidi@eecs.umich.edu 4433833Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 4443833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 4453833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 4463833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 4473833Ssaidi@eecs.umich.edu bool lsu_im = bits(tlbdata,4,4); 4483833Ssaidi@eecs.umich.edu 4493833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 4503833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 4513833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 4523804Ssaidi@eecs.umich.edu int context; 4533804Ssaidi@eecs.umich.edu ContextType ct; 4543804Ssaidi@eecs.umich.edu int asi; 4553804Ssaidi@eecs.umich.edu bool real = false; 4563804Ssaidi@eecs.umich.edu 4573833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 4583833Ssaidi@eecs.umich.edu priv, hpriv, red, lsu_im, part_id); 4593811Ssaidi@eecs.umich.edu 4603804Ssaidi@eecs.umich.edu if (tl > 0) { 4613804Ssaidi@eecs.umich.edu asi = ASI_N; 4623804Ssaidi@eecs.umich.edu ct = Nucleus; 4633804Ssaidi@eecs.umich.edu context = 0; 4643804Ssaidi@eecs.umich.edu } else { 4653804Ssaidi@eecs.umich.edu asi = ASI_P; 4663804Ssaidi@eecs.umich.edu ct = Primary; 4673833Ssaidi@eecs.umich.edu context = pri_context; 4683804Ssaidi@eecs.umich.edu } 4693804Ssaidi@eecs.umich.edu 4703833Ssaidi@eecs.umich.edu if ( hpriv || red ) { 4713836Ssaidi@eecs.umich.edu cacheValid = true; 4723836Ssaidi@eecs.umich.edu cacheState = tlbdata; 4736022Sgblack@eecs.umich.edu cacheEntry[0] = NULL; 4743836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 4753804Ssaidi@eecs.umich.edu return NoFault; 4763804Ssaidi@eecs.umich.edu } 4773804Ssaidi@eecs.umich.edu 4783836Ssaidi@eecs.umich.edu // If the access is unaligned trap 4793836Ssaidi@eecs.umich.edu if (vaddr & 0x3) { 4804990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, OtherFault, asi); 48110474Sandreas.hansson@arm.com return std::make_shared<MemAddressNotAligned>(); 4823804Ssaidi@eecs.umich.edu } 4833804Ssaidi@eecs.umich.edu 4843804Ssaidi@eecs.umich.edu if (addr_mask) 4853804Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 4863804Ssaidi@eecs.umich.edu 4873804Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 4884990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, VaOutOfRange, asi); 48910474Sandreas.hansson@arm.com return std::make_shared<InstructionAccessException>(); 4903804Ssaidi@eecs.umich.edu } 4913804Ssaidi@eecs.umich.edu 4923833Ssaidi@eecs.umich.edu if (!lsu_im) { 4933836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, true); 4943804Ssaidi@eecs.umich.edu real = true; 4953804Ssaidi@eecs.umich.edu context = 0; 4963804Ssaidi@eecs.umich.edu } else { 4973804Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, false, context); 4983804Ssaidi@eecs.umich.edu } 4993804Ssaidi@eecs.umich.edu 5003804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 5014990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5028751Sgblack@eecs.umich.edu if (real) { 50310474Sandreas.hansson@arm.com return std::make_shared<InstructionRealTranslationMiss>(); 5048751Sgblack@eecs.umich.edu } else { 5058751Sgblack@eecs.umich.edu if (FullSystem) 50610474Sandreas.hansson@arm.com return std::make_shared<FastInstructionAccessMMUMiss>(); 5078751Sgblack@eecs.umich.edu else 50810474Sandreas.hansson@arm.com return std::make_shared<FastInstructionAccessMMUMiss>( 50910474Sandreas.hansson@arm.com req->getVaddr()); 5108751Sgblack@eecs.umich.edu } 5113804Ssaidi@eecs.umich.edu } 5123804Ssaidi@eecs.umich.edu 5133804Ssaidi@eecs.umich.edu // were not priviledged accesing priv page 5143804Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 5154990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 5164990Sgblack@eecs.umich.edu writeSfsr(false, ct, false, PrivViolation, asi); 51710474Sandreas.hansson@arm.com return std::make_shared<InstructionAccessException>(); 5183804Ssaidi@eecs.umich.edu } 5193804Ssaidi@eecs.umich.edu 5203836Ssaidi@eecs.umich.edu // cache translation date for next translation 5213836Ssaidi@eecs.umich.edu cacheValid = true; 5223836Ssaidi@eecs.umich.edu cacheState = tlbdata; 5236022Sgblack@eecs.umich.edu cacheEntry[0] = e; 5243836Ssaidi@eecs.umich.edu 5255555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 5263836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5273804Ssaidi@eecs.umich.edu return NoFault; 5283804Ssaidi@eecs.umich.edu} 5293804Ssaidi@eecs.umich.edu 5303804Ssaidi@eecs.umich.eduFault 5316022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 5323804Ssaidi@eecs.umich.edu{ 5335555Snate@binkert.org /* 5345555Snate@binkert.org * @todo this could really use some profiling and fixing to make 5355555Snate@binkert.org * it faster! 5365555Snate@binkert.org */ 5374172Ssaidi@eecs.umich.edu uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 5383836Ssaidi@eecs.umich.edu Addr vaddr = req->getVaddr(); 5393836Ssaidi@eecs.umich.edu Addr size = req->getSize(); 5403836Ssaidi@eecs.umich.edu ASI asi; 5419912Sandreas@sandberg.pp.se asi = (ASI)req->getArchFlags(); 5423836Ssaidi@eecs.umich.edu bool implicit = false; 5433836Ssaidi@eecs.umich.edu bool hpriv = bits(tlbdata,0,0); 5445570Snate@binkert.org bool unaligned = vaddr & (size - 1); 5453833Ssaidi@eecs.umich.edu 5463836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 5473836Ssaidi@eecs.umich.edu vaddr, size, asi); 5483836Ssaidi@eecs.umich.edu 5493929Ssaidi@eecs.umich.edu if (lookupTable.size() != 64 - freeList.size()) 5503929Ssaidi@eecs.umich.edu panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 5513929Ssaidi@eecs.umich.edu freeList.size()); 5523836Ssaidi@eecs.umich.edu if (asi == ASI_IMPLICIT) 5533836Ssaidi@eecs.umich.edu implicit = true; 5543836Ssaidi@eecs.umich.edu 5554996Sgblack@eecs.umich.edu // Only use the fast path here if there doesn't need to be an unaligned 5564996Sgblack@eecs.umich.edu // trap later 5574996Sgblack@eecs.umich.edu if (!unaligned) { 5584996Sgblack@eecs.umich.edu if (hpriv && implicit) { 5594996Sgblack@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 5604996Sgblack@eecs.umich.edu return NoFault; 5614996Sgblack@eecs.umich.edu } 5624996Sgblack@eecs.umich.edu 5634996Sgblack@eecs.umich.edu // Be fast if we can! 5644996Sgblack@eecs.umich.edu if (cacheValid && cacheState == tlbdata) { 5654996Sgblack@eecs.umich.edu 5664996Sgblack@eecs.umich.edu 5674996Sgblack@eecs.umich.edu 5684996Sgblack@eecs.umich.edu if (cacheEntry[0]) { 5694996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[0]; 5704996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5714996Sgblack@eecs.umich.edu if (cacheAsi[0] == asi && 5724996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5734996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5745555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 57510824SAndreas.Sandberg@ARM.com if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 57610824SAndreas.Sandberg@ARM.com req->setFlags( 57710824SAndreas.Sandberg@ARM.com Request::UNCACHEABLE | Request::STRICT_ORDER); 57810824SAndreas.Sandberg@ARM.com } 5795555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5805555Snate@binkert.org return NoFault; 5814996Sgblack@eecs.umich.edu } // if matched 5824996Sgblack@eecs.umich.edu } // if cache entry valid 5834996Sgblack@eecs.umich.edu if (cacheEntry[1]) { 5844996Sgblack@eecs.umich.edu TlbEntry *ce = cacheEntry[1]; 5854996Sgblack@eecs.umich.edu Addr ce_va = ce->range.va; 5864996Sgblack@eecs.umich.edu if (cacheAsi[1] == asi && 5874996Sgblack@eecs.umich.edu ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 5884996Sgblack@eecs.umich.edu (!write || ce->pte.writable())) { 5895555Snate@binkert.org req->setPaddr(ce->pte.translate(vaddr)); 59010824SAndreas.Sandberg@ARM.com if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) { 59110824SAndreas.Sandberg@ARM.com req->setFlags( 59210824SAndreas.Sandberg@ARM.com Request::UNCACHEABLE | Request::STRICT_ORDER); 59310824SAndreas.Sandberg@ARM.com } 5945555Snate@binkert.org DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 5955555Snate@binkert.org return NoFault; 5964996Sgblack@eecs.umich.edu } // if matched 5974996Sgblack@eecs.umich.edu } // if cache entry valid 5984996Sgblack@eecs.umich.edu } 5993836Ssaidi@eecs.umich.edu } 6003836Ssaidi@eecs.umich.edu 6013833Ssaidi@eecs.umich.edu bool red = bits(tlbdata,1,1); 6023833Ssaidi@eecs.umich.edu bool priv = bits(tlbdata,2,2); 6033833Ssaidi@eecs.umich.edu bool addr_mask = bits(tlbdata,3,3); 6043833Ssaidi@eecs.umich.edu bool lsu_dm = bits(tlbdata,5,5); 6053833Ssaidi@eecs.umich.edu 6063833Ssaidi@eecs.umich.edu int part_id = bits(tlbdata,15,8); 6073833Ssaidi@eecs.umich.edu int tl = bits(tlbdata,18,16); 6083833Ssaidi@eecs.umich.edu int pri_context = bits(tlbdata,47,32); 6093916Ssaidi@eecs.umich.edu int sec_context = bits(tlbdata,63,48); 6103833Ssaidi@eecs.umich.edu 6113804Ssaidi@eecs.umich.edu bool real = false; 6123832Ssaidi@eecs.umich.edu ContextType ct = Primary; 6133832Ssaidi@eecs.umich.edu int context = 0; 6143804Ssaidi@eecs.umich.edu 6153804Ssaidi@eecs.umich.edu TlbEntry *e; 6163804Ssaidi@eecs.umich.edu 6173833Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 6185555Snate@binkert.org priv, hpriv, red, lsu_dm, part_id); 6193804Ssaidi@eecs.umich.edu 6203804Ssaidi@eecs.umich.edu if (implicit) { 6213804Ssaidi@eecs.umich.edu if (tl > 0) { 6223804Ssaidi@eecs.umich.edu asi = ASI_N; 6233804Ssaidi@eecs.umich.edu ct = Nucleus; 6243804Ssaidi@eecs.umich.edu context = 0; 6253804Ssaidi@eecs.umich.edu } else { 6263804Ssaidi@eecs.umich.edu asi = ASI_P; 6273804Ssaidi@eecs.umich.edu ct = Primary; 6283833Ssaidi@eecs.umich.edu context = pri_context; 6293804Ssaidi@eecs.umich.edu } 6303910Ssaidi@eecs.umich.edu } else { 6313804Ssaidi@eecs.umich.edu // We need to check for priv level/asi priv 6327741Sgblack@eecs.umich.edu if (!priv && !hpriv && !asiIsUnPriv(asi)) { 6333804Ssaidi@eecs.umich.edu // It appears that context should be Nucleus in these cases? 6344990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 63510474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 6363804Ssaidi@eecs.umich.edu } 6373910Ssaidi@eecs.umich.edu 6387741Sgblack@eecs.umich.edu if (!hpriv && asiIsHPriv(asi)) { 6394990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 64010474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 6413804Ssaidi@eecs.umich.edu } 6423804Ssaidi@eecs.umich.edu 6437741Sgblack@eecs.umich.edu if (asiIsPrimary(asi)) { 6443910Ssaidi@eecs.umich.edu context = pri_context; 6453910Ssaidi@eecs.umich.edu ct = Primary; 6467741Sgblack@eecs.umich.edu } else if (asiIsSecondary(asi)) { 6473910Ssaidi@eecs.umich.edu context = sec_context; 6483910Ssaidi@eecs.umich.edu ct = Secondary; 6497741Sgblack@eecs.umich.edu } else if (asiIsNucleus(asi)) { 6503910Ssaidi@eecs.umich.edu ct = Nucleus; 6513910Ssaidi@eecs.umich.edu context = 0; 6523910Ssaidi@eecs.umich.edu } else { // ???? 6533910Ssaidi@eecs.umich.edu ct = Primary; 6543910Ssaidi@eecs.umich.edu context = pri_context; 6553910Ssaidi@eecs.umich.edu } 6563902Ssaidi@eecs.umich.edu } 6573804Ssaidi@eecs.umich.edu 6583926Ssaidi@eecs.umich.edu if (!implicit && asi != ASI_P && asi != ASI_S) { 6597741Sgblack@eecs.umich.edu if (asiIsLittle(asi)) 6603804Ssaidi@eecs.umich.edu panic("Little Endian ASIs not supported\n"); 6614989Sgblack@eecs.umich.edu 6624989Sgblack@eecs.umich.edu //XXX It's unclear from looking at the documentation how a no fault 6637741Sgblack@eecs.umich.edu // load differs from a regular one, other than what happens concerning 6647741Sgblack@eecs.umich.edu // nfo and e bits in the TTE 6657741Sgblack@eecs.umich.edu// if (asiIsNoFault(asi)) 6664989Sgblack@eecs.umich.edu// panic("No Fault ASIs not supported\n"); 6673856Ssaidi@eecs.umich.edu 6687741Sgblack@eecs.umich.edu if (asiIsPartialStore(asi)) 6693804Ssaidi@eecs.umich.edu panic("Partial Store ASIs not supported\n"); 6704103Ssaidi@eecs.umich.edu 6717741Sgblack@eecs.umich.edu if (asiIsCmt(asi)) 6724191Ssaidi@eecs.umich.edu panic("Cmt ASI registers not implmented\n"); 6734191Ssaidi@eecs.umich.edu 6747741Sgblack@eecs.umich.edu if (asiIsInterrupt(asi)) 6754103Ssaidi@eecs.umich.edu goto handleIntRegAccess; 6767741Sgblack@eecs.umich.edu if (asiIsMmu(asi)) 6773804Ssaidi@eecs.umich.edu goto handleMmuRegAccess; 6787741Sgblack@eecs.umich.edu if (asiIsScratchPad(asi)) 6793804Ssaidi@eecs.umich.edu goto handleScratchRegAccess; 6807741Sgblack@eecs.umich.edu if (asiIsQueue(asi)) 6813824Ssaidi@eecs.umich.edu goto handleQueueRegAccess; 6827741Sgblack@eecs.umich.edu if (asiIsSparcError(asi)) 6833825Ssaidi@eecs.umich.edu goto handleSparcErrorRegAccess; 6843823Ssaidi@eecs.umich.edu 6857741Sgblack@eecs.umich.edu if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 6867741Sgblack@eecs.umich.edu !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) 6873823Ssaidi@eecs.umich.edu panic("Accessing ASI %#X. Should we?\n", asi); 6883804Ssaidi@eecs.umich.edu } 6893804Ssaidi@eecs.umich.edu 6903826Ssaidi@eecs.umich.edu // If the asi is unaligned trap 6914996Sgblack@eecs.umich.edu if (unaligned) { 6924990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, false, OtherFault, asi); 69310474Sandreas.hansson@arm.com return std::make_shared<MemAddressNotAligned>(); 6943826Ssaidi@eecs.umich.edu } 6953826Ssaidi@eecs.umich.edu 6963826Ssaidi@eecs.umich.edu if (addr_mask) 6973826Ssaidi@eecs.umich.edu vaddr = vaddr & VAddrAMask; 6983826Ssaidi@eecs.umich.edu 6993826Ssaidi@eecs.umich.edu if (!validVirtualAddress(vaddr, addr_mask)) { 7004990Sgblack@eecs.umich.edu writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 70110474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7023826Ssaidi@eecs.umich.edu } 7033826Ssaidi@eecs.umich.edu 7047741Sgblack@eecs.umich.edu if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { 7053804Ssaidi@eecs.umich.edu real = true; 7063804Ssaidi@eecs.umich.edu context = 0; 7075555Snate@binkert.org } 7083804Ssaidi@eecs.umich.edu 7097741Sgblack@eecs.umich.edu if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { 7103836Ssaidi@eecs.umich.edu req->setPaddr(vaddr & PAddrImplMask); 7113804Ssaidi@eecs.umich.edu return NoFault; 7123804Ssaidi@eecs.umich.edu } 7133804Ssaidi@eecs.umich.edu 7143836Ssaidi@eecs.umich.edu e = lookup(vaddr, part_id, real, context); 7153804Ssaidi@eecs.umich.edu 7163804Ssaidi@eecs.umich.edu if (e == NULL || !e->valid) { 7174990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7183811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 7198751Sgblack@eecs.umich.edu if (real) { 72010474Sandreas.hansson@arm.com return std::make_shared<DataRealTranslationMiss>(); 7218751Sgblack@eecs.umich.edu } else { 7228751Sgblack@eecs.umich.edu if (FullSystem) 72310474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessMMUMiss>(); 7248751Sgblack@eecs.umich.edu else 72510474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessMMUMiss>( 72610474Sandreas.hansson@arm.com req->getVaddr()); 7278751Sgblack@eecs.umich.edu } 7283804Ssaidi@eecs.umich.edu 7293804Ssaidi@eecs.umich.edu } 7303804Ssaidi@eecs.umich.edu 7313928Ssaidi@eecs.umich.edu if (!priv && e->pte.priv()) { 7324990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7334990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 73410474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7353928Ssaidi@eecs.umich.edu } 7363804Ssaidi@eecs.umich.edu 7373804Ssaidi@eecs.umich.edu if (write && !e->pte.writable()) { 7384990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7394990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 74010474Sandreas.hansson@arm.com return std::make_shared<FastDataAccessProtection>(); 7413804Ssaidi@eecs.umich.edu } 7423804Ssaidi@eecs.umich.edu 7437741Sgblack@eecs.umich.edu if (e->pte.nofault() && !asiIsNoFault(asi)) { 7444990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7454990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 74610474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7473804Ssaidi@eecs.umich.edu } 7483804Ssaidi@eecs.umich.edu 7497741Sgblack@eecs.umich.edu if (e->pte.sideffect() && asiIsNoFault(asi)) { 7504990Sgblack@eecs.umich.edu writeTagAccess(vaddr, context); 7514990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 75210474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7533928Ssaidi@eecs.umich.edu } 7543928Ssaidi@eecs.umich.edu 7554090Ssaidi@eecs.umich.edu if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 75610824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 7573804Ssaidi@eecs.umich.edu 7583836Ssaidi@eecs.umich.edu // cache translation date for next translation 7593836Ssaidi@eecs.umich.edu cacheState = tlbdata; 7603881Ssaidi@eecs.umich.edu if (!cacheValid) { 7613881Ssaidi@eecs.umich.edu cacheEntry[1] = NULL; 7623881Ssaidi@eecs.umich.edu cacheEntry[0] = NULL; 7633881Ssaidi@eecs.umich.edu } 7643881Ssaidi@eecs.umich.edu 7653836Ssaidi@eecs.umich.edu if (cacheEntry[0] != e && cacheEntry[1] != e) { 7663836Ssaidi@eecs.umich.edu cacheEntry[1] = cacheEntry[0]; 7673836Ssaidi@eecs.umich.edu cacheEntry[0] = e; 7683836Ssaidi@eecs.umich.edu cacheAsi[1] = cacheAsi[0]; 7693836Ssaidi@eecs.umich.edu cacheAsi[0] = asi; 7703836Ssaidi@eecs.umich.edu if (implicit) 7713836Ssaidi@eecs.umich.edu cacheAsi[0] = (ASI)0; 7723836Ssaidi@eecs.umich.edu } 7733881Ssaidi@eecs.umich.edu cacheValid = true; 7745555Snate@binkert.org req->setPaddr(e->pte.translate(vaddr)); 7753836Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 7763804Ssaidi@eecs.umich.edu return NoFault; 7774103Ssaidi@eecs.umich.edu 7783806Ssaidi@eecs.umich.edu /** Normal flow ends here. */ 7794103Ssaidi@eecs.umich.eduhandleIntRegAccess: 7804103Ssaidi@eecs.umich.edu if (!hpriv) { 7814990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 7824103Ssaidi@eecs.umich.edu if (priv) 78310474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7844103Ssaidi@eecs.umich.edu else 78510474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 7864103Ssaidi@eecs.umich.edu } 7874103Ssaidi@eecs.umich.edu 7885570Snate@binkert.org if ((asi == ASI_SWVR_UDB_INTR_W && !write) || 7895570Snate@binkert.org (asi == ASI_SWVR_UDB_INTR_R && write)) { 7904990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 79110474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 7924103Ssaidi@eecs.umich.edu } 7934103Ssaidi@eecs.umich.edu 7944103Ssaidi@eecs.umich.edu goto regAccessOk; 7954103Ssaidi@eecs.umich.edu 7963804Ssaidi@eecs.umich.edu 7973806Ssaidi@eecs.umich.eduhandleScratchRegAccess: 7983806Ssaidi@eecs.umich.edu if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 7994990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 80010474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8013806Ssaidi@eecs.umich.edu } 8023824Ssaidi@eecs.umich.edu goto regAccessOk; 8033824Ssaidi@eecs.umich.edu 8043824Ssaidi@eecs.umich.eduhandleQueueRegAccess: 8053824Ssaidi@eecs.umich.edu if (!priv && !hpriv) { 8064990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 80710474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 8083824Ssaidi@eecs.umich.edu } 8095570Snate@binkert.org if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) { 8104990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 81110474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8123824Ssaidi@eecs.umich.edu } 8133824Ssaidi@eecs.umich.edu goto regAccessOk; 8143824Ssaidi@eecs.umich.edu 8153825Ssaidi@eecs.umich.eduhandleSparcErrorRegAccess: 8163825Ssaidi@eecs.umich.edu if (!hpriv) { 8174990Sgblack@eecs.umich.edu writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); 8184070Ssaidi@eecs.umich.edu if (priv) 81910474Sandreas.hansson@arm.com return std::make_shared<DataAccessException>(); 8204070Ssaidi@eecs.umich.edu else 82110474Sandreas.hansson@arm.com return std::make_shared<PrivilegedAction>(); 8223825Ssaidi@eecs.umich.edu } 8233825Ssaidi@eecs.umich.edu goto regAccessOk; 8243825Ssaidi@eecs.umich.edu 8253825Ssaidi@eecs.umich.edu 8263824Ssaidi@eecs.umich.eduregAccessOk: 8273804Ssaidi@eecs.umich.eduhandleMmuRegAccess: 8283811Ssaidi@eecs.umich.edu DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 8298105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 8303806Ssaidi@eecs.umich.edu req->setPaddr(req->getVaddr()); 8313806Ssaidi@eecs.umich.edu return NoFault; 8323804Ssaidi@eecs.umich.edu}; 8333804Ssaidi@eecs.umich.edu 8346022Sgblack@eecs.umich.eduFault 8356023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 8366022Sgblack@eecs.umich.edu{ 8376023Snate@binkert.org if (mode == Execute) 8386022Sgblack@eecs.umich.edu return translateInst(req, tc); 8396022Sgblack@eecs.umich.edu else 8406023Snate@binkert.org return translateData(req, tc, mode == Write); 8416022Sgblack@eecs.umich.edu} 8426022Sgblack@eecs.umich.edu 8435894Sgblack@eecs.umich.eduvoid 8446022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 8456023Snate@binkert.org Translation *translation, Mode mode) 8465894Sgblack@eecs.umich.edu{ 8475894Sgblack@eecs.umich.edu assert(translation); 8486023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 8495894Sgblack@eecs.umich.edu} 8505894Sgblack@eecs.umich.edu 8518888Sgeoffrey.blake@arm.comFault 8529738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 8539738Sandreas@sandberg.pp.se{ 8549738Sandreas@sandberg.pp.se return NoFault; 8559738Sandreas@sandberg.pp.se} 8569738Sandreas@sandberg.pp.se 8579180Sandreas.hansson@arm.comCycles 8586022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 8593806Ssaidi@eecs.umich.edu{ 8603823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 8619912Sandreas@sandberg.pp.se ASI asi = (ASI)pkt->req->getArchFlags(); 8624070Ssaidi@eecs.umich.edu uint64_t temp; 8633823Ssaidi@eecs.umich.edu 8643823Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 8659912Sandreas@sandberg.pp.se (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); 8663823Ssaidi@eecs.umich.edu 86712406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 8684990Sgblack@eecs.umich.edu 8693823Ssaidi@eecs.umich.edu switch (asi) { 8703823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 8713823Ssaidi@eecs.umich.edu assert(va == 0); 8724172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 8733823Ssaidi@eecs.umich.edu break; 8743823Ssaidi@eecs.umich.edu case ASI_MMU: 8753823Ssaidi@eecs.umich.edu switch (va) { 8763823Ssaidi@eecs.umich.edu case 0x8: 8774172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); 8783823Ssaidi@eecs.umich.edu break; 8793823Ssaidi@eecs.umich.edu case 0x10: 8804172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); 8813823Ssaidi@eecs.umich.edu break; 8823823Ssaidi@eecs.umich.edu default: 8833823Ssaidi@eecs.umich.edu goto doMmuReadError; 8843823Ssaidi@eecs.umich.edu } 8853823Ssaidi@eecs.umich.edu break; 8863824Ssaidi@eecs.umich.edu case ASI_QUEUE: 8874172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 8883824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c)); 8893824Ssaidi@eecs.umich.edu break; 8903823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 8913823Ssaidi@eecs.umich.edu assert(va == 0); 8924990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps0); 8933823Ssaidi@eecs.umich.edu break; 8943823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 8953823Ssaidi@eecs.umich.edu assert(va == 0); 8964990Sgblack@eecs.umich.edu pkt->set(c0_tsb_ps1); 8973823Ssaidi@eecs.umich.edu break; 8983823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 8993823Ssaidi@eecs.umich.edu assert(va == 0); 9004990Sgblack@eecs.umich.edu pkt->set(c0_config); 9013823Ssaidi@eecs.umich.edu break; 9023823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 9033823Ssaidi@eecs.umich.edu assert(va == 0); 9044990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps0); 9053823Ssaidi@eecs.umich.edu break; 9063823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 9073823Ssaidi@eecs.umich.edu assert(va == 0); 9084990Sgblack@eecs.umich.edu pkt->set(itb->c0_tsb_ps1); 9093823Ssaidi@eecs.umich.edu break; 9103823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 9113823Ssaidi@eecs.umich.edu assert(va == 0); 9124990Sgblack@eecs.umich.edu pkt->set(itb->c0_config); 9133823Ssaidi@eecs.umich.edu break; 9143823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 9153823Ssaidi@eecs.umich.edu assert(va == 0); 9164990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps0); 9173823Ssaidi@eecs.umich.edu break; 9183823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 9193823Ssaidi@eecs.umich.edu assert(va == 0); 9204990Sgblack@eecs.umich.edu pkt->set(cx_tsb_ps1); 9213823Ssaidi@eecs.umich.edu break; 9223823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 9233823Ssaidi@eecs.umich.edu assert(va == 0); 9244990Sgblack@eecs.umich.edu pkt->set(cx_config); 9253823Ssaidi@eecs.umich.edu break; 9263823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 9273823Ssaidi@eecs.umich.edu assert(va == 0); 9284990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps0); 9293823Ssaidi@eecs.umich.edu break; 9303823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 9313823Ssaidi@eecs.umich.edu assert(va == 0); 9324990Sgblack@eecs.umich.edu pkt->set(itb->cx_tsb_ps1); 9333823Ssaidi@eecs.umich.edu break; 9343823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 9353823Ssaidi@eecs.umich.edu assert(va == 0); 9364990Sgblack@eecs.umich.edu pkt->set(itb->cx_config); 9373823Ssaidi@eecs.umich.edu break; 9383826Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 9393912Ssaidi@eecs.umich.edu pkt->set((uint64_t)0); 9403826Ssaidi@eecs.umich.edu break; 9413823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 9423823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 9434172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 9443823Ssaidi@eecs.umich.edu break; 9453826Ssaidi@eecs.umich.edu case ASI_IMMU: 9463826Ssaidi@eecs.umich.edu switch (va) { 9473833Ssaidi@eecs.umich.edu case 0x0: 9484990Sgblack@eecs.umich.edu temp = itb->tag_access; 9493833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9503833Ssaidi@eecs.umich.edu break; 9513906Ssaidi@eecs.umich.edu case 0x18: 9524990Sgblack@eecs.umich.edu pkt->set(itb->sfsr); 9533906Ssaidi@eecs.umich.edu break; 9543826Ssaidi@eecs.umich.edu case 0x30: 9554990Sgblack@eecs.umich.edu pkt->set(itb->tag_access); 9563826Ssaidi@eecs.umich.edu break; 9573826Ssaidi@eecs.umich.edu default: 9583826Ssaidi@eecs.umich.edu goto doMmuReadError; 9593826Ssaidi@eecs.umich.edu } 9603826Ssaidi@eecs.umich.edu break; 9613823Ssaidi@eecs.umich.edu case ASI_DMMU: 9623823Ssaidi@eecs.umich.edu switch (va) { 9633833Ssaidi@eecs.umich.edu case 0x0: 9644990Sgblack@eecs.umich.edu temp = tag_access; 9653833Ssaidi@eecs.umich.edu pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 9663833Ssaidi@eecs.umich.edu break; 9673906Ssaidi@eecs.umich.edu case 0x18: 9684990Sgblack@eecs.umich.edu pkt->set(sfsr); 9693906Ssaidi@eecs.umich.edu break; 9703906Ssaidi@eecs.umich.edu case 0x20: 9714990Sgblack@eecs.umich.edu pkt->set(sfar); 9723906Ssaidi@eecs.umich.edu break; 9733826Ssaidi@eecs.umich.edu case 0x30: 9744990Sgblack@eecs.umich.edu pkt->set(tag_access); 9753826Ssaidi@eecs.umich.edu break; 9763823Ssaidi@eecs.umich.edu case 0x80: 9774172Ssaidi@eecs.umich.edu pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 9783823Ssaidi@eecs.umich.edu break; 9793823Ssaidi@eecs.umich.edu default: 9803823Ssaidi@eecs.umich.edu goto doMmuReadError; 9813823Ssaidi@eecs.umich.edu } 9823823Ssaidi@eecs.umich.edu break; 9833833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS0_PTR_REG: 9844070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 9854990Sgblack@eecs.umich.edu tag_access, 9864990Sgblack@eecs.umich.edu c0_tsb_ps0, 9874990Sgblack@eecs.umich.edu c0_config, 9884990Sgblack@eecs.umich.edu cx_tsb_ps0, 9894990Sgblack@eecs.umich.edu cx_config)); 9903833Ssaidi@eecs.umich.edu break; 9913833Ssaidi@eecs.umich.edu case ASI_DMMU_TSB_PS1_PTR_REG: 9924070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 9934990Sgblack@eecs.umich.edu tag_access, 9944990Sgblack@eecs.umich.edu c0_tsb_ps1, 9954990Sgblack@eecs.umich.edu c0_config, 9964990Sgblack@eecs.umich.edu cx_tsb_ps1, 9974990Sgblack@eecs.umich.edu cx_config)); 9983833Ssaidi@eecs.umich.edu break; 9993899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS0_PTR_REG: 10004070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps0, 10014990Sgblack@eecs.umich.edu itb->tag_access, 10024990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 10034990Sgblack@eecs.umich.edu itb->c0_config, 10044990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 10054990Sgblack@eecs.umich.edu itb->cx_config)); 10063899Ssaidi@eecs.umich.edu break; 10073899Ssaidi@eecs.umich.edu case ASI_IMMU_TSB_PS1_PTR_REG: 10084070Ssaidi@eecs.umich.edu pkt->set(MakeTsbPtr(Ps1, 10094990Sgblack@eecs.umich.edu itb->tag_access, 10104990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 10114990Sgblack@eecs.umich.edu itb->c0_config, 10124990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 10134990Sgblack@eecs.umich.edu itb->cx_config)); 10143899Ssaidi@eecs.umich.edu break; 10154103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 10165646Sgblack@eecs.umich.edu { 10175646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10185646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 101911150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 10205646Sgblack@eecs.umich.edu pkt->set(interrupts->get_vec(IT_INT_VEC)); 10215646Sgblack@eecs.umich.edu } 10224103Ssaidi@eecs.umich.edu break; 10234103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_R: 10245646Sgblack@eecs.umich.edu { 10255646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 10265646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 102711150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 10285646Sgblack@eecs.umich.edu temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); 102911150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp); 10305646Sgblack@eecs.umich.edu pkt->set(temp); 10315646Sgblack@eecs.umich.edu } 10324103Ssaidi@eecs.umich.edu break; 10333823Ssaidi@eecs.umich.edu default: 10343823Ssaidi@eecs.umich.edudoMmuReadError: 10353823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 10363823Ssaidi@eecs.umich.edu (uint32_t)asi, va); 10373823Ssaidi@eecs.umich.edu } 10384870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 10399180Sandreas.hansson@arm.com return Cycles(1); 10403806Ssaidi@eecs.umich.edu} 10413806Ssaidi@eecs.umich.edu 10429180Sandreas.hansson@arm.comCycles 10436022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 10443806Ssaidi@eecs.umich.edu{ 10457518Sgblack@eecs.umich.edu uint64_t data = pkt->get<uint64_t>(); 10463823Ssaidi@eecs.umich.edu Addr va = pkt->getAddr(); 10479912Sandreas@sandberg.pp.se ASI asi = (ASI)pkt->req->getArchFlags(); 10483823Ssaidi@eecs.umich.edu 10493826Ssaidi@eecs.umich.edu Addr ta_insert; 10503826Ssaidi@eecs.umich.edu Addr va_insert; 10513826Ssaidi@eecs.umich.edu Addr ct_insert; 10523826Ssaidi@eecs.umich.edu int part_insert; 10533826Ssaidi@eecs.umich.edu int entry_insert = -1; 10543826Ssaidi@eecs.umich.edu bool real_insert; 10553863Ssaidi@eecs.umich.edu bool ignore; 10563863Ssaidi@eecs.umich.edu int part_id; 10573863Ssaidi@eecs.umich.edu int ctx_id; 10583826Ssaidi@eecs.umich.edu PageTableEntry pte; 10593826Ssaidi@eecs.umich.edu 10603825Ssaidi@eecs.umich.edu DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 10613823Ssaidi@eecs.umich.edu (uint32_t)asi, va, data); 10623823Ssaidi@eecs.umich.edu 106312406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 10644990Sgblack@eecs.umich.edu 10653823Ssaidi@eecs.umich.edu switch (asi) { 10663823Ssaidi@eecs.umich.edu case ASI_LSU_CONTROL_REG: 10673823Ssaidi@eecs.umich.edu assert(va == 0); 10684172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 10693823Ssaidi@eecs.umich.edu break; 10703823Ssaidi@eecs.umich.edu case ASI_MMU: 10713823Ssaidi@eecs.umich.edu switch (va) { 10723823Ssaidi@eecs.umich.edu case 0x8: 10734172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); 10743823Ssaidi@eecs.umich.edu break; 10753823Ssaidi@eecs.umich.edu case 0x10: 10764172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); 10773823Ssaidi@eecs.umich.edu break; 10783823Ssaidi@eecs.umich.edu default: 10793823Ssaidi@eecs.umich.edu goto doMmuWriteError; 10803823Ssaidi@eecs.umich.edu } 10813823Ssaidi@eecs.umich.edu break; 10823824Ssaidi@eecs.umich.edu case ASI_QUEUE: 10833825Ssaidi@eecs.umich.edu assert(mbits(data,13,6) == data); 10844172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 10853824Ssaidi@eecs.umich.edu (va >> 4) - 0x3c, data); 10863824Ssaidi@eecs.umich.edu break; 10873823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 10883823Ssaidi@eecs.umich.edu assert(va == 0); 10894990Sgblack@eecs.umich.edu c0_tsb_ps0 = data; 10903823Ssaidi@eecs.umich.edu break; 10913823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 10923823Ssaidi@eecs.umich.edu assert(va == 0); 10934990Sgblack@eecs.umich.edu c0_tsb_ps1 = data; 10943823Ssaidi@eecs.umich.edu break; 10953823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_ZERO_CONFIG: 10963823Ssaidi@eecs.umich.edu assert(va == 0); 10974990Sgblack@eecs.umich.edu c0_config = data; 10983823Ssaidi@eecs.umich.edu break; 10993823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 11003823Ssaidi@eecs.umich.edu assert(va == 0); 11014990Sgblack@eecs.umich.edu itb->c0_tsb_ps0 = data; 11023823Ssaidi@eecs.umich.edu break; 11033823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 11043823Ssaidi@eecs.umich.edu assert(va == 0); 11054990Sgblack@eecs.umich.edu itb->c0_tsb_ps1 = data; 11063823Ssaidi@eecs.umich.edu break; 11073823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_ZERO_CONFIG: 11083823Ssaidi@eecs.umich.edu assert(va == 0); 11094990Sgblack@eecs.umich.edu itb->c0_config = data; 11103823Ssaidi@eecs.umich.edu break; 11113823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 11123823Ssaidi@eecs.umich.edu assert(va == 0); 11134990Sgblack@eecs.umich.edu cx_tsb_ps0 = data; 11143823Ssaidi@eecs.umich.edu break; 11153823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 11163823Ssaidi@eecs.umich.edu assert(va == 0); 11174990Sgblack@eecs.umich.edu cx_tsb_ps1 = data; 11183823Ssaidi@eecs.umich.edu break; 11193823Ssaidi@eecs.umich.edu case ASI_DMMU_CTXT_NONZERO_CONFIG: 11203823Ssaidi@eecs.umich.edu assert(va == 0); 11214990Sgblack@eecs.umich.edu cx_config = data; 11223823Ssaidi@eecs.umich.edu break; 11233823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 11243823Ssaidi@eecs.umich.edu assert(va == 0); 11254990Sgblack@eecs.umich.edu itb->cx_tsb_ps0 = data; 11263823Ssaidi@eecs.umich.edu break; 11273823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 11283823Ssaidi@eecs.umich.edu assert(va == 0); 11294990Sgblack@eecs.umich.edu itb->cx_tsb_ps1 = data; 11303823Ssaidi@eecs.umich.edu break; 11313823Ssaidi@eecs.umich.edu case ASI_IMMU_CTXT_NONZERO_CONFIG: 11323823Ssaidi@eecs.umich.edu assert(va == 0); 11334990Sgblack@eecs.umich.edu itb->cx_config = data; 11343823Ssaidi@eecs.umich.edu break; 11353825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_EN_REG: 11363825Ssaidi@eecs.umich.edu case ASI_SPARC_ERROR_STATUS_REG: 11375823Ssaidi@eecs.umich.edu inform("Ignoring write to SPARC ERROR regsiter\n"); 11383825Ssaidi@eecs.umich.edu break; 11393823Ssaidi@eecs.umich.edu case ASI_HYP_SCRATCHPAD: 11403823Ssaidi@eecs.umich.edu case ASI_SCRATCHPAD: 11414172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 11423823Ssaidi@eecs.umich.edu break; 11433826Ssaidi@eecs.umich.edu case ASI_IMMU: 11443826Ssaidi@eecs.umich.edu switch (va) { 11453906Ssaidi@eecs.umich.edu case 0x18: 11464990Sgblack@eecs.umich.edu itb->sfsr = data; 11473906Ssaidi@eecs.umich.edu break; 11483826Ssaidi@eecs.umich.edu case 0x30: 11493916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 11504990Sgblack@eecs.umich.edu itb->tag_access = data; 11513826Ssaidi@eecs.umich.edu break; 11523826Ssaidi@eecs.umich.edu default: 11533826Ssaidi@eecs.umich.edu goto doMmuWriteError; 11543826Ssaidi@eecs.umich.edu } 11553826Ssaidi@eecs.umich.edu break; 11563826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_ACCESS_REG: 11573826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11583826Ssaidi@eecs.umich.edu case ASI_ITLB_DATA_IN_REG: 11593826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11604990Sgblack@eecs.umich.edu ta_insert = itb->tag_access; 11613826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11623826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11634172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11643826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11653826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11663826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 116712406Sgabeblack@google.com itb->insert(va_insert, part_insert, ct_insert, real_insert, 116812406Sgabeblack@google.com pte, entry_insert); 11693826Ssaidi@eecs.umich.edu break; 11703826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_ACCESS_REG: 11713826Ssaidi@eecs.umich.edu entry_insert = bits(va, 8,3); 11723826Ssaidi@eecs.umich.edu case ASI_DTLB_DATA_IN_REG: 11733826Ssaidi@eecs.umich.edu assert(entry_insert != -1 || mbits(va,10,9) == va); 11744990Sgblack@eecs.umich.edu ta_insert = tag_access; 11753826Ssaidi@eecs.umich.edu va_insert = mbits(ta_insert, 63,13); 11763826Ssaidi@eecs.umich.edu ct_insert = mbits(ta_insert, 12,0); 11774172Ssaidi@eecs.umich.edu part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 11783826Ssaidi@eecs.umich.edu real_insert = bits(va, 9,9); 11793826Ssaidi@eecs.umich.edu pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 11803826Ssaidi@eecs.umich.edu PageTableEntry::sun4u); 11815555Snate@binkert.org insert(va_insert, part_insert, ct_insert, real_insert, pte, 11825555Snate@binkert.org entry_insert); 11833826Ssaidi@eecs.umich.edu break; 11843863Ssaidi@eecs.umich.edu case ASI_IMMU_DEMAP: 11853863Ssaidi@eecs.umich.edu ignore = false; 11863863Ssaidi@eecs.umich.edu ctx_id = -1; 11874172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 11883863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 11893863Ssaidi@eecs.umich.edu case 0: 11904172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 11913863Ssaidi@eecs.umich.edu break; 11923863Ssaidi@eecs.umich.edu case 1: 11933863Ssaidi@eecs.umich.edu ignore = true; 11943863Ssaidi@eecs.umich.edu break; 11953863Ssaidi@eecs.umich.edu case 3: 11963863Ssaidi@eecs.umich.edu ctx_id = 0; 11973863Ssaidi@eecs.umich.edu break; 11983863Ssaidi@eecs.umich.edu default: 11993863Ssaidi@eecs.umich.edu ignore = true; 12003863Ssaidi@eecs.umich.edu } 12013863Ssaidi@eecs.umich.edu 12027741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12033863Ssaidi@eecs.umich.edu case 0: // demap page 12043863Ssaidi@eecs.umich.edu if (!ignore) 120512406Sgabeblack@google.com itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12063863Ssaidi@eecs.umich.edu break; 12077741Sgblack@eecs.umich.edu case 1: // demap context 12083863Ssaidi@eecs.umich.edu if (!ignore) 120912406Sgabeblack@google.com itb->demapContext(part_id, ctx_id); 12103863Ssaidi@eecs.umich.edu break; 12113863Ssaidi@eecs.umich.edu case 2: 121212406Sgabeblack@google.com itb->demapAll(part_id); 12133863Ssaidi@eecs.umich.edu break; 12143863Ssaidi@eecs.umich.edu default: 12153863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12163863Ssaidi@eecs.umich.edu } 12173863Ssaidi@eecs.umich.edu break; 12183823Ssaidi@eecs.umich.edu case ASI_DMMU: 12193823Ssaidi@eecs.umich.edu switch (va) { 12203906Ssaidi@eecs.umich.edu case 0x18: 12214990Sgblack@eecs.umich.edu sfsr = data; 12223906Ssaidi@eecs.umich.edu break; 12233826Ssaidi@eecs.umich.edu case 0x30: 12243916Ssaidi@eecs.umich.edu sext<59>(bits(data, 59,0)); 12254990Sgblack@eecs.umich.edu tag_access = data; 12263826Ssaidi@eecs.umich.edu break; 12273823Ssaidi@eecs.umich.edu case 0x80: 12284172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_MMU_PART_ID, data); 12293823Ssaidi@eecs.umich.edu break; 12303823Ssaidi@eecs.umich.edu default: 12313823Ssaidi@eecs.umich.edu goto doMmuWriteError; 12323823Ssaidi@eecs.umich.edu } 12333823Ssaidi@eecs.umich.edu break; 12343863Ssaidi@eecs.umich.edu case ASI_DMMU_DEMAP: 12353863Ssaidi@eecs.umich.edu ignore = false; 12363863Ssaidi@eecs.umich.edu ctx_id = -1; 12374172Ssaidi@eecs.umich.edu part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); 12383863Ssaidi@eecs.umich.edu switch (bits(va,5,4)) { 12393863Ssaidi@eecs.umich.edu case 0: 12404172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 12413863Ssaidi@eecs.umich.edu break; 12423863Ssaidi@eecs.umich.edu case 1: 12434172Ssaidi@eecs.umich.edu ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); 12443863Ssaidi@eecs.umich.edu break; 12453863Ssaidi@eecs.umich.edu case 3: 12463863Ssaidi@eecs.umich.edu ctx_id = 0; 12473863Ssaidi@eecs.umich.edu break; 12483863Ssaidi@eecs.umich.edu default: 12493863Ssaidi@eecs.umich.edu ignore = true; 12503863Ssaidi@eecs.umich.edu } 12513863Ssaidi@eecs.umich.edu 12527741Sgblack@eecs.umich.edu switch (bits(va,7,6)) { 12533863Ssaidi@eecs.umich.edu case 0: // demap page 12543863Ssaidi@eecs.umich.edu if (!ignore) 12553863Ssaidi@eecs.umich.edu demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 12563863Ssaidi@eecs.umich.edu break; 12577741Sgblack@eecs.umich.edu case 1: // demap context 12583863Ssaidi@eecs.umich.edu if (!ignore) 12593863Ssaidi@eecs.umich.edu demapContext(part_id, ctx_id); 12603863Ssaidi@eecs.umich.edu break; 12613863Ssaidi@eecs.umich.edu case 2: 12623863Ssaidi@eecs.umich.edu demapAll(part_id); 12633863Ssaidi@eecs.umich.edu break; 12643863Ssaidi@eecs.umich.edu default: 12653863Ssaidi@eecs.umich.edu panic("Invalid type for IMMU demap\n"); 12663863Ssaidi@eecs.umich.edu } 12673863Ssaidi@eecs.umich.edu break; 12684103Ssaidi@eecs.umich.edu case ASI_SWVR_INTR_RECEIVE: 12695646Sgblack@eecs.umich.edu { 12705646Sgblack@eecs.umich.edu int msb; 12715646Sgblack@eecs.umich.edu // clear all the interrupts that aren't set in the write 12725646Sgblack@eecs.umich.edu SparcISA::Interrupts * interrupts = 12735646Sgblack@eecs.umich.edu dynamic_cast<SparcISA::Interrupts *>( 127411150Smitch.hayenga@arm.com tc->getCpuPtr()->getInterruptController(0)); 12755704Snate@binkert.org while (interrupts->get_vec(IT_INT_VEC) & data) { 12765646Sgblack@eecs.umich.edu msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); 127711150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb); 12785646Sgblack@eecs.umich.edu } 12794103Ssaidi@eecs.umich.edu } 12804103Ssaidi@eecs.umich.edu break; 12814103Ssaidi@eecs.umich.edu case ASI_SWVR_UDB_INTR_W: 12824103Ssaidi@eecs.umich.edu tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 128311150Smitch.hayenga@arm.com postInterrupt(0, bits(data, 5, 0), 0); 12844103Ssaidi@eecs.umich.edu break; 12855555Snate@binkert.org default: 12863823Ssaidi@eecs.umich.edudoMmuWriteError: 12873823Ssaidi@eecs.umich.edu panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 12889912Sandreas@sandberg.pp.se (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data); 12893823Ssaidi@eecs.umich.edu } 12904870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 12919180Sandreas.hansson@arm.com return Cycles(1); 12923806Ssaidi@eecs.umich.edu} 12933806Ssaidi@eecs.umich.edu 12943804Ssaidi@eecs.umich.eduvoid 12956022Sgblack@eecs.umich.eduTLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 12964070Ssaidi@eecs.umich.edu{ 12974070Ssaidi@eecs.umich.edu uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); 129812406Sgabeblack@google.com TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); 12994070Ssaidi@eecs.umich.edu ptrs[0] = MakeTsbPtr(Ps0, tag_access, 13004990Sgblack@eecs.umich.edu c0_tsb_ps0, 13014990Sgblack@eecs.umich.edu c0_config, 13024990Sgblack@eecs.umich.edu cx_tsb_ps0, 13034990Sgblack@eecs.umich.edu cx_config); 13044070Ssaidi@eecs.umich.edu ptrs[1] = MakeTsbPtr(Ps1, tag_access, 13054990Sgblack@eecs.umich.edu c0_tsb_ps1, 13064990Sgblack@eecs.umich.edu c0_config, 13074990Sgblack@eecs.umich.edu cx_tsb_ps1, 13084990Sgblack@eecs.umich.edu cx_config); 13094070Ssaidi@eecs.umich.edu ptrs[2] = MakeTsbPtr(Ps0, tag_access, 13104990Sgblack@eecs.umich.edu itb->c0_tsb_ps0, 13114990Sgblack@eecs.umich.edu itb->c0_config, 13124990Sgblack@eecs.umich.edu itb->cx_tsb_ps0, 13134990Sgblack@eecs.umich.edu itb->cx_config); 13144070Ssaidi@eecs.umich.edu ptrs[3] = MakeTsbPtr(Ps1, tag_access, 13154990Sgblack@eecs.umich.edu itb->c0_tsb_ps1, 13164990Sgblack@eecs.umich.edu itb->c0_config, 13174990Sgblack@eecs.umich.edu itb->cx_tsb_ps1, 13184990Sgblack@eecs.umich.edu itb->cx_config); 13194070Ssaidi@eecs.umich.edu} 13204070Ssaidi@eecs.umich.edu 13214070Ssaidi@eecs.umich.eduuint64_t 13226022Sgblack@eecs.umich.eduTLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 13234070Ssaidi@eecs.umich.edu uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config) 13244070Ssaidi@eecs.umich.edu{ 13254070Ssaidi@eecs.umich.edu uint64_t tsb; 13264070Ssaidi@eecs.umich.edu uint64_t config; 13274070Ssaidi@eecs.umich.edu 13284070Ssaidi@eecs.umich.edu if (bits(tag_access, 12,0) == 0) { 13294070Ssaidi@eecs.umich.edu tsb = c0_tsb; 13304070Ssaidi@eecs.umich.edu config = c0_config; 13314070Ssaidi@eecs.umich.edu } else { 13324070Ssaidi@eecs.umich.edu tsb = cX_tsb; 13334070Ssaidi@eecs.umich.edu config = cX_config; 13344070Ssaidi@eecs.umich.edu } 13354070Ssaidi@eecs.umich.edu 13364070Ssaidi@eecs.umich.edu uint64_t ptr = mbits(tsb,63,13); 13374070Ssaidi@eecs.umich.edu bool split = bits(tsb,12,12); 13384070Ssaidi@eecs.umich.edu int tsb_size = bits(tsb,3,0); 13394070Ssaidi@eecs.umich.edu int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8); 13404070Ssaidi@eecs.umich.edu 13414070Ssaidi@eecs.umich.edu if (ps == Ps1 && split) 13424070Ssaidi@eecs.umich.edu ptr |= ULL(1) << (13 + tsb_size); 13434070Ssaidi@eecs.umich.edu ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4); 13444070Ssaidi@eecs.umich.edu 13454070Ssaidi@eecs.umich.edu return ptr; 13464070Ssaidi@eecs.umich.edu} 13474070Ssaidi@eecs.umich.edu 13484070Ssaidi@eecs.umich.eduvoid 134910905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 13503804Ssaidi@eecs.umich.edu{ 13514000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(size); 13524000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(usedEntries); 13534000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(lastReplaced); 13544000Ssaidi@eecs.umich.edu 13554000Ssaidi@eecs.umich.edu // convert the pointer based free list into an index based one 135610905Sandreas.sandberg@arm.com std::vector<int> free_list; 135710905Sandreas.sandberg@arm.com for (const TlbEntry *entry : freeList) 135810905Sandreas.sandberg@arm.com free_list.push_back(entry - tlb); 135910905Sandreas.sandberg@arm.com 136010905Sandreas.sandberg@arm.com SERIALIZE_CONTAINER(free_list); 13614000Ssaidi@eecs.umich.edu 13624990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps0); 13634990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_tsb_ps1); 13644990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(c0_config); 13654990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps0); 13664990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_tsb_ps1); 13674990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cx_config); 13684990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(sfsr); 13694990Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tag_access); 137012544Skhalique913@gmail.com SERIALIZE_SCALAR(sfar); 13715276Ssaidi@eecs.umich.edu 13725276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 137310905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 137410905Sandreas.sandberg@arm.com tlb[x].serialize(cp); 13755276Ssaidi@eecs.umich.edu } 13763804Ssaidi@eecs.umich.edu} 13773804Ssaidi@eecs.umich.edu 13783804Ssaidi@eecs.umich.eduvoid 137910905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 13803804Ssaidi@eecs.umich.edu{ 13814000Ssaidi@eecs.umich.edu int oldSize; 13824000Ssaidi@eecs.umich.edu 138310905Sandreas.sandberg@arm.com paramIn(cp, "size", oldSize); 13844000Ssaidi@eecs.umich.edu if (oldSize != size) 13854000Ssaidi@eecs.umich.edu panic("Don't support unserializing different sized TLBs\n"); 13864000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(usedEntries); 13874000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(lastReplaced); 13884000Ssaidi@eecs.umich.edu 138910905Sandreas.sandberg@arm.com std::vector<int> free_list; 139010905Sandreas.sandberg@arm.com UNSERIALIZE_CONTAINER(free_list); 13914000Ssaidi@eecs.umich.edu freeList.clear(); 139210905Sandreas.sandberg@arm.com for (int idx : free_list) 139310905Sandreas.sandberg@arm.com freeList.push_back(&tlb[idx]); 13944000Ssaidi@eecs.umich.edu 13954990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps0); 13964990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_tsb_ps1); 13974990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(c0_config); 13984990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps0); 13994990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_tsb_ps1); 14004990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cx_config); 14014990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfsr); 14024990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tag_access); 14035276Ssaidi@eecs.umich.edu 14045276Ssaidi@eecs.umich.edu lookupTable.clear(); 14055276Ssaidi@eecs.umich.edu for (int x = 0; x < size; x++) { 140610905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", x)); 140710905Sandreas.sandberg@arm.com tlb[x].unserialize(cp); 14085276Ssaidi@eecs.umich.edu if (tlb[x].valid) 14095276Ssaidi@eecs.umich.edu lookupTable.insert(tlb[x].range, &tlb[x]); 14105276Ssaidi@eecs.umich.edu 14115276Ssaidi@eecs.umich.edu } 14124990Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(sfar); 14133804Ssaidi@eecs.umich.edu} 14143804Ssaidi@eecs.umich.edu 14157811Ssteve.reinhardt@amd.com} // namespace SparcISA 14164088Sbinkertn@umich.edu 14176022Sgblack@eecs.umich.eduSparcISA::TLB * 14186022Sgblack@eecs.umich.eduSparcTLBParams::create() 14193804Ssaidi@eecs.umich.edu{ 14206022Sgblack@eecs.umich.edu return new SparcISA::TLB(this); 14213804Ssaidi@eecs.umich.edu} 1422