registers.hh revision 13583:f7482392b097
16019Shines@cs.fsu.edu/* 212528Schuan.zhu@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 37093Sgblack@eecs.umich.edu * All rights reserved. 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Gabe Black 296019Shines@cs.fsu.edu * Ali Saidi 306019Shines@cs.fsu.edu */ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#ifndef __ARCH_SPARC_REGISTERS_HH__ 336019Shines@cs.fsu.edu#define __ARCH_SPARC_REGISTERS_HH__ 346019Shines@cs.fsu.edu 356019Shines@cs.fsu.edu#include "arch/generic/vec_reg.hh" 366019Shines@cs.fsu.edu#include "arch/sparc/generated/max_inst_regs.hh" 376019Shines@cs.fsu.edu#include "arch/sparc/miscregs.hh" 386019Shines@cs.fsu.edu#include "arch/sparc/sparc_traits.hh" 396019Shines@cs.fsu.edu#include "base/types.hh" 407399SAli.Saidi@ARM.com 417399SAli.Saidi@ARM.comnamespace SparcISA 426019Shines@cs.fsu.edu{ 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.eduusing SparcISAInst::MaxInstSrcRegs; 4510873Sandreas.sandberg@arm.comusing SparcISAInst::MaxInstDestRegs; 4610873Sandreas.sandberg@arm.comusing SparcISAInst::MaxMiscDestRegs; 4710474Sandreas.hansson@arm.com 486019Shines@cs.fsu.edu// dummy typedef since we don't have CC regs 496019Shines@cs.fsu.edutypedef uint8_t CCReg; 506019Shines@cs.fsu.edu 516116Snate@binkert.org// dummy typedefs since we don't have vector regs 526019Shines@cs.fsu.educonstexpr unsigned NumVecElemPerVecReg = 2; 5311793Sbrandon.potter@amd.comusing VecElem = uint32_t; 5411793Sbrandon.potter@amd.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 558782Sgblack@eecs.umich.eduusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 568756Sgblack@eecs.umich.eduusing VecRegContainer = VecReg::Container; 576019Shines@cs.fsu.edu// This has to be one to prevent warnings that are treated as errors 5812005Sandreas.sandberg@arm.comconstexpr unsigned NumVecRegs = 1; 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.edu// semantically meaningful register indices 616019Shines@cs.fsu.educonst int ZeroReg = 0; // architecturally meaningful 6210024Sdam.sunwoo@arm.com// the rest of these depend on the ABI 636019Shines@cs.fsu.educonst int ReturnAddressReg = 31; // post call, precall is 15 648232Snate@binkert.orgconst int ReturnValueReg = 8; // Post return, 24 is pre-return. 658232Snate@binkert.orgconst int StackPointerReg = 14; 668232Snate@binkert.orgconst int FramePointerReg = 30; 676116Snate@binkert.org 6811608Snikos.nikoleris@arm.com// Some OS syscall use a second register (o1) to return a second value 696116Snate@binkert.orgconst int SyscallPseudoReturnReg = 9; 708756Sgblack@eecs.umich.edu 716019Shines@cs.fsu.educonst int NumIntArchRegs = 32; 726019Shines@cs.fsu.educonst int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 736019Shines@cs.fsu.educonst int NumCCRegs = 0; 746019Shines@cs.fsu.edu 756019Shines@cs.fsu.educonst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 7610037SARM gem5 Developers 7710037SARM gem5 Developers} // namespace SparcISA 7813374Sanouk.vanlaer@arm.com 7910418Sandreas.hansson@arm.com#endif 8011395Sandreas.sandberg@arm.com