registers.hh revision 12109:f29e9c5418aa 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_REGISTERS_HH__
33#define __ARCH_SPARC_REGISTERS_HH__
34
35#include "arch/generic/vec_reg.hh"
36#include "arch/sparc/generated/max_inst_regs.hh"
37#include "arch/sparc/miscregs.hh"
38#include "arch/sparc/sparc_traits.hh"
39#include "base/types.hh"
40
41namespace SparcISA
42{
43
44using SparcISAInst::MaxInstSrcRegs;
45using SparcISAInst::MaxInstDestRegs;
46using SparcISAInst::MaxMiscDestRegs;
47
48typedef uint64_t IntReg;
49typedef uint64_t MiscReg;
50typedef float FloatReg;
51typedef uint32_t FloatRegBits;
52
53// dummy typedef since we don't have CC regs
54typedef uint8_t CCReg;
55
56// dummy typedefs since we don't have vector regs
57constexpr unsigned NumVecElemPerVecReg = 2;
58using VecElem = uint32_t;
59using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
60using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
61using VecRegContainer = VecReg::Container;
62// This has to be one to prevent warnings that are treated as errors
63constexpr unsigned NumVecRegs = 1;
64
65typedef union
66{
67    IntReg intReg;
68    FloatReg fpreg;
69    MiscReg ctrlreg;
70} AnyReg;
71
72// semantically meaningful register indices
73const int ZeroReg = 0;      // architecturally meaningful
74// the rest of these depend on the ABI
75const int ReturnAddressReg = 31; // post call, precall is 15
76const int ReturnValueReg = 8;  // Post return, 24 is pre-return.
77const int StackPointerReg = 14;
78const int FramePointerReg = 30;
79
80// Some OS syscall use a second register (o1) to return a second value
81const int SyscallPseudoReturnReg = 9;
82
83const int NumIntArchRegs = 32;
84const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
85const int NumCCRegs = 0;
86
87const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
88
89} // namespace SparcISA
90
91#endif
92