registers.hh revision 9917
12459SN/A/*
22459SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32459SN/A * All rights reserved.
42459SN/A *
52459SN/A * Redistribution and use in source and binary forms, with or without
62459SN/A * modification, are permitted provided that the following conditions are
72459SN/A * met: redistributions of source code must retain the above copyright
82459SN/A * notice, this list of conditions and the following disclaimer;
92459SN/A * redistributions in binary form must reproduce the above copyright
102459SN/A * notice, this list of conditions and the following disclaimer in the
112459SN/A * documentation and/or other materials provided with the distribution;
122459SN/A * neither the name of the copyright holders nor the names of its
132459SN/A * contributors may be used to endorse or promote products derived from
142459SN/A * this software without specific prior written permission.
152459SN/A *
162459SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172459SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182459SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192459SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202459SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212459SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222459SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232459SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242459SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252459SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262459SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Gabe Black
292665SN/A *          Ali Saidi
302459SN/A */
312459SN/A
326329Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_REGISTERS_HH__
336329Sgblack@eecs.umich.edu#define __ARCH_SPARC_REGISTERS_HH__
342459SN/A
358961Sgblack@eecs.umich.edu#include "arch/sparc/generated/max_inst_regs.hh"
366329Sgblack@eecs.umich.edu#include "arch/sparc/miscregs.hh"
376320SN/A#include "arch/sparc/sparc_traits.hh"
386329Sgblack@eecs.umich.edu#include "base/types.hh"
392459SN/A
402459SN/Anamespace SparcISA
412459SN/A{
426329Sgblack@eecs.umich.edu
437741Sgblack@eecs.umich.eduusing SparcISAInst::MaxInstSrcRegs;
447741Sgblack@eecs.umich.eduusing SparcISAInst::MaxInstDestRegs;
459046SAli.Saidi@ARM.comusing SparcISAInst::MaxMiscDestRegs;
466329Sgblack@eecs.umich.edu
477741Sgblack@eecs.umich.edutypedef uint64_t IntReg;
487741Sgblack@eecs.umich.edutypedef uint64_t MiscReg;
497741Sgblack@eecs.umich.edutypedef float FloatReg;
507741Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits;
517741Sgblack@eecs.umich.edutypedef union
527741Sgblack@eecs.umich.edu{
537741Sgblack@eecs.umich.edu    IntReg intReg;
547741Sgblack@eecs.umich.edu    FloatReg fpreg;
557741Sgblack@eecs.umich.edu    MiscReg ctrlreg;
567741Sgblack@eecs.umich.edu} AnyReg;
576329Sgblack@eecs.umich.edu
587741Sgblack@eecs.umich.edutypedef uint16_t RegIndex;
596329Sgblack@eecs.umich.edu
607741Sgblack@eecs.umich.edu// semantically meaningful register indices
617741Sgblack@eecs.umich.educonst int ZeroReg = 0;      // architecturally meaningful
627741Sgblack@eecs.umich.edu// the rest of these depend on the ABI
637741Sgblack@eecs.umich.educonst int ReturnAddressReg = 31; // post call, precall is 15
647741Sgblack@eecs.umich.educonst int ReturnValueReg = 8;  // Post return, 24 is pre-return.
657741Sgblack@eecs.umich.educonst int StackPointerReg = 14;
667741Sgblack@eecs.umich.educonst int FramePointerReg = 30;
676329Sgblack@eecs.umich.edu
687741Sgblack@eecs.umich.edu// Some OS syscall use a second register (o1) to return a second value
697741Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = 9;
707741Sgblack@eecs.umich.edu
717741Sgblack@eecs.umich.educonst int NumIntArchRegs = 32;
727741Sgblack@eecs.umich.educonst int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
736320SN/A
748342Sksewell@umich.educonst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
758342Sksewell@umich.edu
769917Ssteve.reinhardt@amd.com// These enumerate all the registers for dependence tracking.
779917Ssteve.reinhardt@amd.comenum DependenceTags {
789917Ssteve.reinhardt@amd.com    FP_Base_DepTag = NumIntRegs,
799917Ssteve.reinhardt@amd.com    Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
809917Ssteve.reinhardt@amd.com    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
819917Ssteve.reinhardt@amd.com};
829917Ssteve.reinhardt@amd.com
832459SN/A} // namespace SparcISA
842459SN/A
852459SN/A#endif
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