registers.hh revision 12109
12459SN/A/* 22459SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32459SN/A * All rights reserved. 42459SN/A * 52459SN/A * Redistribution and use in source and binary forms, with or without 62459SN/A * modification, are permitted provided that the following conditions are 72459SN/A * met: redistributions of source code must retain the above copyright 82459SN/A * notice, this list of conditions and the following disclaimer; 92459SN/A * redistributions in binary form must reproduce the above copyright 102459SN/A * notice, this list of conditions and the following disclaimer in the 112459SN/A * documentation and/or other materials provided with the distribution; 122459SN/A * neither the name of the copyright holders nor the names of its 132459SN/A * contributors may be used to endorse or promote products derived from 142459SN/A * this software without specific prior written permission. 152459SN/A * 162459SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172459SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182459SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192459SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202459SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212459SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222459SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232459SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242459SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252459SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262459SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Gabe Black 292665SN/A * Ali Saidi 302459SN/A */ 312459SN/A 326329Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_REGISTERS_HH__ 336329Sgblack@eecs.umich.edu#define __ARCH_SPARC_REGISTERS_HH__ 342459SN/A 3512109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh" 368961Sgblack@eecs.umich.edu#include "arch/sparc/generated/max_inst_regs.hh" 376329Sgblack@eecs.umich.edu#include "arch/sparc/miscregs.hh" 386320SN/A#include "arch/sparc/sparc_traits.hh" 396329Sgblack@eecs.umich.edu#include "base/types.hh" 402459SN/A 412459SN/Anamespace SparcISA 422459SN/A{ 436329Sgblack@eecs.umich.edu 447741Sgblack@eecs.umich.eduusing SparcISAInst::MaxInstSrcRegs; 457741Sgblack@eecs.umich.eduusing SparcISAInst::MaxInstDestRegs; 469046SAli.Saidi@ARM.comusing SparcISAInst::MaxMiscDestRegs; 476329Sgblack@eecs.umich.edu 487741Sgblack@eecs.umich.edutypedef uint64_t IntReg; 497741Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 507741Sgblack@eecs.umich.edutypedef float FloatReg; 517741Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits; 529920Syasuko.eckert@amd.com 539920Syasuko.eckert@amd.com// dummy typedef since we don't have CC regs 549920Syasuko.eckert@amd.comtypedef uint8_t CCReg; 559920Syasuko.eckert@amd.com 5612109SRekai.GonzalezAlberquilla@arm.com// dummy typedefs since we don't have vector regs 5712109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecElemPerVecReg = 2; 5812109SRekai.GonzalezAlberquilla@arm.comusing VecElem = uint32_t; 5912109SRekai.GonzalezAlberquilla@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 6012109SRekai.GonzalezAlberquilla@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 6112109SRekai.GonzalezAlberquilla@arm.comusing VecRegContainer = VecReg::Container; 6212109SRekai.GonzalezAlberquilla@arm.com// This has to be one to prevent warnings that are treated as errors 6312109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecRegs = 1; 6412109SRekai.GonzalezAlberquilla@arm.com 657741Sgblack@eecs.umich.edutypedef union 667741Sgblack@eecs.umich.edu{ 677741Sgblack@eecs.umich.edu IntReg intReg; 687741Sgblack@eecs.umich.edu FloatReg fpreg; 697741Sgblack@eecs.umich.edu MiscReg ctrlreg; 707741Sgblack@eecs.umich.edu} AnyReg; 716329Sgblack@eecs.umich.edu 727741Sgblack@eecs.umich.edu// semantically meaningful register indices 737741Sgblack@eecs.umich.educonst int ZeroReg = 0; // architecturally meaningful 747741Sgblack@eecs.umich.edu// the rest of these depend on the ABI 757741Sgblack@eecs.umich.educonst int ReturnAddressReg = 31; // post call, precall is 15 767741Sgblack@eecs.umich.educonst int ReturnValueReg = 8; // Post return, 24 is pre-return. 777741Sgblack@eecs.umich.educonst int StackPointerReg = 14; 787741Sgblack@eecs.umich.educonst int FramePointerReg = 30; 796329Sgblack@eecs.umich.edu 807741Sgblack@eecs.umich.edu// Some OS syscall use a second register (o1) to return a second value 817741Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = 9; 827741Sgblack@eecs.umich.edu 837741Sgblack@eecs.umich.educonst int NumIntArchRegs = 32; 847741Sgblack@eecs.umich.educonst int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; 859920Syasuko.eckert@amd.comconst int NumCCRegs = 0; 866320SN/A 878342Sksewell@umich.educonst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 888342Sksewell@umich.edu 892459SN/A} // namespace SparcISA 902459SN/A 912459SN/A#endif 92