process.hh revision 5154
12158SN/A/*
22158SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan
32158SN/A * All rights reserved.
42158SN/A *
52158SN/A * Redistribution and use in source and binary forms, with or without
62158SN/A * modification, are permitted provided that the following conditions are
72158SN/A * met: redistributions of source code must retain the above copyright
82158SN/A * notice, this list of conditions and the following disclaimer;
92158SN/A * redistributions in binary form must reproduce the above copyright
102158SN/A * notice, this list of conditions and the following disclaimer in the
112158SN/A * documentation and/or other materials provided with the distribution;
122158SN/A * neither the name of the copyright holders nor the names of its
132158SN/A * contributors may be used to endorse or promote products derived from
142158SN/A * this software without specific prior written permission.
152158SN/A *
162158SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172158SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182158SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192158SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202158SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212158SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222158SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232158SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242158SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252158SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262158SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292760Sbinkertn@umich.edu *          Ali Saidi
302158SN/A */
312158SN/A
322158SN/A#ifndef __SPARC_PROCESS_HH__
332158SN/A#define __SPARC_PROCESS_HH__
342158SN/A
352158SN/A#include <string>
362158SN/A#include <vector>
372158SN/A#include "sim/process.hh"
382158SN/A
392158SN/Aclass ObjectFile;
402158SN/Aclass System;
412158SN/A
422158SN/Aclass SparcLiveProcess : public LiveProcess
432158SN/A{
442158SN/A  protected:
452158SN/A
462158SN/A    //The locations of the fill and spill handlers
472158SN/A    Addr fillStart, spillStart;
482158SN/A
492158SN/A    SparcLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
502158SN/A
512158SN/A  public:
522158SN/A
532158SN/A    //Handles traps which request services from the operating system
542158SN/A    virtual void handleTrap(int trapNum, ThreadContext *tc);
552158SN/A
562158SN/A    Addr readFillStart()
572158SN/A    { return fillStart; }
582158SN/A
592158SN/A    Addr readSpillStart()
602158SN/A    { return spillStart; }
612158SN/A
622158SN/A    virtual void flushWindows(ThreadContext *tc) = 0;
632158SN/A};
642158SN/A
652158SN/Astruct M5_32_auxv_t
662158SN/A{
672158SN/A    int32_t a_type;
682158SN/A    union {
692158SN/A        int32_t a_val;
702158SN/A        int32_t a_ptr;
712158SN/A        int32_t a_fcn;
722158SN/A    };
732158SN/A
742158SN/A    M5_32_auxv_t()
752158SN/A    {}
762158SN/A
772158SN/A    M5_32_auxv_t(int32_t type, int32_t val);
782158SN/A};
792158SN/A
802158SN/Aclass Sparc32LiveProcess : public SparcLiveProcess
812158SN/A{
822158SN/A  protected:
832158SN/A
842158SN/A    std::vector<M5_32_auxv_t> auxv;
852158SN/A
862158SN/A    Sparc32LiveProcess(LiveProcessParams * params, ObjectFile *objFile) :
872158SN/A            SparcLiveProcess(params, objFile)
882158SN/A    {
892158SN/A        // Set up stack. On SPARC Linux, stack goes from the top of memory
902158SN/A        // downward, less the hole for the kernel address space.
912158SN/A        stack_base = (Addr)0xf0000000ULL;
922158SN/A
932158SN/A        // Set up region for mmaps.
942989Ssaidi@eecs.umich.edu        mmap_start = mmap_end = 0x70000000;
952158SN/A    }
962158SN/A
972158SN/A    void startup();
982158SN/A
992158SN/A  public:
1002158SN/A
1012989Ssaidi@eecs.umich.edu    void argsInit(int intSize, int pageSize);
1022158SN/A
1032158SN/A    void flushWindows(ThreadContext *tc);
1042158SN/A};
1052158SN/A
1062158SN/Astruct M5_64_auxv_t
1072158SN/A{
1082158SN/A    int64_t a_type;
1092158SN/A    union {
1102158SN/A        int64_t a_val;
1112158SN/A        int64_t a_ptr;
112        int64_t a_fcn;
113    };
114
115    M5_64_auxv_t()
116    {}
117
118    M5_64_auxv_t(int64_t type, int64_t val);
119};
120
121class Sparc64LiveProcess : public SparcLiveProcess
122{
123  protected:
124
125    static const Addr StackBias = 2047;
126
127    std::vector<M5_64_auxv_t> auxv;
128
129    Sparc64LiveProcess(LiveProcessParams * params, ObjectFile *objFile) :
130            SparcLiveProcess(params, objFile)
131    {
132        // Set up stack. On SPARC Linux, stack goes from the top of memory
133        // downward, less the hole for the kernel address space.
134        stack_base = (Addr)0x80000000000ULL;
135
136        // Set up region for mmaps.  Tru64 seems to start just above 0 and
137        // grow up from there.
138        mmap_start = mmap_end = 0xfffff80000000000ULL;
139    }
140
141    void startup();
142
143  public:
144
145    void argsInit(int intSize, int pageSize);
146
147    void flushWindows(ThreadContext *tc);
148};
149
150#endif // __SPARC_PROCESS_HH__
151