process.cc revision 8706
1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/asi.hh" 33#include "arch/sparc/handlers.hh" 34#include "arch/sparc/isa_traits.hh" 35#include "arch/sparc/process.hh" 36#include "arch/sparc/registers.hh" 37#include "arch/sparc/types.hh" 38#include "base/loader/elf_object.hh" 39#include "base/loader/object_file.hh" 40#include "base/misc.hh" 41#include "cpu/thread_context.hh" 42#include "debug/Stack.hh" 43#include "mem/page_table.hh" 44#include "sim/process_impl.hh" 45#include "sim/system.hh" 46 47using namespace std; 48using namespace SparcISA; 49 50static const int FirstArgumentReg = 8; 51 52 53SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 54 ObjectFile *objFile, Addr _StackBias) 55 : LiveProcess(params, objFile), StackBias(_StackBias) 56{ 57 58 // XXX all the below need to be updated for SPARC - Ali 59 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 60 brk_point = roundUp(brk_point, VMPageSize); 61 62 // Set pointer for next thread stack. Reserve 8M for main stack. 63 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 64 65 // Initialize these to 0s 66 fillStart = 0; 67 spillStart = 0; 68} 69 70void 71SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 72{ 73 PCState pc = tc->pcState(); 74 switch (trapNum) { 75 case 0x01: // Software breakpoint 76 warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 77 break; 78 case 0x02: // Division by zero 79 warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 80 break; 81 case 0x03: // Flush window trap 82 flushWindows(tc); 83 break; 84 case 0x04: // Clean windows 85 warn("Ignoring process request for clean register " 86 "windows at pc %#x.\n", pc.pc()); 87 break; 88 case 0x05: // Range check 89 warn("Software signaled a range check at pc %#x.\n", pc.pc()); 90 break; 91 case 0x06: // Fix alignment 92 warn("Ignoring process request for os assisted unaligned accesses " 93 "at pc %#x.\n", pc.pc()); 94 break; 95 case 0x07: // Integer overflow 96 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 97 break; 98 case 0x32: // Get integer condition codes 99 warn("Ignoring process request to get the integer condition codes " 100 "at pc %#x.\n", pc.pc()); 101 break; 102 case 0x33: // Set integer condition codes 103 warn("Ignoring process request to set the integer condition codes " 104 "at pc %#x.\n", pc.pc()); 105 break; 106 default: 107 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 108 } 109} 110 111void 112SparcLiveProcess::initState() 113{ 114 LiveProcess::initState(); 115 116 ThreadContext *tc = system->getThreadContext(contextIds[0]); 117 // From the SPARC ABI 118 119 // Setup default FP state 120 tc->setMiscRegNoEffect(MISCREG_FSR, 0); 121 122 tc->setMiscRegNoEffect(MISCREG_TICK, 0); 123 124 /* 125 * Register window management registers 126 */ 127 128 // No windows contain info from other programs 129 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 130 tc->setIntReg(NumIntArchRegs + 6, 0); 131 // There are no windows to pop 132 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 133 tc->setIntReg(NumIntArchRegs + 4, 0); 134 // All windows are available to save into 135 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 136 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 137 // All windows are "clean" 138 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 139 tc->setIntReg(NumIntArchRegs + 5, NWindows); 140 // Start with register window 0 141 tc->setMiscReg(MISCREG_CWP, 0); 142 // Always use spill and fill traps 0 143 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 144 tc->setIntReg(NumIntArchRegs + 7, 0); 145 // Set the trap level to 0 146 tc->setMiscRegNoEffect(MISCREG_TL, 0); 147 // Set the ASI register to something fixed 148 tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); 149 150 /* 151 * T1 specific registers 152 */ 153 // Turn on the icache, dcache, dtb translation, and itb translation. 154 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 155} 156 157void 158Sparc32LiveProcess::initState() 159{ 160 SparcLiveProcess::initState(); 161 162 ThreadContext *tc = system->getThreadContext(contextIds[0]); 163 // The process runs in user mode with 32 bit addresses 164 tc->setMiscReg(MISCREG_PSTATE, 0x0a); 165 166 argsInit(32 / 8, VMPageSize); 167} 168 169void 170Sparc64LiveProcess::initState() 171{ 172 SparcLiveProcess::initState(); 173 174 ThreadContext *tc = system->getThreadContext(contextIds[0]); 175 // The process runs in user mode 176 tc->setMiscReg(MISCREG_PSTATE, 0x02); 177 178 argsInit(sizeof(IntReg), VMPageSize); 179} 180 181template<class IntType> 182void 183SparcLiveProcess::argsInit(int pageSize) 184{ 185 int intSize = sizeof(IntType); 186 187 typedef AuxVector<IntType> auxv_t; 188 189 std::vector<auxv_t> auxv; 190 191 string filename; 192 if (argv.size() < 1) 193 filename = ""; 194 else 195 filename = argv[0]; 196 197 // Even for a 32 bit process, the ABI says we still need to 198 // maintain double word alignment of the stack pointer. 199 uint64_t align = 16; 200 201 // load object file into target memory 202 objFile->loadSections(initVirtMem); 203 204 enum hardwareCaps 205 { 206 M5_HWCAP_SPARC_FLUSH = 1, 207 M5_HWCAP_SPARC_STBAR = 2, 208 M5_HWCAP_SPARC_SWAP = 4, 209 M5_HWCAP_SPARC_MULDIV = 8, 210 M5_HWCAP_SPARC_V9 = 16, 211 // This one should technically only be set 212 // if there is a cheetah or cheetah_plus tlb, 213 // but we'll use it all the time 214 M5_HWCAP_SPARC_ULTRA3 = 32 215 }; 216 217 const int64_t hwcap = 218 M5_HWCAP_SPARC_FLUSH | 219 M5_HWCAP_SPARC_STBAR | 220 M5_HWCAP_SPARC_SWAP | 221 M5_HWCAP_SPARC_MULDIV | 222 M5_HWCAP_SPARC_V9 | 223 M5_HWCAP_SPARC_ULTRA3; 224 225 // Setup the auxilliary vectors. These will already have endian conversion. 226 // Auxilliary vectors are loaded only for elf formatted executables. 227 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 228 if (elfObject) { 229 // Bits which describe the system hardware capabilities 230 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 231 // The system page size 232 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize)); 233 // Defined to be 100 in the kernel source. 234 // Frequency at which times() increments 235 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 236 // For statically linked executables, this is the virtual address of the 237 // program header tables if they appear in the executable image 238 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 239 // This is the size of a program header entry from the elf file. 240 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 241 // This is the number of program headers from the original elf file. 242 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 243 // This is the address of the elf "interpreter", It should be set 244 // to 0 for regular executables. It should be something else 245 // (not sure what) for dynamic libraries. 246 auxv.push_back(auxv_t(M5_AT_BASE, 0)); 247 // This is hardwired to 0 in the elf loading code in the kernel 248 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 249 // The entry point to the program 250 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 251 // Different user and group IDs 252 auxv.push_back(auxv_t(M5_AT_UID, uid())); 253 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 254 auxv.push_back(auxv_t(M5_AT_GID, gid())); 255 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 256 // Whether to enable "secure mode" in the executable 257 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 258 } 259 260 // Figure out how big the initial stack needs to be 261 262 // The unaccounted for 8 byte 0 at the top of the stack 263 int sentry_size = 8; 264 265 // This is the name of the file which is present on the initial stack 266 // It's purpose is to let the user space linker examine the original file. 267 int file_name_size = filename.size() + 1; 268 269 int env_data_size = 0; 270 for (int i = 0; i < envp.size(); ++i) { 271 env_data_size += envp[i].size() + 1; 272 } 273 int arg_data_size = 0; 274 for (int i = 0; i < argv.size(); ++i) { 275 arg_data_size += argv[i].size() + 1; 276 } 277 278 // The info_block. 279 int base_info_block_size = 280 sentry_size + file_name_size + env_data_size + arg_data_size; 281 282 int info_block_size = roundUp(base_info_block_size, align); 283 284 int info_block_padding = info_block_size - base_info_block_size; 285 286 // Each auxilliary vector is two words 287 int aux_array_size = intSize * 2 * (auxv.size() + 1); 288 289 int envp_array_size = intSize * (envp.size() + 1); 290 int argv_array_size = intSize * (argv.size() + 1); 291 292 int argc_size = intSize; 293 int window_save_size = intSize * 16; 294 295 // Figure out the size of the contents of the actual initial frame 296 int frame_size = 297 aux_array_size + 298 envp_array_size + 299 argv_array_size + 300 argc_size + 301 window_save_size; 302 303 // There needs to be padding after the auxiliary vector data so that the 304 // very bottom of the stack is aligned properly. 305 int aligned_partial_size = roundUp(frame_size, align); 306 int aux_padding = aligned_partial_size - frame_size; 307 308 int space_needed = 309 info_block_size + 310 aux_padding + 311 frame_size; 312 313 stack_min = stack_base - space_needed; 314 stack_min = roundDown(stack_min, align); 315 stack_size = stack_base - stack_min; 316 317 // Allocate space for the stack 318 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 319 320 // map out initial stack contents 321 IntType sentry_base = stack_base - sentry_size; 322 IntType file_name_base = sentry_base - file_name_size; 323 IntType env_data_base = file_name_base - env_data_size; 324 IntType arg_data_base = env_data_base - arg_data_size; 325 IntType auxv_array_base = arg_data_base - 326 info_block_padding - aux_array_size - aux_padding; 327 IntType envp_array_base = auxv_array_base - envp_array_size; 328 IntType argv_array_base = envp_array_base - argv_array_size; 329 IntType argc_base = argv_array_base - argc_size; 330#if TRACING_ON 331 IntType window_save_base = argc_base - window_save_size; 332#endif 333 334 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 335 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 336 DPRINTF(Stack, "filename = %s\n", filename); 337 DPRINTF(Stack, "%#x - file name\n", file_name_base); 338 DPRINTF(Stack, "%#x - env data\n", env_data_base); 339 DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 340 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 341 DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 342 DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 343 DPRINTF(Stack, "%#x - argc \n", argc_base); 344 DPRINTF(Stack, "%#x - window save\n", window_save_base); 345 DPRINTF(Stack, "%#x - stack min\n", stack_min); 346 347 assert(window_save_base == stack_min); 348 349 // write contents to stack 350 351 // figure out argc 352 IntType argc = argv.size(); 353 IntType guestArgc = SparcISA::htog(argc); 354 355 // Write out the sentry void * 356 uint64_t sentry_NULL = 0; 357 initVirtMem->writeBlob(sentry_base, 358 (uint8_t*)&sentry_NULL, sentry_size); 359 360 // Write the file name 361 initVirtMem->writeString(file_name_base, filename.c_str()); 362 363 // Copy the aux stuff 364 for (int x = 0; x < auxv.size(); x++) { 365 initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 366 (uint8_t*)&(auxv[x].a_type), intSize); 367 initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 368 (uint8_t*)&(auxv[x].a_val), intSize); 369 } 370 371 // Write out the terminating zeroed auxilliary vector 372 const IntType zero = 0; 373 initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 374 (uint8_t*)&zero, intSize); 375 initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 376 (uint8_t*)&zero, intSize); 377 378 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 379 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 380 381 initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 382 383 // Set up space for the trap handlers into the processes address space. 384 // Since the stack grows down and there is reserved address space abov 385 // it, we can put stuff above it and stay out of the way. 386 fillStart = stack_base; 387 spillStart = fillStart + sizeof(MachInst) * numFillInsts; 388 389 ThreadContext *tc = system->getThreadContext(contextIds[0]); 390 // Set up the thread context to start running the process 391 // assert(NumArgumentRegs >= 2); 392 // tc->setIntReg(ArgumentReg[0], argc); 393 // tc->setIntReg(ArgumentReg[1], argv_array_base); 394 tc->setIntReg(StackPointerReg, stack_min - StackBias); 395 396 // %g1 is a pointer to a function that should be run at exit. Since we 397 // don't have anything like that, it should be set to 0. 398 tc->setIntReg(1, 0); 399 400 tc->pcState(objFile->entryPoint()); 401 402 // Align the "stack_min" to a page boundary. 403 stack_min = roundDown(stack_min, pageSize); 404 405// num_processes++; 406} 407 408void 409Sparc64LiveProcess::argsInit(int intSize, int pageSize) 410{ 411 SparcLiveProcess::argsInit<uint64_t>(pageSize); 412 413 // Stuff the trap handlers into the process address space 414 initVirtMem->writeBlob(fillStart, 415 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 416 initVirtMem->writeBlob(spillStart, 417 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 418} 419 420void 421Sparc32LiveProcess::argsInit(int intSize, int pageSize) 422{ 423 SparcLiveProcess::argsInit<uint32_t>(pageSize); 424 425 // Stuff the trap handlers into the process address space 426 initVirtMem->writeBlob(fillStart, 427 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 428 initVirtMem->writeBlob(spillStart, 429 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 430} 431 432void Sparc32LiveProcess::flushWindows(ThreadContext *tc) 433{ 434 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 435 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 436 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 437 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 438 MiscReg origCWP = CWP; 439 CWP = (CWP + Cansave + 2) % NWindows; 440 while (NWindows - 2 - Cansave != 0) { 441 if (Otherwin) { 442 panic("Otherwin non-zero.\n"); 443 } else { 444 tc->setMiscReg(MISCREG_CWP, CWP); 445 // Do the stores 446 IntReg sp = tc->readIntReg(StackPointerReg); 447 for (int index = 16; index < 32; index++) { 448 uint32_t regVal = tc->readIntReg(index); 449 regVal = htog(regVal); 450 if (!tc->getMemProxy()->tryWriteBlob( 451 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 452 warn("Failed to save register to the stack when " 453 "flushing windows.\n"); 454 } 455 } 456 Canrestore--; 457 Cansave++; 458 CWP = (CWP + 1) % NWindows; 459 } 460 } 461 tc->setIntReg(NumIntArchRegs + 3, Cansave); 462 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 463 tc->setMiscReg(MISCREG_CWP, origCWP); 464} 465 466void 467Sparc64LiveProcess::flushWindows(ThreadContext *tc) 468{ 469 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 470 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 471 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 472 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 473 MiscReg origCWP = CWP; 474 CWP = (CWP + Cansave + 2) % NWindows; 475 while (NWindows - 2 - Cansave != 0) { 476 if (Otherwin) { 477 panic("Otherwin non-zero.\n"); 478 } else { 479 tc->setMiscReg(MISCREG_CWP, CWP); 480 // Do the stores 481 IntReg sp = tc->readIntReg(StackPointerReg); 482 for (int index = 16; index < 32; index++) { 483 IntReg regVal = tc->readIntReg(index); 484 regVal = htog(regVal); 485 if (!tc->getMemProxy()->tryWriteBlob( 486 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 487 warn("Failed to save register to the stack when " 488 "flushing windows.\n"); 489 } 490 } 491 Canrestore--; 492 Cansave++; 493 CWP = (CWP + 1) % NWindows; 494 } 495 } 496 tc->setIntReg(NumIntArchRegs + 3, Cansave); 497 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 498 tc->setMiscReg(MISCREG_CWP, origCWP); 499} 500 501IntReg 502Sparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 503{ 504 assert(i < 6); 505 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 506} 507 508void 509Sparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 510{ 511 assert(i < 6); 512 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 513} 514 515IntReg 516Sparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 517{ 518 assert(i < 6); 519 return tc->readIntReg(FirstArgumentReg + i++); 520} 521 522void 523Sparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 524{ 525 assert(i < 6); 526 tc->setIntReg(FirstArgumentReg + i, val); 527} 528 529void 530SparcLiveProcess::setSyscallReturn(ThreadContext *tc, 531 SyscallReturn return_value) 532{ 533 // check for error condition. SPARC syscall convention is to 534 // indicate success/failure in reg the carry bit of the ccr 535 // and put the return value itself in the standard return value reg (). 536 if (return_value.successful()) { 537 // no error, clear XCC.C 538 tc->setIntReg(NumIntArchRegs + 2, 539 tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 540 // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE); 541 IntReg val = return_value.value(); 542 if (bits(tc->readMiscRegNoEffect( 543 SparcISA::MISCREG_PSTATE), 3, 3)) { 544 val = bits(val, 31, 0); 545 } 546 tc->setIntReg(ReturnValueReg, val); 547 } else { 548 // got an error, set XCC.C 549 tc->setIntReg(NumIntArchRegs + 2, 550 tc->readIntReg(NumIntArchRegs + 2) | 0x11); 551 // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11); 552 IntReg val = -return_value.value(); 553 if (bits(tc->readMiscRegNoEffect( 554 SparcISA::MISCREG_PSTATE), 3, 3)) { 555 val = bits(val, 31, 0); 556 } 557 tc->setIntReg(ReturnValueReg, val); 558 } 559} 560