process.cc revision 11793
1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/process.hh" 33 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/handlers.hh" 36#include "arch/sparc/isa_traits.hh" 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "base/loader/elf_object.hh" 40#include "base/loader/object_file.hh" 41#include "base/misc.hh" 42#include "cpu/thread_context.hh" 43#include "debug/Stack.hh" 44#include "mem/page_table.hh" 45#include "sim/process_impl.hh" 46#include "sim/system.hh" 47 48using namespace std; 49using namespace SparcISA; 50 51static const int FirstArgumentReg = 8; 52 53 54SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 55 ObjectFile *objFile, Addr _StackBias) 56 : LiveProcess(params, objFile), StackBias(_StackBias) 57{ 58 59 // XXX all the below need to be updated for SPARC - Ali 60 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 61 brk_point = roundUp(brk_point, PageBytes); 62 63 // Set pointer for next thread stack. Reserve 8M for main stack. 64 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 65 66 // Initialize these to 0s 67 fillStart = 0; 68 spillStart = 0; 69} 70 71void 72SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 73{ 74 PCState pc = tc->pcState(); 75 switch (trapNum) { 76 case 0x01: // Software breakpoint 77 warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 78 break; 79 case 0x02: // Division by zero 80 warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 81 break; 82 case 0x03: // Flush window trap 83 flushWindows(tc); 84 break; 85 case 0x04: // Clean windows 86 warn("Ignoring process request for clean register " 87 "windows at pc %#x.\n", pc.pc()); 88 break; 89 case 0x05: // Range check 90 warn("Software signaled a range check at pc %#x.\n", pc.pc()); 91 break; 92 case 0x06: // Fix alignment 93 warn("Ignoring process request for os assisted unaligned accesses " 94 "at pc %#x.\n", pc.pc()); 95 break; 96 case 0x07: // Integer overflow 97 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 98 break; 99 case 0x32: // Get integer condition codes 100 warn("Ignoring process request to get the integer condition codes " 101 "at pc %#x.\n", pc.pc()); 102 break; 103 case 0x33: // Set integer condition codes 104 warn("Ignoring process request to set the integer condition codes " 105 "at pc %#x.\n", pc.pc()); 106 break; 107 default: 108 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 109 } 110} 111 112void 113SparcLiveProcess::initState() 114{ 115 LiveProcess::initState(); 116 117 ThreadContext *tc = system->getThreadContext(contextIds[0]); 118 // From the SPARC ABI 119 120 // Setup default FP state 121 tc->setMiscRegNoEffect(MISCREG_FSR, 0); 122 123 tc->setMiscRegNoEffect(MISCREG_TICK, 0); 124 125 /* 126 * Register window management registers 127 */ 128 129 // No windows contain info from other programs 130 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 131 tc->setIntReg(NumIntArchRegs + 6, 0); 132 // There are no windows to pop 133 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 134 tc->setIntReg(NumIntArchRegs + 4, 0); 135 // All windows are available to save into 136 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 137 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 138 // All windows are "clean" 139 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 140 tc->setIntReg(NumIntArchRegs + 5, NWindows); 141 // Start with register window 0 142 tc->setMiscReg(MISCREG_CWP, 0); 143 // Always use spill and fill traps 0 144 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 145 tc->setIntReg(NumIntArchRegs + 7, 0); 146 // Set the trap level to 0 147 tc->setMiscRegNoEffect(MISCREG_TL, 0); 148 // Set the ASI register to something fixed 149 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 150 151 /* 152 * T1 specific registers 153 */ 154 // Turn on the icache, dcache, dtb translation, and itb translation. 155 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 156} 157 158void 159Sparc32LiveProcess::initState() 160{ 161 SparcLiveProcess::initState(); 162 163 ThreadContext *tc = system->getThreadContext(contextIds[0]); 164 // The process runs in user mode with 32 bit addresses 165 PSTATE pstate = 0; 166 pstate.ie = 1; 167 pstate.am = 1; 168 tc->setMiscReg(MISCREG_PSTATE, pstate); 169 170 argsInit(32 / 8, PageBytes); 171} 172 173void 174Sparc64LiveProcess::initState() 175{ 176 SparcLiveProcess::initState(); 177 178 ThreadContext *tc = system->getThreadContext(contextIds[0]); 179 // The process runs in user mode 180 PSTATE pstate = 0; 181 pstate.ie = 1; 182 tc->setMiscReg(MISCREG_PSTATE, pstate); 183 184 argsInit(sizeof(IntReg), PageBytes); 185} 186 187template<class IntType> 188void 189SparcLiveProcess::argsInit(int pageSize) 190{ 191 int intSize = sizeof(IntType); 192 193 typedef AuxVector<IntType> auxv_t; 194 195 std::vector<auxv_t> auxv; 196 197 string filename; 198 if (argv.size() < 1) 199 filename = ""; 200 else 201 filename = argv[0]; 202 203 // Even for a 32 bit process, the ABI says we still need to 204 // maintain double word alignment of the stack pointer. 205 uint64_t align = 16; 206 207 // Patch the ld_bias for dynamic executables. 208 updateBias(); 209 210 // load object file into target memory 211 objFile->loadSections(initVirtMem); 212 213 enum hardwareCaps 214 { 215 M5_HWCAP_SPARC_FLUSH = 1, 216 M5_HWCAP_SPARC_STBAR = 2, 217 M5_HWCAP_SPARC_SWAP = 4, 218 M5_HWCAP_SPARC_MULDIV = 8, 219 M5_HWCAP_SPARC_V9 = 16, 220 // This one should technically only be set 221 // if there is a cheetah or cheetah_plus tlb, 222 // but we'll use it all the time 223 M5_HWCAP_SPARC_ULTRA3 = 32 224 }; 225 226 const int64_t hwcap = 227 M5_HWCAP_SPARC_FLUSH | 228 M5_HWCAP_SPARC_STBAR | 229 M5_HWCAP_SPARC_SWAP | 230 M5_HWCAP_SPARC_MULDIV | 231 M5_HWCAP_SPARC_V9 | 232 M5_HWCAP_SPARC_ULTRA3; 233 234 // Setup the auxilliary vectors. These will already have endian conversion. 235 // Auxilliary vectors are loaded only for elf formatted executables. 236 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 237 if (elfObject) { 238 // Bits which describe the system hardware capabilities 239 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 240 // The system page size 241 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 242 // Defined to be 100 in the kernel source. 243 // Frequency at which times() increments 244 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 245 // For statically linked executables, this is the virtual address of the 246 // program header tables if they appear in the executable image 247 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 248 // This is the size of a program header entry from the elf file. 249 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 250 // This is the number of program headers from the original elf file. 251 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 252 // This is the base address of the ELF interpreter; it should be 253 // zero for static executables or contain the base address for 254 // dynamic executables. 255 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 256 // This is hardwired to 0 in the elf loading code in the kernel 257 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 258 // The entry point to the program 259 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 260 // Different user and group IDs 261 auxv.push_back(auxv_t(M5_AT_UID, uid())); 262 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 263 auxv.push_back(auxv_t(M5_AT_GID, gid())); 264 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 265 // Whether to enable "secure mode" in the executable 266 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 267 } 268 269 // Figure out how big the initial stack needs to be 270 271 // The unaccounted for 8 byte 0 at the top of the stack 272 int sentry_size = 8; 273 274 // This is the name of the file which is present on the initial stack 275 // It's purpose is to let the user space linker examine the original file. 276 int file_name_size = filename.size() + 1; 277 278 int env_data_size = 0; 279 for (int i = 0; i < envp.size(); ++i) { 280 env_data_size += envp[i].size() + 1; 281 } 282 int arg_data_size = 0; 283 for (int i = 0; i < argv.size(); ++i) { 284 arg_data_size += argv[i].size() + 1; 285 } 286 287 // The info_block. 288 int base_info_block_size = 289 sentry_size + file_name_size + env_data_size + arg_data_size; 290 291 int info_block_size = roundUp(base_info_block_size, align); 292 293 int info_block_padding = info_block_size - base_info_block_size; 294 295 // Each auxilliary vector is two words 296 int aux_array_size = intSize * 2 * (auxv.size() + 1); 297 298 int envp_array_size = intSize * (envp.size() + 1); 299 int argv_array_size = intSize * (argv.size() + 1); 300 301 int argc_size = intSize; 302 int window_save_size = intSize * 16; 303 304 // Figure out the size of the contents of the actual initial frame 305 int frame_size = 306 aux_array_size + 307 envp_array_size + 308 argv_array_size + 309 argc_size + 310 window_save_size; 311 312 // There needs to be padding after the auxiliary vector data so that the 313 // very bottom of the stack is aligned properly. 314 int aligned_partial_size = roundUp(frame_size, align); 315 int aux_padding = aligned_partial_size - frame_size; 316 317 int space_needed = 318 info_block_size + 319 aux_padding + 320 frame_size; 321 322 stack_min = stack_base - space_needed; 323 stack_min = roundDown(stack_min, align); 324 stack_size = stack_base - stack_min; 325 326 // Allocate space for the stack 327 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 328 329 // map out initial stack contents 330 IntType sentry_base = stack_base - sentry_size; 331 IntType file_name_base = sentry_base - file_name_size; 332 IntType env_data_base = file_name_base - env_data_size; 333 IntType arg_data_base = env_data_base - arg_data_size; 334 IntType auxv_array_base = arg_data_base - 335 info_block_padding - aux_array_size - aux_padding; 336 IntType envp_array_base = auxv_array_base - envp_array_size; 337 IntType argv_array_base = envp_array_base - argv_array_size; 338 IntType argc_base = argv_array_base - argc_size; 339#if TRACING_ON 340 IntType window_save_base = argc_base - window_save_size; 341#endif 342 343 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 344 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 345 DPRINTF(Stack, "filename = %s\n", filename); 346 DPRINTF(Stack, "%#x - file name\n", file_name_base); 347 DPRINTF(Stack, "%#x - env data\n", env_data_base); 348 DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 349 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 350 DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 351 DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 352 DPRINTF(Stack, "%#x - argc \n", argc_base); 353 DPRINTF(Stack, "%#x - window save\n", window_save_base); 354 DPRINTF(Stack, "%#x - stack min\n", stack_min); 355 356 assert(window_save_base == stack_min); 357 358 // write contents to stack 359 360 // figure out argc 361 IntType argc = argv.size(); 362 IntType guestArgc = SparcISA::htog(argc); 363 364 // Write out the sentry void * 365 uint64_t sentry_NULL = 0; 366 initVirtMem.writeBlob(sentry_base, 367 (uint8_t*)&sentry_NULL, sentry_size); 368 369 // Write the file name 370 initVirtMem.writeString(file_name_base, filename.c_str()); 371 372 // Copy the aux stuff 373 for (int x = 0; x < auxv.size(); x++) { 374 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 375 (uint8_t*)&(auxv[x].a_type), intSize); 376 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 377 (uint8_t*)&(auxv[x].a_val), intSize); 378 } 379 380 // Write out the terminating zeroed auxilliary vector 381 const IntType zero = 0; 382 initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 383 (uint8_t*)&zero, intSize); 384 initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 385 (uint8_t*)&zero, intSize); 386 387 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 388 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 389 390 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 391 392 // Set up space for the trap handlers into the processes address space. 393 // Since the stack grows down and there is reserved address space abov 394 // it, we can put stuff above it and stay out of the way. 395 fillStart = stack_base; 396 spillStart = fillStart + sizeof(MachInst) * numFillInsts; 397 398 ThreadContext *tc = system->getThreadContext(contextIds[0]); 399 // Set up the thread context to start running the process 400 // assert(NumArgumentRegs >= 2); 401 // tc->setIntReg(ArgumentReg[0], argc); 402 // tc->setIntReg(ArgumentReg[1], argv_array_base); 403 tc->setIntReg(StackPointerReg, stack_min - StackBias); 404 405 // %g1 is a pointer to a function that should be run at exit. Since we 406 // don't have anything like that, it should be set to 0. 407 tc->setIntReg(1, 0); 408 409 tc->pcState(getStartPC()); 410 411 // Align the "stack_min" to a page boundary. 412 stack_min = roundDown(stack_min, pageSize); 413 414// num_processes++; 415} 416 417void 418Sparc64LiveProcess::argsInit(int intSize, int pageSize) 419{ 420 SparcLiveProcess::argsInit<uint64_t>(pageSize); 421 422 // Stuff the trap handlers into the process address space 423 initVirtMem.writeBlob(fillStart, 424 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 425 initVirtMem.writeBlob(spillStart, 426 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 427} 428 429void 430Sparc32LiveProcess::argsInit(int intSize, int pageSize) 431{ 432 SparcLiveProcess::argsInit<uint32_t>(pageSize); 433 434 // Stuff the trap handlers into the process address space 435 initVirtMem.writeBlob(fillStart, 436 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 437 initVirtMem.writeBlob(spillStart, 438 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 439} 440 441void Sparc32LiveProcess::flushWindows(ThreadContext *tc) 442{ 443 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 444 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 445 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 446 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 447 MiscReg origCWP = CWP; 448 CWP = (CWP + Cansave + 2) % NWindows; 449 while (NWindows - 2 - Cansave != 0) { 450 if (Otherwin) { 451 panic("Otherwin non-zero.\n"); 452 } else { 453 tc->setMiscReg(MISCREG_CWP, CWP); 454 // Do the stores 455 IntReg sp = tc->readIntReg(StackPointerReg); 456 for (int index = 16; index < 32; index++) { 457 uint32_t regVal = tc->readIntReg(index); 458 regVal = htog(regVal); 459 if (!tc->getMemProxy().tryWriteBlob( 460 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 461 warn("Failed to save register to the stack when " 462 "flushing windows.\n"); 463 } 464 } 465 Canrestore--; 466 Cansave++; 467 CWP = (CWP + 1) % NWindows; 468 } 469 } 470 tc->setIntReg(NumIntArchRegs + 3, Cansave); 471 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 472 tc->setMiscReg(MISCREG_CWP, origCWP); 473} 474 475void 476Sparc64LiveProcess::flushWindows(ThreadContext *tc) 477{ 478 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 479 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 480 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 481 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 482 MiscReg origCWP = CWP; 483 CWP = (CWP + Cansave + 2) % NWindows; 484 while (NWindows - 2 - Cansave != 0) { 485 if (Otherwin) { 486 panic("Otherwin non-zero.\n"); 487 } else { 488 tc->setMiscReg(MISCREG_CWP, CWP); 489 // Do the stores 490 IntReg sp = tc->readIntReg(StackPointerReg); 491 for (int index = 16; index < 32; index++) { 492 IntReg regVal = tc->readIntReg(index); 493 regVal = htog(regVal); 494 if (!tc->getMemProxy().tryWriteBlob( 495 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 496 warn("Failed to save register to the stack when " 497 "flushing windows.\n"); 498 } 499 } 500 Canrestore--; 501 Cansave++; 502 CWP = (CWP + 1) % NWindows; 503 } 504 } 505 tc->setIntReg(NumIntArchRegs + 3, Cansave); 506 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 507 tc->setMiscReg(MISCREG_CWP, origCWP); 508} 509 510IntReg 511Sparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 512{ 513 assert(i < 6); 514 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 515} 516 517void 518Sparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 519{ 520 assert(i < 6); 521 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 522} 523 524IntReg 525Sparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 526{ 527 assert(i < 6); 528 return tc->readIntReg(FirstArgumentReg + i++); 529} 530 531void 532Sparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 533{ 534 assert(i < 6); 535 tc->setIntReg(FirstArgumentReg + i, val); 536} 537 538void 539SparcLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 540{ 541 // check for error condition. SPARC syscall convention is to 542 // indicate success/failure in reg the carry bit of the ccr 543 // and put the return value itself in the standard return value reg (). 544 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 545 if (sysret.successful()) { 546 // no error, clear XCC.C 547 tc->setIntReg(NumIntArchRegs + 2, 548 tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 549 IntReg val = sysret.returnValue(); 550 if (pstate.am) 551 val = bits(val, 31, 0); 552 tc->setIntReg(ReturnValueReg, val); 553 } else { 554 // got an error, set XCC.C 555 tc->setIntReg(NumIntArchRegs + 2, 556 tc->readIntReg(NumIntArchRegs + 2) | 0x11); 557 IntReg val = sysret.errnoValue(); 558 if (pstate.am) 559 val = bits(val, 31, 0); 560 tc->setIntReg(ReturnValueReg, val); 561 } 562} 563