process.cc revision 9375
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 3211793Sbrandon.potter@amd.com#include "arch/sparc/asi.hh" 3311793Sbrandon.potter@amd.com#include "arch/sparc/handlers.hh" 343589Sgblack@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 354111Sgblack@eecs.umich.edu#include "arch/sparc/process.hh" 362474SN/A#include "arch/sparc/registers.hh" 376335Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 383760Sgblack@eecs.umich.edu#include "base/loader/elf_object.hh" 398229Snate@binkert.org#include "base/loader/object_file.hh" 402454SN/A#include "base/misc.hh" 412454SN/A#include "cpu/thread_context.hh" 422680Sktlim@umich.edu#include "debug/Stack.hh" 438232Snate@binkert.org#include "mem/page_table.hh" 442561SN/A#include "sim/process_impl.hh" 4511854Sbrandon.potter@amd.com#include "sim/system.hh" 464434Ssaidi@eecs.umich.edu 4711800Sbrandon.potter@amd.comusing namespace std; 482474SN/Ausing namespace SparcISA; 492207SN/A 502458SN/Astatic const int FirstArgumentReg = 8; 512474SN/A 522458SN/A 535958Sgblack@eecs.umich.eduSparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 545958Sgblack@eecs.umich.edu ObjectFile *objFile, Addr _StackBias) 552207SN/A : LiveProcess(params, objFile), StackBias(_StackBias) 5611851Sbrandon.potter@amd.com{ 5711851Sbrandon.potter@amd.com 5811851Sbrandon.potter@amd.com // XXX all the below need to be updated for SPARC - Ali 592474SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 602474SN/A brk_point = roundUp(brk_point, VMPageSize); 612474SN/A 622474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 6310318Sandreas.hansson@arm.com next_thread_stack_base = stack_base - (8 * 1024 * 1024); 642474SN/A 652474SN/A // Initialize these to 0s 662474SN/A fillStart = 0; 673415Sgblack@eecs.umich.edu spillStart = 0; 687741Sgblack@eecs.umich.edu} 693415Sgblack@eecs.umich.edu 703415Sgblack@eecs.umich.eduvoid 712474SN/ASparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 722474SN/A{ 737741Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7411877Sbrandon.potter@amd.com switch (trapNum) { 754111Sgblack@eecs.umich.edu case 0x01: // Software breakpoint 767720Sgblack@eecs.umich.edu warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 777741Sgblack@eecs.umich.edu break; 787741Sgblack@eecs.umich.edu case 0x02: // Division by zero 797720Sgblack@eecs.umich.edu warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 805128Sgblack@eecs.umich.edu break; 817741Sgblack@eecs.umich.edu case 0x03: // Flush window trap 827720Sgblack@eecs.umich.edu flushWindows(tc); 835128Sgblack@eecs.umich.edu break; 847741Sgblack@eecs.umich.edu case 0x04: // Clean windows 855128Sgblack@eecs.umich.edu warn("Ignoring process request for clean register " 865128Sgblack@eecs.umich.edu "windows at pc %#x.\n", pc.pc()); 877741Sgblack@eecs.umich.edu break; 885128Sgblack@eecs.umich.edu case 0x05: // Range check 897720Sgblack@eecs.umich.edu warn("Software signaled a range check at pc %#x.\n", pc.pc()); 905128Sgblack@eecs.umich.edu break; 917741Sgblack@eecs.umich.edu case 0x06: // Fix alignment 927720Sgblack@eecs.umich.edu warn("Ignoring process request for os assisted unaligned accesses " 935128Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 947741Sgblack@eecs.umich.edu break; 955128Sgblack@eecs.umich.edu case 0x07: // Integer overflow 967720Sgblack@eecs.umich.edu warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 975128Sgblack@eecs.umich.edu break; 987741Sgblack@eecs.umich.edu case 0x32: // Get integer condition codes 997720Sgblack@eecs.umich.edu warn("Ignoring process request to get the integer condition codes " 1005128Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1017741Sgblack@eecs.umich.edu break; 1025128Sgblack@eecs.umich.edu case 0x33: // Set integer condition codes 1037720Sgblack@eecs.umich.edu warn("Ignoring process request to set the integer condition codes " 1045128Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1057741Sgblack@eecs.umich.edu break; 1065128Sgblack@eecs.umich.edu default: 1077720Sgblack@eecs.umich.edu panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1084111Sgblack@eecs.umich.edu } 1094111Sgblack@eecs.umich.edu} 1104111Sgblack@eecs.umich.edu 1114111Sgblack@eecs.umich.eduvoid 1124111Sgblack@eecs.umich.eduSparcLiveProcess::initState() 1134111Sgblack@eecs.umich.edu{ 1142474SN/A LiveProcess::initState(); 11511851Sbrandon.potter@amd.com 1164111Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 11711851Sbrandon.potter@amd.com // From the SPARC ABI 1184111Sgblack@eecs.umich.edu 1195713Shsul@eecs.umich.edu // Setup default FP state 1207741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1214111Sgblack@eecs.umich.edu 1227741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1235713Shsul@eecs.umich.edu 1242646Ssaidi@eecs.umich.edu /* 1255713Shsul@eecs.umich.edu * Register window management registers 1264997Sgblack@eecs.umich.edu */ 1272561SN/A 1282561SN/A // No windows contain info from other programs 1292561SN/A // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1302561SN/A tc->setIntReg(NumIntArchRegs + 6, 0); 1317741Sgblack@eecs.umich.edu // There are no windows to pop 1327741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1335713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, 0); 1347741Sgblack@eecs.umich.edu // All windows are available to save into 1357741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 1365713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 1377741Sgblack@eecs.umich.edu // All windows are "clean" 1387741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 1395713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 5, NWindows); 1407741Sgblack@eecs.umich.edu // Start with register window 0 1417741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, 0); 1425713Shsul@eecs.umich.edu // Always use spill and fill traps 0 1437741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1446337Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 7, 0); 1457741Sgblack@eecs.umich.edu // Set the trap level to 0 1467741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, 0); 1475713Shsul@eecs.umich.edu // Set the ASI register to something fixed 1487741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 1495713Shsul@eecs.umich.edu 1507741Sgblack@eecs.umich.edu /* 1519375Sgblack@eecs.umich.edu * T1 specific registers 1524997Sgblack@eecs.umich.edu */ 15311850Sbrandon.potter@amd.com // Turn on the icache, dcache, dtb translation, and itb translation. 15411850Sbrandon.potter@amd.com tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 15511850Sbrandon.potter@amd.com} 1564997Sgblack@eecs.umich.edu 1574997Sgblack@eecs.umich.eduvoid 1584997Sgblack@eecs.umich.eduSparc32LiveProcess::initState() 1597741Sgblack@eecs.umich.edu{ 1605713Shsul@eecs.umich.edu SparcLiveProcess::initState(); 1612474SN/A 1622474SN/A ThreadContext *tc = system->getThreadContext(contextIds[0]); 1635285Sgblack@eecs.umich.edu // The process runs in user mode with 32 bit addresses 16411851Sbrandon.potter@amd.com PSTATE pstate = 0; 1652585SN/A pstate.ie = 1; 16611851Sbrandon.potter@amd.com pstate.am = 1; 1675285Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1685713Shsul@eecs.umich.edu 1697741Sgblack@eecs.umich.edu argsInit(32 / 8, VMPageSize); 1708829Sgblack@eecs.umich.edu} 1718829Sgblack@eecs.umich.edu 1728829Sgblack@eecs.umich.eduvoid 1738829Sgblack@eecs.umich.eduSparc64LiveProcess::initState() 1745285Sgblack@eecs.umich.edu{ 17510318Sandreas.hansson@arm.com SparcLiveProcess::initState(); 1764111Sgblack@eecs.umich.edu 1773415Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1782561SN/A // The process runs in user mode 17911851Sbrandon.potter@amd.com PSTATE pstate = 0; 1802561SN/A pstate.ie = 1; 18111851Sbrandon.potter@amd.com tc->setMiscReg(MISCREG_PSTATE, pstate); 1825285Sgblack@eecs.umich.edu 1835713Shsul@eecs.umich.edu argsInit(sizeof(IntReg), VMPageSize); 1847741Sgblack@eecs.umich.edu} 1858829Sgblack@eecs.umich.edu 1868829Sgblack@eecs.umich.edutemplate<class IntType> 1878829Sgblack@eecs.umich.eduvoid 1885285Sgblack@eecs.umich.eduSparcLiveProcess::argsInit(int pageSize) 18910318Sandreas.hansson@arm.com{ 1905285Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 1915285Sgblack@eecs.umich.edu 1925285Sgblack@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 1935285Sgblack@eecs.umich.edu 19411851Sbrandon.potter@amd.com std::vector<auxv_t> auxv; 1955285Sgblack@eecs.umich.edu 1965285Sgblack@eecs.umich.edu string filename; 1975285Sgblack@eecs.umich.edu if (argv.size() < 1) 1985771Shsul@eecs.umich.edu filename = ""; 1995285Sgblack@eecs.umich.edu else 2005285Sgblack@eecs.umich.edu filename = argv[0]; 2012474SN/A 2023044Sgblack@eecs.umich.edu // Even for a 32 bit process, the ABI says we still need to 2037741Sgblack@eecs.umich.edu // maintain double word alignment of the stack pointer. 2043044Sgblack@eecs.umich.edu uint64_t align = 16; 2053044Sgblack@eecs.umich.edu 2063044Sgblack@eecs.umich.edu // load object file into target memory 2073044Sgblack@eecs.umich.edu objFile->loadSections(initVirtMem); 2087741Sgblack@eecs.umich.edu 2097741Sgblack@eecs.umich.edu enum hardwareCaps 2105286Sgblack@eecs.umich.edu { 2112561SN/A M5_HWCAP_SPARC_FLUSH = 1, 21211389Sbrandon.potter@amd.com M5_HWCAP_SPARC_STBAR = 2, 21311389Sbrandon.potter@amd.com M5_HWCAP_SPARC_SWAP = 4, 21411389Sbrandon.potter@amd.com M5_HWCAP_SPARC_MULDIV = 8, 2152561SN/A M5_HWCAP_SPARC_V9 = 16, 2162561SN/A // This one should technically only be set 2172561SN/A // if there is a cheetah or cheetah_plus tlb, 2182585SN/A // but we'll use it all the time 2192585SN/A M5_HWCAP_SPARC_ULTRA3 = 32 2202585SN/A }; 2212585SN/A 2222585SN/A const int64_t hwcap = 2232585SN/A M5_HWCAP_SPARC_FLUSH | 2242585SN/A M5_HWCAP_SPARC_STBAR | 2257741Sgblack@eecs.umich.edu M5_HWCAP_SPARC_SWAP | 2267741Sgblack@eecs.umich.edu M5_HWCAP_SPARC_MULDIV | 2277741Sgblack@eecs.umich.edu M5_HWCAP_SPARC_V9 | 2282585SN/A M5_HWCAP_SPARC_ULTRA3; 2292585SN/A 2302585SN/A // Setup the auxilliary vectors. These will already have endian conversion. 2312585SN/A // Auxilliary vectors are loaded only for elf formatted executables. 2322585SN/A ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2332585SN/A if (elfObject) { 2342585SN/A // Bits which describe the system hardware capabilities 2352585SN/A auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 2362585SN/A // The system page size 2372585SN/A auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize)); 2382585SN/A // Defined to be 100 in the kernel source. 2397741Sgblack@eecs.umich.edu // Frequency at which times() increments 2407741Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 2412976Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2427741Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2437741Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2444793Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2457741Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 24610318Sandreas.hansson@arm.com // This is the number of program headers from the original elf file. 2477741Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 2487741Sgblack@eecs.umich.edu // This is the address of the elf "interpreter", It should be set 2494793Sgblack@eecs.umich.edu // to 0 for regular executables. It should be something else 2502976Sgblack@eecs.umich.edu // (not sure what) for dynamic libraries. 2512976Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_BASE, 0)); 2524793Sgblack@eecs.umich.edu // This is hardwired to 0 in the elf loading code in the kernel 2532976Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2544793Sgblack@eecs.umich.edu // The entry point to the program 2552976Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2564793Sgblack@eecs.umich.edu // Different user and group IDs 25711389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_UID, uid())); 25811389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_EUID, euid())); 25911389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_GID, gid())); 26011389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2617741Sgblack@eecs.umich.edu // Whether to enable "secure mode" in the executable 2624793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 2637741Sgblack@eecs.umich.edu } 2644793Sgblack@eecs.umich.edu 2657741Sgblack@eecs.umich.edu // Figure out how big the initial stack needs to be 2664793Sgblack@eecs.umich.edu 2674793Sgblack@eecs.umich.edu // The unaccounted for 8 byte 0 at the top of the stack 2684793Sgblack@eecs.umich.edu int sentry_size = 8; 2694793Sgblack@eecs.umich.edu 2707741Sgblack@eecs.umich.edu // This is the name of the file which is present on the initial stack 2714793Sgblack@eecs.umich.edu // It's purpose is to let the user space linker examine the original file. 2722976Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 2732585SN/A 2747741Sgblack@eecs.umich.edu int env_data_size = 0; 2752561SN/A for (int i = 0; i < envp.size(); ++i) { 2764164Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 2775286Sgblack@eecs.umich.edu } 2784111Sgblack@eecs.umich.edu int arg_data_size = 0; 2797741Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 2807741Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 2814111Sgblack@eecs.umich.edu } 2824111Sgblack@eecs.umich.edu 2834111Sgblack@eecs.umich.edu // The info_block. 2844111Sgblack@eecs.umich.edu int base_info_block_size = 2854111Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 2864111Sgblack@eecs.umich.edu 2874111Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 2884111Sgblack@eecs.umich.edu 2894111Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 2904111Sgblack@eecs.umich.edu 2914111Sgblack@eecs.umich.edu // Each auxilliary vector is two words 2927741Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 2935286Sgblack@eecs.umich.edu 2945286Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 2955286Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 2965286Sgblack@eecs.umich.edu 2975286Sgblack@eecs.umich.edu int argc_size = intSize; 2985286Sgblack@eecs.umich.edu int window_save_size = intSize * 16; 2994111Sgblack@eecs.umich.edu 3007741Sgblack@eecs.umich.edu // Figure out the size of the contents of the actual initial frame 3014111Sgblack@eecs.umich.edu int frame_size = 3024111Sgblack@eecs.umich.edu aux_array_size + 3034111Sgblack@eecs.umich.edu envp_array_size + 3044111Sgblack@eecs.umich.edu argv_array_size + 3054111Sgblack@eecs.umich.edu argc_size + 3064111Sgblack@eecs.umich.edu window_save_size; 3074111Sgblack@eecs.umich.edu 3084111Sgblack@eecs.umich.edu // There needs to be padding after the auxiliary vector data so that the 3097741Sgblack@eecs.umich.edu // very bottom of the stack is aligned properly. 3105286Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(frame_size, align); 3114111Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3124111Sgblack@eecs.umich.edu 3134111Sgblack@eecs.umich.edu int space_needed = 3144111Sgblack@eecs.umich.edu info_block_size + 3154111Sgblack@eecs.umich.edu aux_padding + 3164111Sgblack@eecs.umich.edu frame_size; 3177741Sgblack@eecs.umich.edu 3187741Sgblack@eecs.umich.edu stack_min = stack_base - space_needed; 3195286Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, align); 3205286Sgblack@eecs.umich.edu stack_size = stack_base - stack_min; 3215286Sgblack@eecs.umich.edu 3225286Sgblack@eecs.umich.edu // Allocate space for the stack 3235286Sgblack@eecs.umich.edu allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 3245286Sgblack@eecs.umich.edu 3255286Sgblack@eecs.umich.edu // map out initial stack contents 3265286Sgblack@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 3274111Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 3285286Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3294111Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3304111Sgblack@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3315285Sgblack@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3328601Ssteve.reinhardt@amd.com IntType envp_array_base = auxv_array_base - envp_array_size; 3334111Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 3344111Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3355286Sgblack@eecs.umich.edu#if TRACING_ON 3365286Sgblack@eecs.umich.edu IntType window_save_base = argc_base - window_save_size; 3375286Sgblack@eecs.umich.edu#endif 3385286Sgblack@eecs.umich.edu 3395286Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3405286Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 3415286Sgblack@eecs.umich.edu DPRINTF(Stack, "filename = %s\n", filename); 3425286Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - file name\n", file_name_base); 3435286Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - env data\n", env_data_base); 3445286Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 3455286Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 3465286Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 3474111Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 3485941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argc \n", argc_base); 3495941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - window save\n", window_save_base); 3505941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - stack min\n", stack_min); 3515941Sgblack@eecs.umich.edu 3525941Sgblack@eecs.umich.edu assert(window_save_base == stack_min); 3535941Sgblack@eecs.umich.edu 3545941Sgblack@eecs.umich.edu // write contents to stack 3555941Sgblack@eecs.umich.edu 3565941Sgblack@eecs.umich.edu // figure out argc 3575941Sgblack@eecs.umich.edu IntType argc = argv.size(); 3585941Sgblack@eecs.umich.edu IntType guestArgc = SparcISA::htog(argc); 3595941Sgblack@eecs.umich.edu 3604111Sgblack@eecs.umich.edu // Write out the sentry void * 3615286Sgblack@eecs.umich.edu uint64_t sentry_NULL = 0; 3625286Sgblack@eecs.umich.edu initVirtMem.writeBlob(sentry_base, 3634111Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3644111Sgblack@eecs.umich.edu 3654111Sgblack@eecs.umich.edu // Write the file name 3665285Sgblack@eecs.umich.edu initVirtMem.writeString(file_name_base, filename.c_str()); 3675567Snate@binkert.org 3684111Sgblack@eecs.umich.edu // Copy the aux stuff 3697741Sgblack@eecs.umich.edu for (int x = 0; x < auxv.size(); x++) { 3705286Sgblack@eecs.umich.edu initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 3718852Sandreas.hansson@arm.com (uint8_t*)&(auxv[x].a_type), intSize); 3725286Sgblack@eecs.umich.edu initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 3734111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 3747741Sgblack@eecs.umich.edu } 3758852Sandreas.hansson@arm.com 3764111Sgblack@eecs.umich.edu // Write out the terminating zeroed auxilliary vector 3777741Sgblack@eecs.umich.edu const IntType zero = 0; 3787741Sgblack@eecs.umich.edu initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 3798852Sandreas.hansson@arm.com (uint8_t*)&zero, intSize); 3804111Sgblack@eecs.umich.edu initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 3818852Sandreas.hansson@arm.com (uint8_t*)&zero, intSize); 3824111Sgblack@eecs.umich.edu 3834111Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 3845285Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 3857741Sgblack@eecs.umich.edu 3865285Sgblack@eecs.umich.edu initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 3878852Sandreas.hansson@arm.com 3885286Sgblack@eecs.umich.edu // Set up space for the trap handlers into the processes address space. 3898852Sandreas.hansson@arm.com // Since the stack grows down and there is reserved address space abov 3905286Sgblack@eecs.umich.edu // it, we can put stuff above it and stay out of the way. 3914111Sgblack@eecs.umich.edu fillStart = stack_base; 3924117Sgblack@eecs.umich.edu spillStart = fillStart + sizeof(MachInst) * numFillInsts; 3934117Sgblack@eecs.umich.edu 3944111Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 3958852Sandreas.hansson@arm.com // Set up the thread context to start running the process 3964111Sgblack@eecs.umich.edu // assert(NumArgumentRegs >= 2); 3977741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[0], argc); 3987741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[1], argv_array_base); 3997741Sgblack@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min - StackBias); 4004111Sgblack@eecs.umich.edu 4015285Sgblack@eecs.umich.edu // %g1 is a pointer to a function that should be run at exit. Since we 4024111Sgblack@eecs.umich.edu // don't have anything like that, it should be set to 0. 4035713Shsul@eecs.umich.edu tc->setIntReg(1, 0); 4047741Sgblack@eecs.umich.edu 4057741Sgblack@eecs.umich.edu tc->pcState(objFile->entryPoint()); 4067741Sgblack@eecs.umich.edu 4077741Sgblack@eecs.umich.edu // Align the "stack_min" to a page boundary. 4085713Shsul@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 4094111Sgblack@eecs.umich.edu 4105231Sgblack@eecs.umich.edu// num_processes++; 4115231Sgblack@eecs.umich.edu} 4125713Shsul@eecs.umich.edu 4135231Sgblack@eecs.umich.eduvoid 41411389Sbrandon.potter@amd.comSparc64LiveProcess::argsInit(int intSize, int pageSize) 4154111Sgblack@eecs.umich.edu{ 4167741Sgblack@eecs.umich.edu SparcLiveProcess::argsInit<uint64_t>(pageSize); 4174111Sgblack@eecs.umich.edu 4184111Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4195128Sgblack@eecs.umich.edu initVirtMem.writeBlob(fillStart, 4205285Sgblack@eecs.umich.edu (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 42111851Sbrandon.potter@amd.com initVirtMem.writeBlob(spillStart, 4225285Sgblack@eecs.umich.edu (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 42311851Sbrandon.potter@amd.com} 4245285Sgblack@eecs.umich.edu 4255285Sgblack@eecs.umich.eduvoid 4268852Sandreas.hansson@arm.comSparc32LiveProcess::argsInit(int intSize, int pageSize) 4275285Sgblack@eecs.umich.edu{ 4288852Sandreas.hansson@arm.com SparcLiveProcess::argsInit<uint32_t>(pageSize); 4295285Sgblack@eecs.umich.edu 4305285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4315285Sgblack@eecs.umich.edu initVirtMem.writeBlob(fillStart, 4325285Sgblack@eecs.umich.edu (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 43311851Sbrandon.potter@amd.com initVirtMem.writeBlob(spillStart, 4345285Sgblack@eecs.umich.edu (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 43511851Sbrandon.potter@amd.com} 4365285Sgblack@eecs.umich.edu 4375285Sgblack@eecs.umich.eduvoid Sparc32LiveProcess::flushWindows(ThreadContext *tc) 4388852Sandreas.hansson@arm.com{ 4395285Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4408852Sandreas.hansson@arm.com IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4415285Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4425285Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4435285Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 44411851Sbrandon.potter@amd.com CWP = (CWP + Cansave + 2) % NWindows; 4455128Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4465128Sgblack@eecs.umich.edu if (Otherwin) { 4475128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4485128Sgblack@eecs.umich.edu } else { 4495128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4505128Sgblack@eecs.umich.edu // Do the stores 4515128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4527741Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4535128Sgblack@eecs.umich.edu uint32_t regVal = tc->readIntReg(index); 4545128Sgblack@eecs.umich.edu regVal = htog(regVal); 4555128Sgblack@eecs.umich.edu if (!tc->getMemProxy().tryWriteBlob( 4565128Sgblack@eecs.umich.edu sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 4577741Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4585128Sgblack@eecs.umich.edu "flushing windows.\n"); 4595128Sgblack@eecs.umich.edu } 4605287Sgblack@eecs.umich.edu } 4615128Sgblack@eecs.umich.edu Canrestore--; 4628852Sandreas.hansson@arm.com Cansave++; 4635128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4645128Sgblack@eecs.umich.edu } 4655128Sgblack@eecs.umich.edu } 4665128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 4675128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 4685128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 4695128Sgblack@eecs.umich.edu} 4705128Sgblack@eecs.umich.edu 4715128Sgblack@eecs.umich.eduvoid 4725128Sgblack@eecs.umich.eduSparc64LiveProcess::flushWindows(ThreadContext *tc) 4735128Sgblack@eecs.umich.edu{ 4745128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4755128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4765128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4775128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4787741Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 47911851Sbrandon.potter@amd.com CWP = (CWP + Cansave + 2) % NWindows; 4805128Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4815128Sgblack@eecs.umich.edu if (Otherwin) { 4825128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4835128Sgblack@eecs.umich.edu } else { 4845128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4855128Sgblack@eecs.umich.edu // Do the stores 4865128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4877741Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4885128Sgblack@eecs.umich.edu IntReg regVal = tc->readIntReg(index); 4895128Sgblack@eecs.umich.edu regVal = htog(regVal); 4905128Sgblack@eecs.umich.edu if (!tc->getMemProxy().tryWriteBlob( 4915128Sgblack@eecs.umich.edu sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 4927741Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4935128Sgblack@eecs.umich.edu "flushing windows.\n"); 4945128Sgblack@eecs.umich.edu } 4955128Sgblack@eecs.umich.edu } 4965128Sgblack@eecs.umich.edu Canrestore--; 4978852Sandreas.hansson@arm.com Cansave++; 4985128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4995128Sgblack@eecs.umich.edu } 5005128Sgblack@eecs.umich.edu } 5015128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 5025128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 5035128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 5045128Sgblack@eecs.umich.edu} 5055128Sgblack@eecs.umich.edu 5065128Sgblack@eecs.umich.eduIntReg 5075128Sgblack@eecs.umich.eduSparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 5085128Sgblack@eecs.umich.edu{ 5095128Sgblack@eecs.umich.edu assert(i < 6); 5105128Sgblack@eecs.umich.edu return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 5115128Sgblack@eecs.umich.edu} 5125958Sgblack@eecs.umich.edu 5135958Sgblack@eecs.umich.eduvoid 51411851Sbrandon.potter@amd.comSparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5155958Sgblack@eecs.umich.edu{ 5165958Sgblack@eecs.umich.edu assert(i < 6); 5176701Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 5185958Sgblack@eecs.umich.edu} 5195958Sgblack@eecs.umich.edu 5205958Sgblack@eecs.umich.eduIntReg 52111851Sbrandon.potter@amd.comSparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 5225958Sgblack@eecs.umich.edu{ 5235958Sgblack@eecs.umich.edu assert(i < 6); 5245958Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 5255958Sgblack@eecs.umich.edu} 5265958Sgblack@eecs.umich.edu 5275958Sgblack@eecs.umich.eduvoid 52811851Sbrandon.potter@amd.comSparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5295958Sgblack@eecs.umich.edu{ 5305958Sgblack@eecs.umich.edu assert(i < 6); 5316701Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 5325958Sgblack@eecs.umich.edu} 5335958Sgblack@eecs.umich.edu 5345958Sgblack@eecs.umich.eduvoid 53511851Sbrandon.potter@amd.comSparcLiveProcess::setSyscallReturn(ThreadContext *tc, 5365958Sgblack@eecs.umich.edu SyscallReturn return_value) 5375958Sgblack@eecs.umich.edu{ 5385958Sgblack@eecs.umich.edu // check for error condition. SPARC syscall convention is to 5395958Sgblack@eecs.umich.edu // indicate success/failure in reg the carry bit of the ccr 5405958Sgblack@eecs.umich.edu // and put the return value itself in the standard return value reg (). 5415958Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 54211851Sbrandon.potter@amd.com if (return_value.successful()) { 5435958Sgblack@eecs.umich.edu // no error, clear XCC.C 5445958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 5455958Sgblack@eecs.umich.edu tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 5465958Sgblack@eecs.umich.edu IntReg val = return_value.value(); 5478829Sgblack@eecs.umich.edu if (pstate.am) 54810223Ssteve.reinhardt@amd.com val = bits(val, 31, 0); 5495958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5505958Sgblack@eecs.umich.edu } else { 55110223Ssteve.reinhardt@amd.com // got an error, set XCC.C 55210223Ssteve.reinhardt@amd.com tc->setIntReg(NumIntArchRegs + 2, 5538829Sgblack@eecs.umich.edu tc->readIntReg(NumIntArchRegs + 2) | 0x11); 5545958Sgblack@eecs.umich.edu IntReg val = -return_value.value(); 5555958Sgblack@eecs.umich.edu if (pstate.am) 5565958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5575958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5585958Sgblack@eecs.umich.edu } 55910223Ssteve.reinhardt@amd.com} 56010223Ssteve.reinhardt@amd.com