process.cc revision 10223
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 323589Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 334111Sgblack@eecs.umich.edu#include "arch/sparc/handlers.hh" 342474SN/A#include "arch/sparc/isa_traits.hh" 358229Snate@binkert.org#include "arch/sparc/process.hh" 366335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 373760Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 388229Snate@binkert.org#include "base/loader/elf_object.hh" 392454SN/A#include "base/loader/object_file.hh" 402454SN/A#include "base/misc.hh" 412680Sktlim@umich.edu#include "cpu/thread_context.hh" 428232Snate@binkert.org#include "debug/Stack.hh" 432561SN/A#include "mem/page_table.hh" 444434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 452474SN/A#include "sim/system.hh" 462207SN/A 472458SN/Ausing namespace std; 482474SN/Ausing namespace SparcISA; 492458SN/A 505958Sgblack@eecs.umich.edustatic const int FirstArgumentReg = 8; 515958Sgblack@eecs.umich.edu 522207SN/A 535154Sgblack@eecs.umich.eduSparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 545285Sgblack@eecs.umich.edu ObjectFile *objFile, Addr _StackBias) 555285Sgblack@eecs.umich.edu : LiveProcess(params, objFile), StackBias(_StackBias) 562474SN/A{ 572474SN/A 582474SN/A // XXX all the below need to be updated for SPARC - Ali 592474SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 602474SN/A brk_point = roundUp(brk_point, VMPageSize); 612474SN/A 622474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 632474SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 643415Sgblack@eecs.umich.edu 657741Sgblack@eecs.umich.edu // Initialize these to 0s 663415Sgblack@eecs.umich.edu fillStart = 0; 673415Sgblack@eecs.umich.edu spillStart = 0; 682474SN/A} 692474SN/A 707741Sgblack@eecs.umich.eduvoid 717741Sgblack@eecs.umich.eduSparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 724111Sgblack@eecs.umich.edu{ 737720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 747741Sgblack@eecs.umich.edu switch (trapNum) { 757741Sgblack@eecs.umich.edu case 0x01: // Software breakpoint 767720Sgblack@eecs.umich.edu warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 775128Sgblack@eecs.umich.edu break; 787741Sgblack@eecs.umich.edu case 0x02: // Division by zero 797720Sgblack@eecs.umich.edu warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 805128Sgblack@eecs.umich.edu break; 817741Sgblack@eecs.umich.edu case 0x03: // Flush window trap 825128Sgblack@eecs.umich.edu flushWindows(tc); 835128Sgblack@eecs.umich.edu break; 847741Sgblack@eecs.umich.edu case 0x04: // Clean windows 855128Sgblack@eecs.umich.edu warn("Ignoring process request for clean register " 867720Sgblack@eecs.umich.edu "windows at pc %#x.\n", pc.pc()); 875128Sgblack@eecs.umich.edu break; 887741Sgblack@eecs.umich.edu case 0x05: // Range check 897720Sgblack@eecs.umich.edu warn("Software signaled a range check at pc %#x.\n", pc.pc()); 905128Sgblack@eecs.umich.edu break; 917741Sgblack@eecs.umich.edu case 0x06: // Fix alignment 925128Sgblack@eecs.umich.edu warn("Ignoring process request for os assisted unaligned accesses " 937720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 945128Sgblack@eecs.umich.edu break; 957741Sgblack@eecs.umich.edu case 0x07: // Integer overflow 967720Sgblack@eecs.umich.edu warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 975128Sgblack@eecs.umich.edu break; 987741Sgblack@eecs.umich.edu case 0x32: // Get integer condition codes 995128Sgblack@eecs.umich.edu warn("Ignoring process request to get the integer condition codes " 1007720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1015128Sgblack@eecs.umich.edu break; 1027741Sgblack@eecs.umich.edu case 0x33: // Set integer condition codes 1035128Sgblack@eecs.umich.edu warn("Ignoring process request to set the integer condition codes " 1047720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1054111Sgblack@eecs.umich.edu break; 1064111Sgblack@eecs.umich.edu default: 1074111Sgblack@eecs.umich.edu panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1084111Sgblack@eecs.umich.edu } 1094111Sgblack@eecs.umich.edu} 1104111Sgblack@eecs.umich.edu 1112474SN/Avoid 1127532Ssteve.reinhardt@amd.comSparcLiveProcess::initState() 1134111Sgblack@eecs.umich.edu{ 1147532Ssteve.reinhardt@amd.com LiveProcess::initState(); 1154111Sgblack@eecs.umich.edu 1165713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1177741Sgblack@eecs.umich.edu // From the SPARC ABI 1184111Sgblack@eecs.umich.edu 1197741Sgblack@eecs.umich.edu // Setup default FP state 1205713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1212646Ssaidi@eecs.umich.edu 1225713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1234997Sgblack@eecs.umich.edu 1242561SN/A /* 1252561SN/A * Register window management registers 1262561SN/A */ 1272561SN/A 1287741Sgblack@eecs.umich.edu // No windows contain info from other programs 1297741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1305713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 6, 0); 1317741Sgblack@eecs.umich.edu // There are no windows to pop 1327741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1335713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, 0); 1347741Sgblack@eecs.umich.edu // All windows are available to save into 1357741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 1365713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 1377741Sgblack@eecs.umich.edu // All windows are "clean" 1387741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 1395713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 5, NWindows); 1407741Sgblack@eecs.umich.edu // Start with register window 0 1416337Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, 0); 1427741Sgblack@eecs.umich.edu // Always use spill and fill traps 0 1437741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1445713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 7, 0); 1457741Sgblack@eecs.umich.edu // Set the trap level to 0 1465713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, 0); 1477741Sgblack@eecs.umich.edu // Set the ASI register to something fixed 1489375Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 1494997Sgblack@eecs.umich.edu 1504997Sgblack@eecs.umich.edu /* 1514997Sgblack@eecs.umich.edu * T1 specific registers 1524997Sgblack@eecs.umich.edu */ 1537741Sgblack@eecs.umich.edu // Turn on the icache, dcache, dtb translation, and itb translation. 1545713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1552474SN/A} 1562474SN/A 1575285Sgblack@eecs.umich.eduvoid 1587532Ssteve.reinhardt@amd.comSparc32LiveProcess::initState() 1592585SN/A{ 1607532Ssteve.reinhardt@amd.com SparcLiveProcess::initState(); 1615285Sgblack@eecs.umich.edu 1625713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1637741Sgblack@eecs.umich.edu // The process runs in user mode with 32 bit addresses 1648829Sgblack@eecs.umich.edu PSTATE pstate = 0; 1658829Sgblack@eecs.umich.edu pstate.ie = 1; 1668829Sgblack@eecs.umich.edu pstate.am = 1; 1678829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1685285Sgblack@eecs.umich.edu 1695285Sgblack@eecs.umich.edu argsInit(32 / 8, VMPageSize); 1704111Sgblack@eecs.umich.edu} 1713415Sgblack@eecs.umich.edu 1722561SN/Avoid 1737532Ssteve.reinhardt@amd.comSparc64LiveProcess::initState() 1742561SN/A{ 1757532Ssteve.reinhardt@amd.com SparcLiveProcess::initState(); 1765285Sgblack@eecs.umich.edu 1775713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1787741Sgblack@eecs.umich.edu // The process runs in user mode 1798829Sgblack@eecs.umich.edu PSTATE pstate = 0; 1808829Sgblack@eecs.umich.edu pstate.ie = 1; 1818829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1825285Sgblack@eecs.umich.edu 1835285Sgblack@eecs.umich.edu argsInit(sizeof(IntReg), VMPageSize); 1845285Sgblack@eecs.umich.edu} 1855285Sgblack@eecs.umich.edu 1865285Sgblack@eecs.umich.edutemplate<class IntType> 1875285Sgblack@eecs.umich.eduvoid 1885285Sgblack@eecs.umich.eduSparcLiveProcess::argsInit(int pageSize) 1895285Sgblack@eecs.umich.edu{ 1905285Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 1915285Sgblack@eecs.umich.edu 1925771Shsul@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 1935285Sgblack@eecs.umich.edu 1945285Sgblack@eecs.umich.edu std::vector<auxv_t> auxv; 1952474SN/A 1963044Sgblack@eecs.umich.edu string filename; 1977741Sgblack@eecs.umich.edu if (argv.size() < 1) 1983044Sgblack@eecs.umich.edu filename = ""; 1993044Sgblack@eecs.umich.edu else 2003044Sgblack@eecs.umich.edu filename = argv[0]; 2013044Sgblack@eecs.umich.edu 2027741Sgblack@eecs.umich.edu // Even for a 32 bit process, the ABI says we still need to 2037741Sgblack@eecs.umich.edu // maintain double word alignment of the stack pointer. 2045286Sgblack@eecs.umich.edu uint64_t align = 16; 2052561SN/A 2062561SN/A // load object file into target memory 2072561SN/A objFile->loadSections(initVirtMem); 2082561SN/A 2092585SN/A enum hardwareCaps 2102585SN/A { 2112585SN/A M5_HWCAP_SPARC_FLUSH = 1, 2122585SN/A M5_HWCAP_SPARC_STBAR = 2, 2132585SN/A M5_HWCAP_SPARC_SWAP = 4, 2142585SN/A M5_HWCAP_SPARC_MULDIV = 8, 2152585SN/A M5_HWCAP_SPARC_V9 = 16, 2167741Sgblack@eecs.umich.edu // This one should technically only be set 2177741Sgblack@eecs.umich.edu // if there is a cheetah or cheetah_plus tlb, 2187741Sgblack@eecs.umich.edu // but we'll use it all the time 2192585SN/A M5_HWCAP_SPARC_ULTRA3 = 32 2202585SN/A }; 2212585SN/A 2222585SN/A const int64_t hwcap = 2232585SN/A M5_HWCAP_SPARC_FLUSH | 2242585SN/A M5_HWCAP_SPARC_STBAR | 2252585SN/A M5_HWCAP_SPARC_SWAP | 2262585SN/A M5_HWCAP_SPARC_MULDIV | 2272585SN/A M5_HWCAP_SPARC_V9 | 2282585SN/A M5_HWCAP_SPARC_ULTRA3; 2292585SN/A 2307741Sgblack@eecs.umich.edu // Setup the auxilliary vectors. These will already have endian conversion. 2317741Sgblack@eecs.umich.edu // Auxilliary vectors are loaded only for elf formatted executables. 2322976Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2337741Sgblack@eecs.umich.edu if (elfObject) { 2347741Sgblack@eecs.umich.edu // Bits which describe the system hardware capabilities 2354793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 2367741Sgblack@eecs.umich.edu // The system page size 2374793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize)); 2387741Sgblack@eecs.umich.edu // Defined to be 100 in the kernel source. 2397741Sgblack@eecs.umich.edu // Frequency at which times() increments 2404793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 2412976Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2422976Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2434793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2442976Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2454793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 2462976Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 2474793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 2487741Sgblack@eecs.umich.edu // This is the address of the elf "interpreter", It should be set 2497741Sgblack@eecs.umich.edu // to 0 for regular executables. It should be something else 2507741Sgblack@eecs.umich.edu // (not sure what) for dynamic libraries. 2514793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_BASE, 0)); 2527741Sgblack@eecs.umich.edu // This is hardwired to 0 in the elf loading code in the kernel 2534793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2547741Sgblack@eecs.umich.edu // The entry point to the program 2554793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2567741Sgblack@eecs.umich.edu // Different user and group IDs 2574793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 2584793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 2594793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 2604793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2617741Sgblack@eecs.umich.edu // Whether to enable "secure mode" in the executable 2624793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 2632976Sgblack@eecs.umich.edu } 2642585SN/A 2657741Sgblack@eecs.umich.edu // Figure out how big the initial stack needs to be 2662561SN/A 2674164Sgblack@eecs.umich.edu // The unaccounted for 8 byte 0 at the top of the stack 2685286Sgblack@eecs.umich.edu int sentry_size = 8; 2694111Sgblack@eecs.umich.edu 2707741Sgblack@eecs.umich.edu // This is the name of the file which is present on the initial stack 2717741Sgblack@eecs.umich.edu // It's purpose is to let the user space linker examine the original file. 2724111Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 2734111Sgblack@eecs.umich.edu 2744111Sgblack@eecs.umich.edu int env_data_size = 0; 2754111Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 2764111Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 2774111Sgblack@eecs.umich.edu } 2784111Sgblack@eecs.umich.edu int arg_data_size = 0; 2794111Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 2804111Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 2814111Sgblack@eecs.umich.edu } 2824111Sgblack@eecs.umich.edu 2837741Sgblack@eecs.umich.edu // The info_block. 2845286Sgblack@eecs.umich.edu int base_info_block_size = 2855286Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 2865286Sgblack@eecs.umich.edu 2875286Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 2885286Sgblack@eecs.umich.edu 2895286Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 2904111Sgblack@eecs.umich.edu 2917741Sgblack@eecs.umich.edu // Each auxilliary vector is two words 2924111Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 2934111Sgblack@eecs.umich.edu 2944111Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 2954111Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 2964111Sgblack@eecs.umich.edu 2974111Sgblack@eecs.umich.edu int argc_size = intSize; 2984111Sgblack@eecs.umich.edu int window_save_size = intSize * 16; 2994111Sgblack@eecs.umich.edu 3007741Sgblack@eecs.umich.edu // Figure out the size of the contents of the actual initial frame 3015286Sgblack@eecs.umich.edu int frame_size = 3024111Sgblack@eecs.umich.edu aux_array_size + 3034111Sgblack@eecs.umich.edu envp_array_size + 3044111Sgblack@eecs.umich.edu argv_array_size + 3054111Sgblack@eecs.umich.edu argc_size + 3064111Sgblack@eecs.umich.edu window_save_size; 3074111Sgblack@eecs.umich.edu 3087741Sgblack@eecs.umich.edu // There needs to be padding after the auxiliary vector data so that the 3097741Sgblack@eecs.umich.edu // very bottom of the stack is aligned properly. 3105286Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(frame_size, align); 3115286Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3125286Sgblack@eecs.umich.edu 3135286Sgblack@eecs.umich.edu int space_needed = 3145286Sgblack@eecs.umich.edu info_block_size + 3155286Sgblack@eecs.umich.edu aux_padding + 3165286Sgblack@eecs.umich.edu frame_size; 3175286Sgblack@eecs.umich.edu 3184111Sgblack@eecs.umich.edu stack_min = stack_base - space_needed; 3195286Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, align); 3204111Sgblack@eecs.umich.edu stack_size = stack_base - stack_min; 3214111Sgblack@eecs.umich.edu 3225285Sgblack@eecs.umich.edu // Allocate space for the stack 3238601Ssteve.reinhardt@amd.com allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 3244111Sgblack@eecs.umich.edu 3254111Sgblack@eecs.umich.edu // map out initial stack contents 3265286Sgblack@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 3275286Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 3285286Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3295286Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3305286Sgblack@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3315286Sgblack@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3325286Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 3335286Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 3345286Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3355286Sgblack@eecs.umich.edu#if TRACING_ON 3365286Sgblack@eecs.umich.edu IntType window_save_base = argc_base - window_save_size; 3375286Sgblack@eecs.umich.edu#endif 3384111Sgblack@eecs.umich.edu 3395941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3405941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 3415941Sgblack@eecs.umich.edu DPRINTF(Stack, "filename = %s\n", filename); 3425941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - file name\n", file_name_base); 3435941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - env data\n", env_data_base); 3445941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 3455941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 3465941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 3475941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 3485941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argc \n", argc_base); 3495941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - window save\n", window_save_base); 3505941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - stack min\n", stack_min); 3514111Sgblack@eecs.umich.edu 3525286Sgblack@eecs.umich.edu assert(window_save_base == stack_min); 3535286Sgblack@eecs.umich.edu 3544111Sgblack@eecs.umich.edu // write contents to stack 3554111Sgblack@eecs.umich.edu 3564111Sgblack@eecs.umich.edu // figure out argc 3575285Sgblack@eecs.umich.edu IntType argc = argv.size(); 3585567Snate@binkert.org IntType guestArgc = SparcISA::htog(argc); 3594111Sgblack@eecs.umich.edu 3607741Sgblack@eecs.umich.edu // Write out the sentry void * 3615286Sgblack@eecs.umich.edu uint64_t sentry_NULL = 0; 3628852Sandreas.hansson@arm.com initVirtMem.writeBlob(sentry_base, 3635286Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3644111Sgblack@eecs.umich.edu 3657741Sgblack@eecs.umich.edu // Write the file name 3668852Sandreas.hansson@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 3674111Sgblack@eecs.umich.edu 3687741Sgblack@eecs.umich.edu // Copy the aux stuff 3697741Sgblack@eecs.umich.edu for (int x = 0; x < auxv.size(); x++) { 3708852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 3714111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 3728852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 3734111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 3744111Sgblack@eecs.umich.edu } 3755285Sgblack@eecs.umich.edu 3767741Sgblack@eecs.umich.edu // Write out the terminating zeroed auxilliary vector 3775285Sgblack@eecs.umich.edu const IntType zero = 0; 3788852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 3795286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3808852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 3815286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3824111Sgblack@eecs.umich.edu 3834117Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 3844117Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 3854111Sgblack@eecs.umich.edu 3868852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 3874111Sgblack@eecs.umich.edu 3887741Sgblack@eecs.umich.edu // Set up space for the trap handlers into the processes address space. 3897741Sgblack@eecs.umich.edu // Since the stack grows down and there is reserved address space abov 3907741Sgblack@eecs.umich.edu // it, we can put stuff above it and stay out of the way. 3914111Sgblack@eecs.umich.edu fillStart = stack_base; 3925285Sgblack@eecs.umich.edu spillStart = fillStart + sizeof(MachInst) * numFillInsts; 3934111Sgblack@eecs.umich.edu 3945713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 3957741Sgblack@eecs.umich.edu // Set up the thread context to start running the process 3967741Sgblack@eecs.umich.edu // assert(NumArgumentRegs >= 2); 3977741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[0], argc); 3987741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[1], argv_array_base); 3995713Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min - StackBias); 4004111Sgblack@eecs.umich.edu 4015231Sgblack@eecs.umich.edu // %g1 is a pointer to a function that should be run at exit. Since we 4025231Sgblack@eecs.umich.edu // don't have anything like that, it should be set to 0. 4035713Shsul@eecs.umich.edu tc->setIntReg(1, 0); 4045231Sgblack@eecs.umich.edu 4057720Sgblack@eecs.umich.edu tc->pcState(objFile->entryPoint()); 4064111Sgblack@eecs.umich.edu 4077741Sgblack@eecs.umich.edu // Align the "stack_min" to a page boundary. 4084111Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 4094111Sgblack@eecs.umich.edu 4104111Sgblack@eecs.umich.edu// num_processes++; 4114111Sgblack@eecs.umich.edu} 4125128Sgblack@eecs.umich.edu 4135285Sgblack@eecs.umich.eduvoid 4145285Sgblack@eecs.umich.eduSparc64LiveProcess::argsInit(int intSize, int pageSize) 4155285Sgblack@eecs.umich.edu{ 4165285Sgblack@eecs.umich.edu SparcLiveProcess::argsInit<uint64_t>(pageSize); 4175285Sgblack@eecs.umich.edu 4185285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4198852Sandreas.hansson@arm.com initVirtMem.writeBlob(fillStart, 4205285Sgblack@eecs.umich.edu (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 4218852Sandreas.hansson@arm.com initVirtMem.writeBlob(spillStart, 4225285Sgblack@eecs.umich.edu (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 4235285Sgblack@eecs.umich.edu} 4245285Sgblack@eecs.umich.edu 4255285Sgblack@eecs.umich.eduvoid 4265285Sgblack@eecs.umich.eduSparc32LiveProcess::argsInit(int intSize, int pageSize) 4275285Sgblack@eecs.umich.edu{ 4285285Sgblack@eecs.umich.edu SparcLiveProcess::argsInit<uint32_t>(pageSize); 4295285Sgblack@eecs.umich.edu 4305285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4318852Sandreas.hansson@arm.com initVirtMem.writeBlob(fillStart, 4325285Sgblack@eecs.umich.edu (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 4338852Sandreas.hansson@arm.com initVirtMem.writeBlob(spillStart, 4345285Sgblack@eecs.umich.edu (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 4355285Sgblack@eecs.umich.edu} 4365285Sgblack@eecs.umich.edu 4375128Sgblack@eecs.umich.eduvoid Sparc32LiveProcess::flushWindows(ThreadContext *tc) 4385128Sgblack@eecs.umich.edu{ 4395128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4405128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4415128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4425128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4435128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4445128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4457741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4465128Sgblack@eecs.umich.edu if (Otherwin) { 4475128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4485128Sgblack@eecs.umich.edu } else { 4495128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4507741Sgblack@eecs.umich.edu // Do the stores 4515128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4525128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4535287Sgblack@eecs.umich.edu uint32_t regVal = tc->readIntReg(index); 4545128Sgblack@eecs.umich.edu regVal = htog(regVal); 4558852Sandreas.hansson@arm.com if (!tc->getMemProxy().tryWriteBlob( 4565128Sgblack@eecs.umich.edu sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 4575128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4585128Sgblack@eecs.umich.edu "flushing windows.\n"); 4595128Sgblack@eecs.umich.edu } 4605128Sgblack@eecs.umich.edu } 4615128Sgblack@eecs.umich.edu Canrestore--; 4625128Sgblack@eecs.umich.edu Cansave++; 4635128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4645128Sgblack@eecs.umich.edu } 4655128Sgblack@eecs.umich.edu } 4665128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 4675128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 4685128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 4695128Sgblack@eecs.umich.edu} 4705128Sgblack@eecs.umich.edu 4717741Sgblack@eecs.umich.eduvoid 4727741Sgblack@eecs.umich.eduSparc64LiveProcess::flushWindows(ThreadContext *tc) 4735128Sgblack@eecs.umich.edu{ 4745128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4755128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4765128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4775128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4785128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4795128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4807741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4815128Sgblack@eecs.umich.edu if (Otherwin) { 4825128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4835128Sgblack@eecs.umich.edu } else { 4845128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4857741Sgblack@eecs.umich.edu // Do the stores 4865128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4875128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4885128Sgblack@eecs.umich.edu IntReg regVal = tc->readIntReg(index); 4895128Sgblack@eecs.umich.edu regVal = htog(regVal); 4908852Sandreas.hansson@arm.com if (!tc->getMemProxy().tryWriteBlob( 4915128Sgblack@eecs.umich.edu sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 4925128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4935128Sgblack@eecs.umich.edu "flushing windows.\n"); 4945128Sgblack@eecs.umich.edu } 4955128Sgblack@eecs.umich.edu } 4965128Sgblack@eecs.umich.edu Canrestore--; 4975128Sgblack@eecs.umich.edu Cansave++; 4985128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4995128Sgblack@eecs.umich.edu } 5005128Sgblack@eecs.umich.edu } 5015128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 5025128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 5035128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 5045128Sgblack@eecs.umich.edu} 5055958Sgblack@eecs.umich.edu 5065958Sgblack@eecs.umich.eduIntReg 5076701Sgblack@eecs.umich.eduSparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 5085958Sgblack@eecs.umich.edu{ 5095958Sgblack@eecs.umich.edu assert(i < 6); 5106701Sgblack@eecs.umich.edu return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 5115958Sgblack@eecs.umich.edu} 5125958Sgblack@eecs.umich.edu 5135958Sgblack@eecs.umich.eduvoid 5145958Sgblack@eecs.umich.eduSparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5155958Sgblack@eecs.umich.edu{ 5165958Sgblack@eecs.umich.edu assert(i < 6); 5175958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 5185958Sgblack@eecs.umich.edu} 5195958Sgblack@eecs.umich.edu 5205958Sgblack@eecs.umich.eduIntReg 5216701Sgblack@eecs.umich.eduSparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 5225958Sgblack@eecs.umich.edu{ 5235958Sgblack@eecs.umich.edu assert(i < 6); 5246701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 5255958Sgblack@eecs.umich.edu} 5265958Sgblack@eecs.umich.edu 5275958Sgblack@eecs.umich.eduvoid 5285958Sgblack@eecs.umich.eduSparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5295958Sgblack@eecs.umich.edu{ 5305958Sgblack@eecs.umich.edu assert(i < 6); 5315958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 5325958Sgblack@eecs.umich.edu} 5335958Sgblack@eecs.umich.edu 5345958Sgblack@eecs.umich.eduvoid 53510223Ssteve.reinhardt@amd.comSparcLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 5365958Sgblack@eecs.umich.edu{ 5375958Sgblack@eecs.umich.edu // check for error condition. SPARC syscall convention is to 5385958Sgblack@eecs.umich.edu // indicate success/failure in reg the carry bit of the ccr 5395958Sgblack@eecs.umich.edu // and put the return value itself in the standard return value reg (). 5408829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 54110223Ssteve.reinhardt@amd.com if (sysret.successful()) { 5425958Sgblack@eecs.umich.edu // no error, clear XCC.C 5435958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 54410223Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 54510223Ssteve.reinhardt@amd.com IntReg val = sysret.returnValue(); 5468829Sgblack@eecs.umich.edu if (pstate.am) 5475958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5485958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5495958Sgblack@eecs.umich.edu } else { 5505958Sgblack@eecs.umich.edu // got an error, set XCC.C 5515958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 55210223Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) | 0x11); 55310223Ssteve.reinhardt@amd.com IntReg val = sysret.errnoValue(); 5548829Sgblack@eecs.umich.edu if (pstate.am) 5555958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5565958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5575958Sgblack@eecs.umich.edu } 5585958Sgblack@eecs.umich.edu} 559